CN120185608A

CN120185608A - A phase calibration system for phase interpolation circuit

Info

Publication number: CN120185608A
Application number: CN202510197478.6A
Authority: CN
Inventors: 刘畅; 胡韬; 李博; 罗骞; 苏泽鑫; 马骁
Original assignee: Institute of Microelectronics of CAS
Current assignee: Institute of Microelectronics of CAS
Priority date: 2025-02-21
Filing date: 2025-02-21
Publication date: 2025-06-20

Abstract

The present invention discloses a phase calibration system for a phase interpolation circuit, which relates to the technical field of integrated circuits, and includes a reference circuit and a circuit to be calibrated; the reference circuit and the circuit to be calibrated have the same structure; the reference circuit or the circuit to be calibrated includes a current-type digital-to-analog converter, a phase interpolation module, and a phase combination module; the phase interpolation module includes a PIA module and a PIB module; the current-type digital-to-analog converter is connected to the phase interpolation module, and the current-type digital-to-analog converter provides current for the phase interpolation module; the phase combination module is connected to the phase interpolation module to calibrate a clock phase of 45° and its integer multiples to a standard phase. The present invention adopts a dual-phase interpolator architecture, and compensates for the linearity loss of the phase interpolator by using the complementary principle of nonlinear trends of clocks separated by π/4 under an orthogonal reference clock input.

Description

Phase calibration system for phase interpolation circuit

Technical Field

The present invention relates to the field of integrated circuits, and in particular, to a phase calibration system for a phase interpolation circuit.

Background

Communication is an important means for human interaction, along with the development of network technology, the demands of people for information propagation speed are becoming more stringent, along with the rapid development of semiconductor technology, the complexity and communication rate of integrated circuits are continuously improved, and how to realize high-speed communication is one of the important directions of modern communication research. The conventional parallel transmission technology takes the dominant role in short-distance interconnection, and can simultaneously transmit multiple paths of data, but clock signals are synchronously transmitted, in addition, as the rate is increased, crosstalk between transmission lines and timing offset become more serious, compared with parallel transmission, the serial transmission scheme adopts various measures to improve the problems of crosstalk, timing offset and the like, such as adopting differential signals to replace single-ended signals, enhancing noise resistance, and adopts a clock recovery technology to avoid the problem that clock signals are seriously offset due to additional transmission of clock signals while data is transmitted. Serial transceiver SerDes is an abbreviation of Serializer/Deserializer, a communication technology incorporating time division multiplexing, point-to-point links, and is an integral component of many communication protocols. The phase interpolation circuit is used as a core module of a phase interpolation type clock data recovery circuit (PI-CDR), and the high linearity has important significance in the aspects of improving the performance of a circuit system, reducing signal distortion, improving communication quality and the like. From the main stream research and product iteration direction analysis in academia and industry, the phase interpolation circuit mainly develops towards the high speed, high precision and low power consumption direction.

Therefore, it is desirable to provide a more reliable bi-phase interpolation circuit and phase calibration scheme thereof.

Disclosure of Invention

The invention aims to provide a phase calibration system for a phase interpolation circuit, which is used for solving the problem of linearity loss caused by a tail current source linear coding strategy and the problem of amplitude error phase-shifting error in the current mode clock signal amplifying process in the current mode phase interpolation circuit in the prior art.

In order to achieve the above object, the present invention provides the following technical solutions:

in a first aspect, the present invention provides a phase calibration system for a phase interpolation circuit, the system comprising at least:

The circuit comprises a reference circuit and a circuit to be calibrated, wherein the reference circuit and the circuit to be calibrated have the same structure;

the reference circuit or the circuit to be calibrated comprises a current type digital-to-analog converter, a phase interpolation module and a phase combination module;

The current type digital-to-analog converter is connected with the phase interpolation module and provides current for the phase interpolation module;

The phase combination module is connected with the phase interpolation module and is used for calibrating the clock phase of 45 degrees and the clock phase of integer multiples thereof to a standard phase.

Optionally, the system further comprises:

A CML2CMOS module;

the phase combination module is connected with the CML2CMOS module, and the CML2CMOS module is used for amplifying the current mode signal to the full-amplitude square wave signal.

Optionally, the PIA module and the PIB module respectively receive the 0 ° reference clock, the 90 ° reference clock, the 180 ° reference clock and the 270 ° reference clock as reference input clocks, and realize phase synthesis by controlling on-off of tail current switches of the four differential pairs, so as to generate differential interpolation clock output.

Optionally, the phase combination module is configured to apply a compensation mode of a bi-phase interpolator architecture to the PIA module and the PIB module, respectively, and enable a phase difference of 45 ° between the PIA and the PIB module through the current-mode digital-to-analog converter.

Optionally, the system further comprises:

the calibration logic module is connected with the current type digital-to-analog converter;

The current type digital-to-analog converter is used as the tail current input of the phase interpolation module, and a 9bit control word is used for providing current for the phase interpolation module in a sectional mode, wherein the 9bit control word comprises a high two-bit system code and a low seven-bit total temperature meter code, the high two-bit system code is used for controlling the on-off of tail current sources of four differential pairs, the low seven-bit total temperature meter code is used for controlling the proportion of interpolation current, and the proportion regulation and control of 127 phases within a 90-degree range are completed;

And each section of the low seven-bit thermometer code inputs mutually independent reference current, the reference current comprises two paths of 4-bit adjustable current calibration branches, and the current on-off of the adjustable branches is controlled through the output result of the current type digital-to-analog converter.

Optionally, the reference circuit identifies and corrects the worst linearity shown on the clock phase of 45 ° and integer multiples thereof, provides the reference clock phase by using the copied phase interpolation module as a reference, divides the 127bit thermometer code into four parts in each 90 ° range, and obtains the reference clock of the two-phase standard by adjusting the current type digital-to-analog converter input reference current size and the current ratio of the two paths of I/Q of the specific part, thereby being used for correcting the intermediate phase clock of the phase interpolation module in the circuit to be corrected;

the reference clock of the two-phase standard is obtained by selecting the initial current size and the current proportion of two paths of I/Q (input/output) for generating a preset two-phase clock, wherein the preset two-phase clock is an adjacent clock separated by 45 degrees.

Optionally, the current-mode digital-to-analog converters in the circuit to be calibrated and the reference circuit respectively comprise two current-mode digital-to-analog converters;

In the calibration process, normalization statistics are carried out at a control word 0, when the control word is 32, a clock representing 22.5 degrees of phase is generated, a 31-bit thermometer code switch of a first part of current type digital-to-analog converter in the circuit to be calibrated is opened, when the control word is 480, a 337.5 degrees of clock is generated, a 31-bit thermometer code current branch switch of the first part of current type digital-to-analog converter in the circuit to be calibrated is closed, the other three parts of thermometer codes are opened, and the control word 0 represents 0 degrees of phase.

Optionally, gates of the first transistor and the fourth transistor in the phase interpolation module input 0 ° clocks, gates of the second transistor and the third transistor input 180 ° clocks, and phase synthesis is performed within 360 ° by selecting reference clocks of two paths of I/Q;

in the phase combination module, the gates of the first transistor and the third transistor are respectively connected with the negative electrode of an input clock, the gates of the second transistor and the fourth transistor are connected with the positive electrode of the clock, the voltage signal with phase information is converted into a source leakage current signal with phase information in a differential pair, and vector superposition is performed on a load resistor.

Optionally, in the power-on starting stage, the control position of the current type digital-to-analog converter is set to 0, the calibration control word is set to 0, the circuit is powered on, each module in the system is initialized and establishes a steady state, and the current type digital-to-analog converter generates a reference current;

In the 0-degree clock phase calibration stage, enabling the calibration logic module to set 1, starting a calibration process by a circuit, calibrating a clock phase representing 0 degree and integer multiples thereof, switching an input control word of a phase interpolation module to be calibrated in the circuit to be calibrated to 0, setting a first input control word by a reference phase interpolation module in the reference circuit, providing a first two-phase clock as a reference, providing the 0-degree clock by the phase interpolation module to be calibrated, adjusting the clock phase by an adjustable current type digital-analog converter containing 4-bit calibration bits until a first preset condition is met, and determining that the current error exceeds a calibration range, wherein the first preset condition represents that a done0 signal representing that 0-degree clock calibration is completed is set 1, or the first preset condition represents that the 4-bit current type digital-analog converter control bits are all opened or closed.

Optionally, in the phase calibration stage of the 45 ° clock, after the 0 ° clock calibration is completed, the input control word of the phase interpolation module to be calibrated is changed into a second input control word, the second input control word represents the 45 ° clock, the control word of the reference phase interpolation module is changed into a third input control word, the second two-phase clock is provided as a reference, the phase interpolation module to be calibrated provides the 45 ° clock, and the phase of the clock is adjusted by the adjustable current type digital-analog converter containing 4bit calibration bits until a second preset condition is met, so as to determine that the current error exceeds the calibration range;

And in the calibration ending stage, the calibration logic module is used for controlling the position 0, updating the calibration control word of the current type digital-to-analog converter, switching the system into an external control word input again, and carrying out clock phase modulation after calibration.

Compared with the prior art, the phase calibration system for the phase interpolation circuit is provided by the invention. The circuit comprises a reference circuit and a circuit to be calibrated, the reference circuit and the circuit to be calibrated are the same in structure, the reference circuit or the circuit to be calibrated comprise a current type digital-to-analog converter, a phase interpolation module and a phase combination module, the phase interpolation module comprises a PIA module and a PIB module, the current type digital-to-analog converter is connected with the phase interpolation module and supplies current to the phase interpolation module, and the phase combination module is connected with the phase interpolation module and is used for calibrating a clock phase of 45 degrees and a clock phase of integer multiples thereof to a standard phase. Based on a reference circuit and PIA modules and PIB modules in a circuit to be calibrated, a dual-phase interpolator architecture is adopted, and the linearity loss of the phase interpolator is compensated by a clock nonlinear trend complementation principle of pi/4 intervals under the input of a quadrature reference clock. The method solves the problem of linearity loss caused by a tail current source linear coding strategy in a current mode phase interpolation circuit and the problem of amplitude error (AM) phase inversion error (PM) in the current mode clock signal amplifying process.

Drawings

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and do not constitute a limitation on the invention. In the drawings:

FIG. 1 is a schematic diagram of a phase interpolation circuit of a conventional current mode structure in the prior art;

FIG. 2 is a schematic diagram of a prior art linear code phase interpolation circuit geometry model;

FIG. 3 is a schematic diagram of a phase interpolation circuit of a non-equivalent tail current source according to the first prior art;

FIG. 4 is a block diagram of a high-order coefficient fitting phase interpolation circuit system provided in the second prior art;

FIG. 5 is a diagram of a phase calibration system for a phase interpolation circuit according to the present invention;

FIG. 6 is a schematic diagram of a dual phase interpolator according to the present invention;

fig. 7 is a schematic diagram of a phase interpolation module according to the present invention;

fig. 8 is a schematic diagram of a phase combining module structure according to the present invention;

FIG. 9 is a block diagram of a current mode digital to analog converter according to the present invention;

FIG. 10 is a schematic diagram of an intermediate phase error provided by the present invention;

FIG. 11 is a logic diagram of a calibration process according to the present invention;

FIG. 12 (a) is a diagram of the clock signal before compensation of the dual phase interpolator architecture provided by the present invention;

FIG. 12 (b) is a diagram of the clock signal after the compensation of the dual phase interpolator architecture provided by the present invention;

FIG. 13 (a) is a diagram showing eight clock signals before calibration according to the present invention;

FIG. 13 (b) is a diagram showing eight clock signals after calibration according to the present invention;

FIG. 14 is a schematic diagram of differential nonlinear statistics;

FIG. 15 is a diagram of a calibration clock phase range according to the present invention;

fig. 16 is an INL comparison schematic diagram of a phase interpolation module and a conventional phase interpolation module according to the present invention.

Reference numerals:

the device comprises a 1-reference circuit, a 2-circuit to be calibrated, a 3-CML2CMOS module, a 4-calibration logic module, a 101-current type digital-to-analog converter, a 102-phase interpolation module and a 103-phase combination module.

Detailed Description

In order to clearly describe the technical solution of the embodiments of the present invention, in the embodiments of the present invention, the words "first", "second", etc. are used to distinguish the same item or similar items having substantially the same function and effect. For example, the first threshold and the second threshold are merely for distinguishing between different thresholds, and are not limited in order. It will be appreciated by those of skill in the art that the words "first," "second," and the like do not limit the amount and order of execution, and that the words "first," "second," and the like do not necessarily differ.

In the present invention, the words "exemplary" or "such as" are used to mean serving as an example, instance, or illustration. Any embodiment or design described herein as "exemplary" or "for example" should not be construed as preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "such as" is intended to present related concepts in a concrete fashion.

In the present invention, "at least one" means one or more, and "a plurality" means two or more. "and/or" describes an association of associated objects, meaning that there may be three relationships, e.g., A and/or B, and that there may be A alone, while A and B are present, and B alone, where A, B may be singular or plural. The character "/" generally indicates that the context-dependent object is an "or" relationship. "at least one of" or the like means any combination of these items, including any combination of single item(s) or plural items(s). For example, at least one (a, b or c) of a, b, c, a and b combination, a and c combination, b and c combination, or a, b and c combination, wherein a, b and c can be single or multiple.

First, definitions of abbreviations, english and key terms appearing in the embodiments of the present specification will be described:

1. SerDes: serizer/Deserializer, serializer/Deserializer

2. RX receiver

3. CDR clock data recovery circuit

4. CML Current mode

5. CMOS full amplitude level signal

6. LSB least significant bit

7. INI integral nonlinearity

8. DNL differential nonlinearity

9. AM-PM amplitude to phase transition

10. Dual-PI (proportional-integral) bi-phase interpolator

11. IDAC current type D/A converter

12. PVT process voltage temperature

13. I/Q, quadrature.

At present, the structure of a phase interpolation circuit applied to a high-speed circuit is generally shown in fig. 1, wherein fig. 1 shows the basic structure of interpolation of a traditional current mode circuit, and the principle of phase interpolation is deduced by analysis of the following formula:

Pa=A₁sin(ω_int) (1)

In the above formulas (1) - (3), pa and Pb are input reference clocks, A1 and A2 are amplitude coefficients of two initial clocks, ω _in is the input reference clock frequency, For an initial phase difference of the two input reference clocks, in equation (3):

equations (1) - (5) represent the basic principle of phase interpolation, namely the synthesis formula of trigonometric function, and under the condition that the initial angle of the reference clocks is fixed, the coefficient weights of two phases A1 and A2 are adjusted, so that any phase clock between the two reference clocks is obtained. But in circuit design, coefficients are implemented It is not easy, and a more common solution is to use a linear coding strategy of |a ₁|+|A₂ |=1 to implement a change in the weight coefficient of the phase. The strategy of linear substitution is easy to implement in circuit design, but also brings about the problem of serious linearity degradation of the output clock signal, fig. 2 shows a mathematical geometric model of linear coding and phase interpolation under ideal conditions, and it can be seen that the equivalent square on the linear coding geometry approximately replaces a circle, and the linearity degradation is most serious at an angle of 45 degrees and integer multiples thereof.

In order to solve the problem, in the first prior art, a non-equivalent tail current source coding mode is adopted, and according to the analysis, the linear weight coding can cause the increment of the phase to be in a sine change trend, then the expression of theta is reversely solved, the change proportion of the input weight is obtained under the condition that the output phase is approximately linearly changed, the linearity error is counteracted by adopting a weight coding mode of fitting sine, the linearity of the clock at the output end is further improved, and therefore the problems of circuit complexity and linearity trade-off in the traditional interpolation circuit are solved, fig. 3 shows a phase interpolation circuit structure diagram based on the non-equivalent tail current source, the grids of differential pairs M1, M2, M3 and M4 are respectively connected with reference clock signals, binary coding is carried out on the tail current arrays of the two differential pairs, the more the number of coding bits is, the finer weight change trend is closer to sine, and the linearity of the output clock is better.

However, the non-equivalent tail current source interpolation scheme can improve the linearity loss of the circuit to a certain extent, but has certain defects, firstly, the cost of designing a high-precision binary current type digital-to-analog converter is higher, secondly, the scheme can realize the requirement of linearity compensation for a low-speed circuit with low phase resolution requirement, but the requirement of the circuit for the linearity of a clock signal is higher for the high-speed high-precision design requirement, if a nonlinear fitting mode is adopted, the realization cost of the circuit is greatly increased, and meanwhile, for PVT change, the designed weight is likely to fluctuate and deviate from the proportion of the initial design, so that the linearity is deteriorated.

Another solution is to perform trigonometric function fitting on the higher order current coefficients, and essentially also to adjust the current source duty cycle weight, thereby improving the problem of nonlinear response. The left diagram of fig. 4 is a composition structure of the phase interpolator, and mainly comprises a coefficient coding circuit, a current mirror array and a phase synthesis circuit. The right-hand diagram of fig. 4 is a block diagram of this structure. The main idea of the scheme is that according to a current mirror image array sub-circuit, a current corresponding to an approximate coefficient of a corresponding row of control words is generated according to a first weight, a second weight, a third weight and a fourth weight, wherein the first weight is a weight of a preset bias current, the second weight, the third weight and the fourth weight are weights corresponding to a first-order coefficient, a second-order coefficient and a third-order coefficient in the row of control words respectively, and compared with the first-order coefficient which is directly regulated linearly, the amplitude error after the third-order combination can be reduced to 6.5%.

However, the nature of the high-order current coefficient fitting method is that the current is also weighted and the problem of complex circuit under high resolution still exists, in addition, although the amplitude error of the third-order coefficient fitting is reduced to 6.5%, the value is measured and calculated only under the current mode signal, and as the clock signal sampled in the CDR circuit, the current needs to be amplified to the rail-to-rail clock through the CML2CMOS module, and in the process, the linearity is further deteriorated, namely the amplitude error (AM) phase-shift error (PM).

In view of the drawbacks of the prior art, the present invention provides a phase calibration system for a phase interpolation circuit. Next, the scheme provided by the embodiments of the present specification will be described with reference to the accompanying drawings:

as shown in fig. 5, the system may include:

the circuit comprises a reference circuit 1 and a circuit to be calibrated 2, wherein the reference circuit 1 and the circuit to be calibrated 2 have the same structure;

The reference circuit 1 or the circuit to be calibrated 2 comprises a current type digital-to-analog converter 101, a phase interpolation module 102 and a phase combination module 103;

The current type digital-to-analog converter 101 is connected with the phase interpolation module 102, and the current type digital-to-analog converter 101 provides current for the phase interpolation module 102;

the phase combination module 103 is connected to the phase interpolation module 102, and calibrates the clock phase of 45 ° and the clock phase of integer multiples thereof to a standard phase.

The system may further include:

a CML2CMOS module 3;

The phase combination module 103 is connected with the CML2CMOS module 3, and the CML2CMOS module 3 is used for amplifying a current mode signal to a full-amplitude square wave signal;

and the calibration logic module 4 is connected with the current type digital-to-analog converter 101.

Among them, a Current type Digital-to-Analog Converter (IDAC) 101 generates an Analog voltage by changing a Current flowing through a resistor, thereby realizing Digital-to-Analog conversion.

The phase interpolation module 102PI (Phase Interpolator) plays an important role in high-speed digital-analog hybrid circuits (e.g., phase-locked loop PLL circuits, clock data recovery CDR circuits, serial link transceivers, etc.).

A Phase combining module 103 (Phase Combiner) combines a plurality of signals having different phases to generate an output signal having a specific Phase relationship.

In the system shown in fig. 5, a reference circuit 1 and a circuit 2 to be calibrated are arranged, the reference circuit 1 and the circuit 2 to be calibrated have the same structure, the reference circuit 1 or the circuit 2 to be calibrated respectively comprise a current type digital-to-analog converter 101, a phase interpolation module 102 and a phase combination module 103, the phase interpolation module 102 comprises a PIA module and a PIB module, the current type digital-to-analog converter 101 is connected with the phase interpolation module 102, the current type digital-to-analog converter 101 supplies current for the phase interpolation module 102, and the phase combination module 103 is connected with the phase interpolation module 102 to calibrate a clock phase of 45 degrees and a clock phase of an integer multiple thereof to a standard phase. Based on the PIA module and the PIB module in the reference circuit 1 and the circuit to be calibrated 2, a dual-phase interpolator architecture is adopted, and the linearity loss of the phase interpolator is compensated by the clock nonlinear trend complementation principle of pi/4 intervals under the input of a quadrature reference clock. The method solves the problem of linearity loss caused by a tail current source linear coding strategy in a current mode phase interpolation circuit and the problem of amplitude error (AM) phase inversion error (PM) in the current mode clock signal amplifying process.

Based on the system of fig. 5, some specific structures and specific implementations of the system are also provided in the embodiments of the present disclosure, and are described below.

For the phase interpolation module 102 in fig. 5, a Dual-phase interpolator (Dual-PI) architecture is used, as shown in fig. 6, to compensate for the linearity loss of the phase interpolator by using the principle of clock nonlinear trend complementation of PI/4 at intervals under the input of the quadrature reference clock, in fig. 6, the PIA module is connected to the IDAC of the first part, and the PIB module is connected to the IDAC of the second part, and the two IDACs supply currents to the PIA module and the PIB module. The circuit structure of the phase interpolation module 102 is shown in fig. 7, and the phase interpolation module 102 mainly includes eight transistors (M1-M8) and two load resistors (R1, R2).

As shown in fig. 5, four reference clocks of 0 °,90 °,180 ° and 270 ° are input to the PIA module and the PIB module, respectively, as reference input clocks.

In the phase combining module 103, the gates of the first transistor and the third transistor are respectively connected with the negative electrode of an input clock, the gates of the second transistor and the fourth transistor are connected with the positive electrode of the clock, a voltage signal with phase information is converted into a source leakage current signal with phase information in a differential pair, and vector superposition is performed on a load resistor.

More specifically, the purpose of selecting the reference clocks of two paths of I/Q, such as 0 degree and 90 degrees, 90 degrees and 180 degrees, 180 degrees and 270 degrees and 0 degrees, and realizing phase synthesis within the range of 360 degrees is realized by controlling the on-off of tail current switches of four differential pairs. The current mode signal with phase information is subjected to vector superposition on the load resistors R1 and R2 and converted into a synthesized vector voltage signal, and differential interpolation clocks CKN and CKP are generated and output.

For the phase combination module 103 in fig. 5, the structure of the phase combination module 103 is shown in fig. 8, the PIA and the PIB adopt a Dual-PI compensation mode, wherein two IDACs providing currents for the PIA and the PIB respectively, the control words differ by 64 steps, that is, the phases of the two are always 45 degrees out of phase, the linearity loss caused by the linear interpolation weight control strategy is compensated through the complementary nonlinear trend of the two, the clock signals separated by 45 degrees are vector synthesized on the phase combination module 103, the gates of M1 and M3 are respectively connected with an input clock negative stage, the gates of M2 and M4 are connected with a clock positive stage, the voltage signals with phase information are converted into source leakage current signals with phase information in a differential pair, and vector superposition is performed on the load resistors R1 and R2.

For the current-type digital-to-analog converter 101 (IDAC) in fig. 5, the current-type digital-to-analog converter 101 is used as the tail current input of the phase interpolation module 102, a 9-bit control word sectional type is used for providing current for the phase interpolation module 102, the 9-bit control word sectional type comprises a high two-bit system code and a low seven-bit total temperature code, the high two-bit system code is used for controlling the on-off of tail current sources of four differential pairs, the low seven-bit total temperature code is used for controlling the proportion of interpolation current to complete the proportion regulation of 127 phases within a 90-degree range, each section of the low seven-bit temperature code inputs mutually independent reference current, the reference current comprises two paths of 4-bit adjustable current calibration branches, and the on-off of the current of the adjustable branches is controlled through the output result of the current-type digital-to-analog converter 101.

Specifically, the current-mode digital-to-analog converter 101 in fig. 5 adopts a fully customized IDAC array mode, the IDAC structure is shown in fig. 9, the IDAC of fig. 9 is used as the tail current input of the phase interpolation module 102, a 9bit control word sectional design is adopted, wherein the upper two bits adopt binary codes to control the on-off of tail current sources of four differential pairs and select the reference clock phase of an access circuit, the lower seven bits adopt a full thermometer code design as the control bit of the phase weight to control the proportion of interpolation current, so that the proportion regulation of 127 phases within the 90-degree range is realized, the conversion error can be effectively reduced, and the linearity and the switching noise are improved.

The 7bit control 127 thermometer code outputs are divided into 31,32,32,32 four sections, each section inputs mutually independent reference current, the reference current comprises two paths of 4bit adjustable current calibration branches, and the current on-off of the adjustable branches is controlled through a calibration logic output result. The 4bit control word is divided into 16 gears, so that nonlinear response of an output clock within a 22.5 DEG degree range is finely fitted, and linearity loss is compensated. The circuitry is a quarter-rate architecture that uses four phase interpolators to simultaneously generate eight clock signals CLK <7:0> spaced 45 degrees apart.

Fig. 12 (a) is a clock signal diagram before the compensation of the dual-phase interpolator structure provided by the invention, and fig. 12 (b) is a clock signal diagram after the compensation of the dual-phase interpolator structure provided by the invention, which shows the amplitude error of the phase interpolation clocks which are 45 degrees apart after the compensation, wherein the amplitude error accounts for the proportion of the output swing (DeltaVerr/Vpp) to be reduced from 32.2% to 3.6%. The current mode signal is amplified to the full-amplitude square wave signal through the CML2CMOS module 3, and in the process, the linearity loss of 9.3LSB still can be caused due to the AM-PM problem, and at this time, the invention is further optimized on the basis of the structure of FIG. 5, and adopts a global linearity calibration technology based on worst phase optimization:

The linear coding strategy will exhibit worst linearity at the "45 °" phase, however the phase is not absolute, but rather relative, depending on where the intersection of the approximately equivalent diamond with the standard circle is, the worst phase point is the point that is 45 ° out of phase with the intersection. From the coding characteristics of thermometer codes we can see that in each segment of 90 ° the tail current of the control phase change always has a linear increasing and decreasing trend, and each current change is always the same, although the middle phase clock in the segment is far away from the standard clock, the phase clocks on both sides of the middle phase still follow uniform distribution, and the middle phase error is caused by the nonlinear response brought by the linear coding and the AM-PM conversion, the clock phase representing 45 ° is not directly middle to the clock representing 0 ° and 90 °, but is fixed to one side of the clock of 0 ° to deviate, as shown in fig. 10, based on the analysis, if we can calibrate the clock phase of "45 °" and integer multiples thereof to the standard phase, then the clock phase uniformly distributed on both sides naturally returns to the correct phase, the problem is only to obtain the accurate reference standard, and the invention introduces an accurate duplicated phase interpolation circuit as a reference to provide the accurate reference clock phase. The specific implementation logic is as follows:

the current-type digital-to-analog converters 101 in the circuit to be calibrated 2 and the reference circuit 1 respectively comprise two parts of current-type digital-to-analog converters 101;

In the calibration process, normalization statistics are carried out at a control word 0, when the control word is 32, a clock representing 22.5 degrees of phase is generated, a 31-bit thermometer code switch of a first part of current type digital-to-analog converter 101 in the circuit 2 to be calibrated is opened, when the control word is 480, a 337.5 degrees of clock is generated, a 31-bit thermometer code current branch switch of the first part of current type digital-to-analog converter 101 in the circuit 2 to be calibrated is closed, the other three parts of thermometer codes are opened, and the control word 0 represents 0 degrees of phase.

More specifically, in each 90 ° range, 127-bit thermometer code is divided into four parts, namely, every 31 or 32 thermometer code current branch switches control a step regulation in a 22.5 ° phase range, normalization statistics are made at control word 0, control word 0 represents 0 ° phase, then when control word is 32, a clock representing 22.5 ° phase is generated, and IDAC only has 31-bit thermometer code switches of the first part to be opened to provide reference current, and IDAC switches of the other three parts are closed, which means that the input reference current of the three parts IDAC is adjusted, so that linearity of the 22.5 ° clock is not affected, similarly, when input control word is 480, the generated 337.5 ° clock is just that 31-bit thermometer code current branch switch of the first part is closed, and the rest three parts thermometer code is opened, so long as initial current sizes of the two-phase clocks and current ratios of two paths of I/Q are carefully selected, so that we can obtain standard reference clocks. The system architecture is shown in fig. 5, PI represents the replicated phase interpolation modules 102 (PIA and PIB). Three-phase clocks are taken from the PI clock output as calibrated input clocks, such as CLK <0>, CLK <1>, CLK <2> in fig. 5. Wherein CLK <1>, CLK <2> are from the reference standard PI and are adjacent clocks 45 DEG apart, the third phase CLK <0> is taken from the calibrated PI, CLK <0> is the intermediate phase clock between CLK <1> and CLK <2>, and each is 32 steps different from the two reference clocks, i.e., 22.5 deg..

Based on the circuit structure in fig. 5, the corresponding calibration logic flow is shown in fig. 11, and the process is briefly analyzed:

In the power-on starting stage, the control position of the current type digital-to-analog converter 101 is set to be 0, a calibration control word is set to be 0, a circuit is powered on, each module in the system is initialized and a steady state is established, and the current type digital-to-analog converter 101 generates a reference current;

In the 0-degree clock phase calibration stage, enabling the calibration logic module 4 to be 1, starting a calibration process by a circuit, calibrating clock phases representing 0 degrees and integer multiples thereof, switching an input control word of a phase interpolation module 102 to be calibrated in the circuit 2 to be calibrated to 0, setting a first input control word by a reference phase interpolation module 102 in the reference circuit 1, providing a first two-phase clock as a reference, providing the 0-degree clock by the phase interpolation module 102 to be calibrated, adjusting the clock phases by an adjustable current type digital-to-analog converter 101 containing 4-bit calibration bits until a first preset condition is met, and determining that the current error exceeds a calibration range, wherein the first preset condition indicates that a done0 signal representing that the 0-degree clock calibration is completed is set to 1, or the first preset condition indicates that the control bits of the 4-bit current type digital-to-analog converter 101 are all turned on or turned off.

In the phase calibration stage of the 45 DEG clock, after the 0 DEG clock calibration is completed, the input control word of the phase interpolation module 102 to be calibrated is changed into a second input control word, the second input control word represents the 45 DEG clock, the control word of the reference phase interpolation module 102 is changed into a third input control word, a second two-phase clock is provided as a reference, the phase interpolation module 102 to be calibrated provides the 45 DEG clock, and the clock phase is regulated by the adjustable current type digital-analog converter 101 containing 4bit calibration bits until a second preset condition is met, and the current error is determined to exceed the calibration range;

In the calibration ending stage, the calibration logic module 4 controls the position 0, the calibration control word of the current type digital-to-analog converter 101 is updated, the system is switched to the external control word input again, and the calibrated clock phase modulation is carried out.

More specifically, in the calibration logic flow, the first phase is a power-on start phase, in which the calibration logic control bit (en_cal) is set to 0, the IDAC calibration control word is set to 0, the circuit is powered on, each module initializes and establishes a steady state, the IDAC generates a reference current, and the circuit normally generates 8 phases of clocks that are not calibrated. In the second stage, the calibration logic enables (en_cal) to set 1, the circuit starts the calibration process, firstly calibrates the clock phase representing 0 DEG and integer multiples thereof, switches the calibrated PI input control word to 0, sets the input control word to 480 with reference to PI, provides 337.5 DEG, 22.5 DEG two-phase clocks, calibrates PI to provide 0 DEG clocks, takes the two-phase clocks as reference at this time, corrects the 0 DEG clocks, an adjustable IDAC containing 4bit calibration bits opens a one-bit current reference selection switch under the control of a logic circuit, adjusts the clock phase, and then repeats the process, if the logic circuit sets a done0 signal representing 0 DEG clock calibration to 1, then the 0 DEG clock calibration is done, if the 4bit IDAC control bits are all turned on or off, indicating that the current error exceeds the calibration range. When the 0 degree clock calibration is completed, the third stage calibrates the clock phase of the 45 degree clock and the integer multiple thereof, the input control word input of the calibrated PI is changed into 64 to represent the 45 degree clock, the reference PI control word is changed into 32, 22.5 degrees and 62.5 degrees clocks are provided, the two-phase clock is taken as a reference to calibrate the 45 degree clock, an adjustable IDAC containing 4bit calibration bits is used for opening a one-bit current reference selection switch under the control of a logic circuit to adjust the clock phase, then the process is repeated, if the logic circuit sets a done signal of the done45 degree clock representing the 45 degree clock to 1, the 45 degree clock calibration is completed, if the 4bit control bit is all opened or closed, which indicates that the current error exceeds the calibration range. And in the last stage, the done0 signal and the done45 signal are processed by a logic circuit, and the system calibration is judged to be finished, then the calibration logic control bit (en_cal) is set to 0, the IDAC calibration control word is updated, the system is switched to the external control word input again, and the calibrated clock phase modulation is carried out.

The invention verifies the effectiveness by simulating and building an actual circuit, wherein fig. 13 (a) is a schematic diagram of eight clock signals before the calibration of the invention, fig. 13 (b) is a schematic diagram of eight clock signals after the calibration of the invention, fig. 14 is Differential Nonlinear (DNL) normalization statistics of eight clocks before and after the calibration, and as can be seen from fig. 13 (a), fig. 13 (b) and fig. 14, eight-phase clocks reach 0LSB,0.29LSB,0.68LSB,0.65LSB, -0.09LSB,0.17LSB,0.77LSB and 0.69LSB. With the maximum value falling from-9.37 LSB to 0.77LSB.

Calibration ranges as shown in fig. 15, a calibration of 0.4 ° step size can be provided in a range of 6.336 °.

Fig. 16 is statistics of Integrated Nonlinear (INL) simulation results of 512 phases, and compared with the conventional PI without calibration, the scheme provided by the invention can limit the overall INL to below 2.1LSB, and in general, the invention can realize very high-precision phase linearity calibration, has better process portability in an all-digital manner, has certain resistance to PVT fluctuation, and can realize very excellent phase interpolator linearity level at a lower cost. Of these, INL (Integral Nonlinearity), integral nonlinearity, is an important static performance parameter of analog-to-digital converters (ADCs). INL is the error value at which the integral nonlinearity represents the maximum error between the corresponding analog and real values of the ADC at all points in the value, i.e., the distance that the output value deviates from linearity by the maximum. The unit of INL is LSB (LEAST SIGNIFICANT Bit), i.e., the least significant Bit. The LSB represents the last bit in the digital stream and also represents the smallest unit that constitutes the full range input range.

Through the scheme of the embodiment, the invention provides a global linearity calibration technology and an implementation scheme based on worst phase optimization on the basis of a traditional current mode phase interpolation circuit, so as to solve the problem of linearity loss caused by a tail current source linear coding strategy in the current mode phase interpolation circuit and the problem of amplitude error (AM) phase-to-phase error (PM) in the current mode clock signal amplifying process, and provide an effective solution for designing the problem of serious loss of linearity of a system due to AM-PM error generated by an output signal caused by a linear weight control strategy in the traditional current mode phase interpolation circuit. By using the scheme of the invention, very good linearity calibration of the phase interpolation circuit can be realized. The innovative phase calibration concept and calibration logic design are the innovative points to be protected by the present invention.

Although the invention is described herein in connection with various embodiments, other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the "a" or "an" does not exclude a plurality. A single processor or other unit may fulfill the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

Although the invention has been described in connection with specific features and embodiments thereof, it will be apparent that various modifications and combinations can be made without departing from the spirit and scope of the invention. Accordingly, the specification and drawings are merely exemplary illustrations of the present invention as defined in the appended claims and are considered to cover any and all modifications, variations, combinations, or equivalents that fall within the scope of the invention. It will be apparent to those skilled in the art that various modifications and variations can be made to the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.

Claims

1. A phase calibration system for a phase interpolation circuit, characterized in that the system at least comprises:

A reference circuit and a circuit to be calibrated; the reference circuit and the circuit to be calibrated have the same structure;

The reference circuit or the circuit to be calibrated includes a current-type digital-to-analog converter, a phase interpolation module and a phase combination module;

The phase interpolation module includes a PIA module and a PIB module; the current-type digital-to-analog converter is connected to the phase interpolation module, and the current-type digital-to-analog converter provides current for the phase interpolation module;

The phase combination module is connected to the phase interpolation module to calibrate the clock phase of 45° and its integer multiples to the standard phase.

2. A phase calibration system for a phase interpolation circuit according to claim 1, characterized in that the system further comprises:

CML2CMOS module;

The phase combination module is connected to the CML2CMOS module, and the CML2CMOS module is used to amplify the current mode signal to a full-scale square wave signal.

3. According to claim 1, a phase calibration system for a phase interpolation circuit is characterized in that the PIA module and the PIB module respectively receive a 0° reference clock, a 90° reference clock, a 180° reference clock and a 270° reference clock as reference input clocks, and realize phase synthesis by controlling the on and off of the tail current switches of the four differential pairs to generate a differential interpolation clock output.

4. According to claim 3, a phase calibration system for a phase interpolation circuit is characterized in that the phase combination module is used to adopt a compensation method of a dual-phase interpolator architecture on the PIA module and the PIB module respectively, and a phase difference of 45° is created between PIA and PIB through the current-type digital-to-analog converter.

5. The phase calibration system for a phase interpolation circuit according to claim 1, characterized in that the system further comprises:

A calibration logic module; the calibration logic module is connected to the current-type digital-to-analog converter;

The current-type digital-to-analog converter serves as the tail current input of the phase interpolation module, and adopts a 9-bit control word segmented method to provide current for the phase interpolation module; the 9-bit control word segmented method includes two high-order binary codes and seven low-order full-thermometer codes, the two high-order binary codes are used to control the on-off of the tail current sources of the four differential pairs, and the seven low-order full-thermometer codes are used to control the ratio of the interpolation current, completing the ratio control of 127 phases within a 90-degree range;

Each input of the lower seven-bit thermometer code is an independent reference current. The reference current includes two 4-bit adjustable current calibration branches. The output result of the current-type digital-to-analog converter is used to control the current on and off of the adjustable branch.

6. A phase calibration system for a phase interpolation circuit according to claim 1, characterized in that the reference circuit identifies and calibrates the worst linearity exhibited at a clock phase of 45° and its integer multiples, provides a reference clock phase by using a replicated phase interpolation module as a reference, and divides the 127-bit thermometer code into four parts within each 90° range, obtains a two-phase standard reference clock by adjusting the input reference current of a current-type digital-to-analog converter of a specific part and the current ratio of the I/Q paths, and is used to calibrate the intermediate phase clock of the phase interpolation module in the circuit to be calibrated;

By selecting the initial current size and the current ratio of the I/Q paths for generating a preset two-phase clock, a two-phase standard reference clock is obtained; the preset two-phase clock is an adjacent clock separated by 45°.

7. A phase calibration system for a phase interpolation circuit according to claim 1, characterized in that the current-type digital-to-analog converter in the circuit to be calibrated and in the reference circuit each comprises two parts of current-type digital-to-analog converters;

During the calibration process, normalized statistics are performed at control word 0; when the control word is 32, a clock representing a 22.5° phase is generated, and the 31-bit thermometer code switch of the first part of the current-type digital-to-analog converter in the circuit to be calibrated is turned on; when the control word is 480, a 337.5° clock is generated, the 31-bit thermometer code current branch switch of the first part of the current-type digital-to-analog converter in the circuit to be calibrated is turned off, and the remaining three parts of the thermometer code are turned on; the control word 0 represents a 0° phase.

8. A phase calibration system for a phase interpolation circuit according to claim 1, characterized in that the gates of the first transistor and the fourth transistor in the phase interpolation module input 0° clocks, and the gates of the second transistor and the third transistor input 180° clocks, and phase synthesis is achieved within a 360° range by selecting the reference clocks of the I/Q channels;

In the phase combination module, the gates of the first transistor and the third transistor are respectively connected to the negative pole of the input clock, and the gates of the second transistor and the fourth transistor are connected to the positive pole of the clock. The voltage signal with phase information is converted into a source-drain current signal with phase information in the differential pair, and vector superposition is performed on the load resistor.

9. A phase calibration system for a phase interpolation circuit according to claim 5, characterized in that, in the power-on startup phase, the control bit of the current-type digital-to-analog converter is set to 0, the calibration control word is set to 0, the circuit is powered on, each module in the system is initialized and establishes a steady state, and the current-type digital-to-analog converter generates a reference current;

In the 0° clock phase calibration stage, the calibration logic module is enabled and set to 1, the circuit starts the calibration process, and the clock phase representing 0° and its integer multiples is calibrated. The input control word of the phase interpolation module to be calibrated in the circuit to be calibrated is switched to 0, and the reference phase interpolation module in the reference circuit sets the first input control word to provide a first two-phase clock as a reference. The phase interpolation module to be calibrated provides a 0° clock, and the clock phase is adjusted through an adjustable current-type digital-to-analog converter containing a 4-bit calibration bit until the first preset condition is met, and it is determined that the current error exceeds the calibration range; the first preset condition indicates that the done0 signal representing the completion of the 0° clock calibration is set to 1, or the first preset condition indicates that all the 4-bit current-type digital-to-analog converter control bits are turned on or off.

10. A phase calibration system for a phase interpolation circuit according to claim 9, characterized in that, in the 45° clock phase calibration stage, when the 0° clock calibration is completed, the input control word input of the phase interpolation module to be calibrated is changed to a second input control word, the second input control word represents a 45° clock, the reference phase interpolation module control word is changed to a third input control word, a second two-phase clock is provided as a reference, the phase interpolation module to be calibrated provides a 45° clock, and the clock phase is adjusted by an adjustable current-type digital-to-analog converter containing a 4-bit calibration bit until a second preset condition is met, and it is determined that the current error exceeds the calibration range; the second preset condition indicates that the done45 signal representing the completion of the 45° clock calibration is set to 1, or the second preset condition indicates that all 4-bit control bits are turned on or off;

In the calibration end stage, the calibration logic module control position is set to 0, the current-mode digital-to-analog converter calibration control word is updated, and the system is switched back to the external control word input to perform the calibrated clock phase adjustment.