CN120201712A - Memory and manufacturing method thereof, and electronic device - Google Patents

Abstract

The present disclosure relates to a memory and a manufacturing method thereof, and an electronic device. The memory comprises a memory cell array periodically stacked on a substrate in a direction perpendicular to the substrate; each of the memory cells comprises a transistor and a capacitor sequentially distributed in the first direction; the capacitor comprises an inner electrode extending in the first direction, a dielectric layer sequentially covering the inner electrode, and an outer electrode; the transistor comprises a first electrode connected to the inner electrode and a second electrode connected to the bit line; a dielectric layer is included between any two layers of the memory cell array; wherein the inner electrode is formed by replacing a sacrificial layer between two adjacent dielectric layers; the first electrode, the second electrode, and the bit line are formed by replacing a sacrificial layer between two adjacent dielectric layers after the inner electrode is formed.

Description

Memory, manufacturing method thereof and electronic equipment

Technical Field

The present disclosure relates to the field of integrated circuit design and manufacturing technologies, and in particular, to a memory, a manufacturing method thereof, and an electronic device.

Background

With the continuous development of integrated circuit manufacturing processes, the market has placed higher demands on the memory capacity and memory performance of DRAM memories. A stereoscopic stacked DRAM (abbreviated as 3D DRAM) is also attracting attention, and this technology provides a possibility to further improve the memory performance of the DRAM memory and to improve the memory density.

Disclosure of Invention

Based on the above, the disclosure provides a memory, a manufacturing method thereof and electronic equipment, which can effectively improve the mechanical reliability of the memory in the manufacturing process.

According to various embodiments of the present disclosure, there is provided in one aspect a memory comprising:

The memory cell array is positioned on a substrate and is stacked along the direction vertical to the substrate, and each layer of memory cell array comprises memory cells distributed along rows and columns in a first direction and a second direction;

a plurality of word lines extending in a direction perpendicular to the substrate, penetrating through the memory cell arrays of each layer, each of the word lines being connected to the plurality of memory cells;

A plurality of bit lines extending in the second direction, each bit line being connected to at least one column of memory cells in one memory cell array;

each memory unit comprises a transistor and a capacitor which are distributed in sequence in the first direction, wherein the capacitor comprises an inner electrode extending in the first direction, a dielectric layer and an outer electrode which cover the inner electrode in sequence, and the transistor comprises a first electrode electrically connected with the inner electrode and a second electrode connected with the bit line;

A dielectric layer is arranged between any two layers of memory cell arrays;

the first electrode, the second electrode and the bit line are formed by replacing the sacrificial layer between the two adjacent dielectric layers after the inner electrode is formed.

In some embodiments, the inner electrode and the first electrode are formed by patterning different conductive layers;

the first electrode, the second electrode and the bit line are formed by patterning the same conductive layer.

In some embodiments, the memory cell further includes a channel layer located between the first electrode and the second electrode around a sidewall of the word line, the channel layer being insulated from the word line by a gate dielectric layer.

In some embodiments, one bit line is connected to each second electrode of two adjacent columns of memory cells, wherein the two adjacent columns of memory cells are distributed in mirror symmetry with respect to the bit line;

the bit lines, the second electrodes and the first electrodes of the two rows of memory cells are formed by replacing a sacrificial layer between two adjacent dielectric layers at one time, and the first electrodes, the second electrodes and the bit lines are formed by patterning the same conductive layer.

In some embodiments, the dielectric layer and the external electrode are formed after forming the internal electrode and before forming the bit line, the external electrode acting as a support frame.

In some embodiments, the dielectric layer and the external electrode cover a column of memory cells and each internal electrode of each memory cell of the column of memory cells stacked in a vertical direction, and the dielectric layer and the external electrode are formed by replacing a dielectric layer of the capacitor region.

In some embodiments, the dielectric layer is silicon oxide and the sacrificial layer is silicon nitride or silicon oxynitride.

An embodiment of the present application provides an electronic device, including a memory as described in any one of the above embodiments.

The embodiment of the application provides a manufacturing method of a memory, which comprises the following steps:

Providing a substrate, and forming a plurality of dielectric layers and a plurality of sacrificial layers on the substrate, wherein the dielectric layers and the sacrificial layers are alternately distributed;

The dielectric layer and the sacrificial layer are subjected to a patterning process to form a plurality of grooves perpendicular to the substrate, a plurality of first sacrificial strips which extend along a first direction and are distributed at intervals along a second direction and are in one-to-one correspondence with the memory cells, and second sacrificial strips which are intersected with the plurality of first sacrificial strips are arranged among the grooves, the dielectric layer stacked with the plurality of first sacrificial strips and the second sacrificial strips of each layer is also arranged among the grooves, the first direction is a row direction, the second direction is a column direction, and the row direction and the column direction are parallel to the substrate;

The first sacrificial strip sequentially comprises a capacitor region and a transistor region in a first direction, and the transistor region is close to the second sacrificial strip;

removing the capacitance area of the first sacrificial strip through an etching process, exposing the dielectric layers adjacent in the vertical direction, and reserving the transistor area of the first sacrificial strip;

filling a conductive layer between the exposed dielectric layers to replace the capacitance area of the first sacrificial strip, so as to form an inner electrode;

And removing the transistor area of the first sacrificial strip and the second sacrificial strip through an etching process after the inner electrode is formed, exposing the adjacent dielectric layers in the vertical direction, filling a conductive layer between the adjacent dielectric layers, and replacing the transistor area and the second sacrificial strip to form a first electrode, a second electrode and a bit line which are in contact with the inner electrode.

In some embodiments, before forming the internal electrode, the trench is filled with the same material as the dielectric layer, a word line hole penetrating through each dielectric layer and each sacrificial layer is formed in the transistor region of the first sacrificial strip, and a dummy word line is filled in the word line hole.

In some embodiments, the first and second sacrificial strips of each layer are of unitary construction, the first and second electrodes are spaced apart from one another, and the second electrode and the bit line are of unitary construction.

In some embodiments, removing the first sacrificial strip of each capacitor region by an etching process to expose the dielectric layer adjacent in the vertical direction, and reserving the first sacrificial strip of the transistor region, including:

Removing the capacitor region of the first sacrificial strip between adjacent dielectric layers in the vertical substrate direction, and sequentially filling a first conductive layer between adjacent dielectric layers to serve as an inner electrode.

In some embodiments, the method further comprises, after the manufacturing of the internal electrode, before the manufacturing of the first electrode, the second electrode, and the bit line:

and sequentially depositing a dielectric layer and a conductive layer on the exposed inner electrode, wherein the conductive layer is an outer electrode of the capacitor, and the outer electrode is used as a supporting frame.

In some embodiments, removing the transistor region of the first sacrificial strip and the second sacrificial strip to expose the adjacent dielectric layer includes:

And removing the sacrificial layer between the adjacent dielectric layers in the vertical direction by a wet process to expose the dielectric layers of the first electrode, the second electrode and the bit line region.

According to the memory and the manufacturing method provided by the embodiment of the application, after the sacrificial layer and the dielectric layer are stacked, the conductive layer is used for replacing the sacrificial layer to realize the transistor and the capacitor of the memory unit, wherein the sacrificial layer of the capacitor area is replaced by the conductive layer, the conductive layer and the dielectric layer of the capacitor area are used for supporting, and then the sacrificial layer of the transistor area is replaced by the conductive layer, so that the mechanical stability of the capacitor and the transistor formed by the sacrificial layer and the dielectric layer stacking process can be improved, and the collapse risk is avoided.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and other drawings may be obtained according to these drawings without inventive effort for a person of ordinary skill in the art.

FIGS. 1-11 are schematic views of a memory manufactured by a method according to an embodiment of the present disclosure;

The ox direction may be a first direction, the oy direction may be a second direction, and the oz direction may be a vertical direction.

Reference numerals illustrate:

100. Substrate, 11, dielectric layer, 12, sacrificial layer, 121, first sacrificial strip, 122, second sacrificial strip, 123, third sacrificial strip, 20, dummy word line, 40, capacitor, 90, isolation layer, 41, inner electrode, 42, intermediate dielectric layer, 43, outer electrode, 50, conductive layer, 13, patterned mask layer, 14, isolation trench, 15, first groove, 16, intermediate trench, 17, interlayer groove, 18, bit line groove, 501, bit line, 19, side groove, 60, common bit line.

Detailed Description

In order that the disclosure may be understood, a more complete description of the disclosure will be rendered by reference to the appended drawings. Preferred embodiments of the present disclosure are shown in the drawings. This disclosure may, however, be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used in the description of the disclosure herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure.

It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and/or sections, these elements, components, regions, layers, doping types and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or section from another element, component, region, layer, doping type or section. Thus, a first element, component, region, layer, doping type or section discussed below could be termed a second element, component, region, layer or section, for example, a first doping type could be termed a second doping type, and, similarly, a second doping type could be termed a first doping type, a doping type different from the second doping type, such as, for example, the first doping type could be P-type and the second doping type could be N-type, or the first doping type could be N-type and the second doping type could be P-type.

Spatially relative terms, such as "under", "below", "beneath", "under", "above", "over" and the like, may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "below" and "under" may include both an upper and a lower orientation. Furthermore, the device may also include an additional orientation (e.g., rotated 90 degrees or other orientations) and the spatial descriptors used herein interpreted accordingly.

As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Also, as used herein, the term "and/or" includes any and all combinations of the associated listed items.

Note that the mutual insulation between the two described in the embodiments of the present disclosure includes, but is not limited to, the presence of one or more of an insulating material, an insulating breath, a gap, etc. between the two.

It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concepts of the disclosure by way of illustration, and only the components related to the disclosure are shown in the illustration, rather than being drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of each component in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.

Note that the mutual insulation between the two described in the embodiments of the present disclosure includes, but is not limited to, at least one of an insulating material layer, an insulating air or a gap between the two, and the meaning of a and B described in the embodiments of the present disclosure as forming "conformal coverage" or "conformal stacking" on a substrate is intended to include that the orthographic projection of a on the top surface of the substrate completely overlaps the orthographic projection of B on the top surface of the substrate.

The fabrication process of the 3D DRAM device, in some embodiments, employs a stack of dielectric layers and sacrificial layers (typically insulating layers), and then replaces the sacrificial layers with conductive layers in the capacitor and transistor regions to form the capacitor and transistor. In the application scene, the problem of mechanical stability of the whole 3D stack easily exists when the sacrificial layer is replaced, for example, the film layer of the 3D-DRAM is easy to collapse after the sacrificial layer is hollowed. Some embodiments will make a support frame independent of the capacitor and transistor as a support.

The application provides a memory capable of improving mechanical stability, a manufacturing method thereof and electronic equipment.

In some embodiments, there is provided a method of manufacturing a memory, comprising:

Providing a substrate, and forming a plurality of dielectric layers and a plurality of sacrificial layers on the substrate, wherein the dielectric layers and the sacrificial layers are alternately distributed;

The dielectric layer and the sacrificial layer are subjected to a patterning process to form a plurality of grooves perpendicular to the substrate, a plurality of first sacrificial strips extending along a first direction and distributed at intervals along a second direction are included among the grooves, and a second sacrificial strip intersected with the plurality of first sacrificial strips, wherein the plurality of first sacrificial strips and the second sacrificial strips of each layer are of an integrated structure, a dielectric layer stacked with the plurality of first sacrificial strips and the second sacrificial strips of each layer is further included among the grooves, the first direction is a row direction, the second direction is a column direction, and the row direction and the column direction are parallel to the substrate;

The first sacrificial strip sequentially comprises a capacitor region and a transistor region in a first direction, and the transistor region is close to the second sacrificial strip;

Removing the first sacrificial strips of each capacitor region through an etching process, exposing the dielectric layers adjacent in the vertical direction, and reserving the first sacrificial strips of the transistor region;

Filling a conductive layer between the exposed adjacent dielectric layers to replace the capacitance area of the first sacrificial strip, so as to form an inner electrode;

And removing the transistor area of the first sacrificial strip and the second sacrificial strip through an etching process after the inner electrode is formed, exposing the adjacent dielectric layers in the vertical direction, filling a conductive layer between the adjacent dielectric layers, replacing the transistor area and the second sacrificial strip, and forming a first electrode in contact with the inner electrode, and a second electrode and a bit line of an integrated structure, wherein the second electrode and the first electrode are mutually spaced.

In some embodiments, before forming the internal electrode, the trench is filled with the same material as the dielectric layer, a word line hole penetrating through each dielectric layer and each sacrificial layer is formed in the transistor region of the first sacrificial strip, and a dummy word line is filled in the word line hole.

In some embodiments, removing the first sacrificial strip of each capacitor region by an etching process to expose the dielectric layer adjacent in the vertical direction, and reserving the first sacrificial strip of the transistor region includes:

Removing the capacitor region of the first sacrificial strip between adjacent dielectric layers in the vertical substrate direction, and sequentially filling a first conductive layer between adjacent dielectric layers to serve as an inner electrode.

In some embodiments, the method further comprises, after the fabricating the internal electrode, before the fabricating the first electrode, the second electrode, and the bit line:

and sequentially depositing a dielectric layer and a second conductive layer on the exposed inner electrode, wherein the second conductive layer is an outer electrode of the capacitor, and the dielectric layer and the outer electrode are used as a supporting frame.

In some embodiments, removing the transistor region of the first sacrificial strip and the second sacrificial strip exposes adjacent dielectric layers includes:

And removing the sacrificial layer between the adjacent dielectric layers in the vertical direction by a wet process to expose the dielectric layers of the first electrode, the second electrode and the bit line region.

According to the memory and the manufacturing method provided by the embodiment of the application, after the sacrificial layer and the dielectric layer are stacked, the conductive layer is used for replacing the sacrificial layer to realize the transistor and the capacitor of the memory unit, wherein the sacrificial layer of the capacitor area is replaced by the conductive layer, the conductive layer and the dielectric layer of the capacitor area are used for supporting, and then the sacrificial layer of the transistor area is replaced by the conductive layer, so that the mechanical stability of the capacitor and the transistor formed by the sacrificial layer and the dielectric layer stacking process can be improved, and the collapse risk is avoided.

The above-described memory manufacturing method and device features of the memory will be described in detail below with reference to the accompanying drawings.

A manufacturing method of a memory includes:

Step S20, providing a substrate (such as a silicon substrate), and sequentially forming dielectric layers and sacrificial layers which are alternately stacked along the direction perpendicular to the substrate on the substrate to form a stacked film layer. Every two adjacent dielectric layers and sacrificial layers are in a cycle. For example, alternating cyclical distributions of silicon nitride and silicon oxide film layers are formed on a substrate. The silicon nitride can be several layers or tens of layers, and the silicon oxide is positioned between any two adjacent silicon nitride film layers. Silicon oxide is a dielectric layer and silicon nitride is a sacrificial layer. Silicon oxide and silicon nitride are only elements included in the material of the film layer, and the ratio of elements in the film layer substance is not limited.

And etching the stacked film layers through a mask to form a trench (trench) perpendicular to the substrate direction. The dielectric layer and the sacrificial layer outside the groove are patterned film layers, wherein the sacrificial layer comprises a plurality of first sacrificial strips extending along a first direction (row direction) and distributed at intervals along a second direction (column direction), and a second sacrificial strip extending along the column direction and intersecting the plurality of first sacrificial strips;

either one second sacrificial strip connects two columns of first sacrificial strips simultaneously or one second sacrificial strip connects only one column of first sacrificial strips.

In addition, the second sacrificial strip and each connected first sacrificial strip are of a unitary structure.

In step S40, an isolation layer is filled in the trench, where the isolation layer may be a film layer made of the same material as the dielectric layer, and may also be referred to as a dielectric layer, and may also be understood as forming an isolation layer between the first sacrificial strips adjacent along the second direction. And forming a word line hole penetrating through the dielectric layer and the first sacrificial strip in the transistor area of the first sacrificial strip, and filling polysilicon in the word line hole to serve as a dummy word line, wherein the dummy word line can be also understood as a temporary word line or a sacrificial word line, and the temporary word line or the sacrificial word line is replaced by a real word line later. The second sacrificial strips are positioned between adjacent dummy word lines along a first direction, and the first direction intersects with a second direction and is parallel to the substrate.

In step S60, the first sacrificial strip extends in the row direction and comprises a capacitor area and a transistor area adjacent to each other in the row direction, the transistor area is close to the bit line area, and the capacitor is connected with the bit line through the transistor.

The capacitor region of the first sacrificial strip is replaced with an inner electrode, and then the dielectric layer contacted with the inner electrode is removed to expose the side surfaces of the inner electrode extending in the row direction, and a dielectric layer and an outer electrode are sequentially formed on the side surfaces.

And when the dielectric layers contacted with the inner electrodes are removed, removing the dielectric layers contacted with the inner electrodes of one row of memory cells and each stacked memory cell at the same time to expose each inner electrode of a plurality of stacked memory cells, forming a dielectric layer forming a capacitance dielectric layer on the side surface of each inner electrode by one process, and forming a conductive layer to replace the removed dielectric layer by one process, wherein the conductive layer is used as an external electrode of a capacitor. The conductive layers are mutually communicated film layers and cover the side surfaces of the inner electrodes. Of course, the dielectric layer and the conductive layer as the external electrode may cover both the side surface and the end surface of the internal electrode.

The outer electrode serves as a supporting frame at the same time, and plays a role of the supporting frame when the sacrificial layer is hollowed out continuously.

Each memory cell array, every two columns of memory cells are distributed in a mirror symmetry mode to serve as a repeating unit. The capacitances of adjacent repeating units are adjacent.

Step S80, removing the isolation layer between the adjacent external electrodes along the first direction, which can be understood as removing the isolation layer between the adjacent repeating units;

and step S100, filling a conductive layer in the isolation layer removed in the step S80, wherein the conductive layer is used as a common external electrode of adjacent capacitors in the two repeated units, and the common external electrode is connected with the external electrode of the capacitor area.

As an example, referring to fig. 1, the substrate 100 provided in step S20 may be formed of a semiconductor material, an insulating material, a conductor material, or any combination thereof. The substrate 100 may have a single-layer structure or a multi-layer structure. For example, the substrate 100 may be a substrate such as a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III/V semiconductor substrate or II/VI semiconductor substrate. Or also for example, substrate 100 may be a layered substrate comprising a material such as Si/SiGe, si/SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator. The type of substrate 100 should not limit the scope of the present disclosure.

Illustratively, the ox direction in fig. 1 is a first direction, the oy direction is a second direction, and the oz direction is a vertical direction (i.e., a direction perpendicular to the substrate). In an embodiment, the first direction may be a row direction and the second direction may be a column direction.

As an example, referring to fig. 1, in step S20, a deposition process may be sequentially used to form dielectric layers and sacrificial layers stacked alternately along the direction perpendicular to the substrate 100 on the substrate 100, and then an etching process is used to obtain trenches (trench) of the perpendicular substrate, so as to obtain patterned dielectric layers 11 and sacrificial layers 12 stacked alternately along the direction perpendicular to the substrate 100.

In which, as shown in fig. 1, the patterned dielectric layer 11 and the sacrificial layer 12 have the same shape.

The sacrificial layer 12 includes a plurality of first sacrificial strips 121 extending in a first direction and spaced apart in a second direction, each sacrificial strip corresponding to one memory cell region.

The sacrificial layer 12 further includes a second sacrificial strip 122 where the plurality of first sacrificial strips 121 intersect. The second sacrificial strips 122 connect two columns of the first sacrificial strips 121 and are disposed integrally with the first sacrificial strips 121.

The sacrificial layer 12 may further include a third sacrificial strip 123 located at the same side of the plurality of first sacrificial strips 121 in the second direction so as to facilitate a subsequent replacement of the third sacrificial strip 123 with a common bit line.

The first sacrificial strip, the second sacrificial strip and the third sacrificial strip are integrally disposed.

The material of the dielectric layer 11 may include, but is not limited to, silicon oxide, and the material of the sacrificial layer 12 may include, but is not limited to, a film layer containing silicon and nitrogen such as silicon oxynitride or silicon nitride. Because the insulating laminated structure comprising nitride and oxide is more convenient in deposition, the etching selection ratio is relatively low in the etching process, and the etching process difficulty is low. Therefore, the manufacturing efficiency of the memory can be improved, and the cost can be reduced. The etching process may include, but is not limited to, one or more of Reactive Ion Etching (RIE), inductively coupled plasma etching (ICP), or high-concentration plasma etching (HDP). The deposition process may include, but is not limited to, one or more of a chemical vapor deposition process (Chemical Vapor Deposition, CVD), an atomic layer deposition process (Atomic Layer Deposition, ALD), a high-density plasma deposition (HIGH DENSITY PLASMA, HDP) process, a plasma enhanced deposition process, and Spin-on Dielectric (SOD) processes.

As an example, referring to fig. 2, in step S40, a deposition process may be used to form an isolation layer 90 in the trench of the three-dimensional structure shown in fig. 1, the isolation layer 90 may fill the trench between the patterned dielectric layer 11 and the sacrificial layer 12, and after forming the isolation layer 90, a planarization process, such as a chemical mechanical polishing process, may be used to expose the dielectric layer 11 on top.

The isolation layer can be a film layer made of the same material as the dielectric layer, for example, a film layer made of the same material as the dielectric layer silicon oxide between the sacrificial layers can be used for forming a silicon oxide film layer.

As an example, please continue to refer to fig. 2, after forming the isolation layer 90 with the top surface flush with the dielectric layer 11, in step S40, a plurality of first holes (which may also be referred to as word line holes) penetrating the dielectric layer 11 and the sacrificial layer 12 along the direction perpendicular to the substrate 100 are formed by using a dry etching process, where the plurality of first holes are located in the transistor region of the first sacrificial strip 121, one first hole corresponds to one word line, and each memory cell stack layer corresponds to one memory cell region. The second sacrificial strip 122 is located between two first holes on the first sacrificial strip 121 as a bit line region to be formed. The first hole may expose a portion of the top surface of the substrate 100, and then an insulating or conductive material (e.g., polysilicon) may be filled in the first hole by a deposition process to form the dummy word line 20 in the first hole, and the second sacrificial strip 122 may be located between adjacent dummy word lines 20 along the first direction, so that two bit lines or one common bit line may be subsequently formed between two memory cells adjacent along the first direction.

After the dummy word line 20 is formed in step S40, the top surface of the dummy word line 20 may be processed using a planarization process such that the top surface of the dummy word line 20 is flush with the top surface of the isolation layer 90.

As an example, referring to fig. 3 to 8, in step S60, replacing an end of the first sacrificial strip 121 facing away from the dummy word line 20 in the first direction with an inner electrode of a capacitor includes:

Step S61, forming a mask layer 13 for defining a capacitance region on the top of the stacked film layers;

In step S62, the portion of the isolation layer 90 facing away from the dummy word line 20 in the first direction is etched and removed using the mask layer 13 as a mask to obtain the isolation trench 14, which can be understood as the mask layer 13 covering the bit line region and the transistor region and the isolation layer region between adjacent transistor regions in the column direction. The region between two adjacent capacitor areas in the column direction in the isolation layer 90 is exposed, and of course, the isolation layer in the vertical direction is removed in this region, and the sidewalls of the patterned dielectric layer and the sacrificial layer are exposed. It is also understood that the trench (isolation trench 14) is dug again in the trench region filled with the isolation layer, the trench (isolation trench 14) exposing only the portion between the capacitance regions, leaving the portion between the transistor regions. The isolation layers between the capacitor regions are removed and the side walls of the dielectric layer and the sacrificial layer after patterning are exposed.

Step S63 of removing portions of the plurality of first sacrificial strips 121 facing away from the dummy word line 20 in the first direction via the isolation trenches 14, resulting in first recesses 15;

It is understood that after the dielectric layer and the sidewall of the sacrificial layer are exposed, the sacrificial layer is etched by using a selective etching solution, so that the inner surface (the surface contacted with the sacrificial layer) of the dielectric layer in the capacitor region is exposed, and at this time, the sacrificial layer in the transistor region remains, which can be achieved by controlling the etching depth of the sacrificial layer by etching time. At this time, the upper and lower surfaces and the side surfaces of any one dielectric layer of the capacitor region are exposed, and the opening between two adjacent dielectric layers may be referred to as a first recess 15.

And S64, forming a conductive layer in the opening between two adjacent dielectric layers to serve as an inner electrode of the capacitor. That is, the inner electrode 41 is formed in the first recess 15 as shown in fig. 6. At this time, the internal electrodes 41 are independent from each other and are isolated by a dielectric layer.

As an example, referring to fig. 3, in step S61, a patterned photoresist layer (not shown) and a hard mask layer located between the patterned photoresist layer and the isolation layer 90 may be formed on the top surface of the three-dimensional structure shown in fig. 2, the hard mask layer may be a single-layer structure or a multi-layer stacked structure, and the hard mask layer may be made of silicon oxide.

As an example, referring to fig. 4, in step S62, a dry etching process may be used to etch and remove a portion of the isolation layer 90 away from the dummy word line 20 in the first direction with the patterned mask layer 13 as a mask, so as to obtain the isolation trench 14. It will be appreciated that when removing the isolation layer silicon oxide filled in the trench formed for the first time, dry etching may be used in combination with the mask layer 13 to remove only the isolation layer between the capacitor regions, in order to expose only the capacitor regions and not the transistor regions.

As an example, referring to fig. 5, in step S63, a wet etching process may be used to remove portions of the plurality of first sacrificial strips 121 facing away from the dummy word line 20 in the first direction via the isolation trenches 14, resulting in the first grooves 15, so as to form the inner electrodes 41 in the first grooves 15. It is understood that the exposed silicon nitride or silicon oxide N layer is removed by wet etching after the silicon oxide of the isolation layer is removed by dry method.

As an example, please continue to refer to fig. 6-8, forming a capacitor in the first recess 15 in step S64 includes:

step S641, forming an inner electrode 41 in the first groove 15;

step S642, removing the dielectric layer 11 between the inner electrodes to expose the upper and lower surfaces and the side surfaces of the inner electrode 41;

Step S643, forming an intermediate dielectric layer 42 surrounding the upper and lower surfaces and the side surfaces of the inner electrode 41;

In step S644, the external electrode 43 is formed in the region where the filling dielectric layer 11 is located, the external electrode 43 is located between the intermediate dielectric layers 42 adjacent in the second direction and the direction perpendicular to the substrate 100, and the internal electrodes 41 adjacent in the second direction and the direction perpendicular to the substrate 100 are insulated from each other via the intermediate dielectric layers 42. The external electrode 43 serves as a common external electrode for each memory cell.

As an example, referring to fig. 6, in step S641, the deposition process may be used to form the inner electrodes 41 of the capacitor in the first recess 15, where the inner electrodes 41 adjacent to each other in the oz direction are insulated from each other by the dielectric layer 11, and the inner electrodes 41 adjacent to each other in the oy direction are insulated from each other by the isolation trench 14.

As an example, referring to fig. 7, in step S642, the dielectric layer 11 between the inner electrodes 41 may be removed by a wet etching process, exposing the upper, lower and side surfaces of the inner electrodes 41. The material of the inner electrode 41 may be selected from doped silicon, polysilicon, copper, tungsten, aluminum, copper alloy, titanium nitride, a nitride button, and combinations thereof.

As an example, referring to fig. 8, in step S643, an atomic layer deposition process and/or a plasma vapor deposition process may be used to form the intermediate dielectric layer 42, and the material of the intermediate dielectric layer 42 may be a high-k dielectric material (e.g., a dielectric material with a dielectric constant greater than or equal to 3.9).

As an example, referring to fig. 8, in step S644, the external electrode 43 may be formed by using an atomic layer deposition process and/or a plasma vapor deposition process, the external electrode 43 is located between the intermediate dielectric layers 42 adjacent to each other in the second direction and the direction perpendicular to the substrate 100, and the internal electrode 41 adjacent to each other in the second direction and the direction perpendicular to the substrate 100 is insulated by the intermediate dielectric layers 42. The capacitors 40 adjacent to each other in the second direction and the direction perpendicular to the substrate 100 share the external electrode 43, so that the manufacturing process and cost of the capacitors 40 can be reduced. The materials of the inner electrode 41 and the outer electrode 43 may be the same or different, for example, the materials of the inner electrode 41 and the outer electrode 43 may be selected from doped silicon, polysilicon, copper, tungsten, aluminum, copper alloy, titanium nitride, nitride buttons, and combinations thereof. The inner electrode 41, the intermediate dielectric layer 42 and the outer electrode 43 are used to jointly form the capacitor 40.

As an example, referring to fig. 9, removing the isolation layer 90 between adjacent capacitors along the first direction in step S80 includes:

Step S81 of etching the isolation layer 90 between the capacitors adjacent in the first direction in the direction perpendicular to the substrate 100 by a dry etching process to obtain the intermediate trench 16, so as to remove the sacrificial layer 12 between the capacitors adjacent in the first direction via the intermediate trench 16.

As an example, referring to fig. 10 to 11, replacing the sacrificial layer 12 between adjacent capacitors along the first direction with the conductive layer 50 in step S100 includes:

step S101, removing the sacrificial layer 12 between adjacent capacitors along the first direction by adopting a wet etching process to obtain an interlayer groove 17;

Step S102, a conductive layer 50 is formed in the interlayer recess 17.

As an example, please continue to refer to fig. 10-11, in step S101, the second sacrificial strip 122 is removed during the process of removing the sacrificial layer 12 between the capacitors adjacent in the first direction by using a wet etching process to obtain the bit line recess 18, in step S102, the conductive layer 50 may be formed in the interlayer recess 17 by using a deposition process, in the process of forming the conductive layer 50, the bit line 501 is formed in the bit line recess 18, and the bit lines adjacent in the direction perpendicular to the substrate 100 are insulated by the dielectric layer 11. The material of bit line 501 is selected from the group consisting of copper, tungsten, aluminum, copper alloys, titanium nitride, buttons nitride, tantalum nitride, and combinations thereof. The material of the conductive layer 50 is selected from the group consisting of copper, tungsten, aluminum, copper alloys, titanium nitride, buttons nitride, tantalum nitride, and combinations thereof.

As an example, please continue to refer to fig. 10-11, in step S101, the third sacrificial strip 123 is removed during the process of removing the sacrificial layer 12 between the capacitors adjacent in the first direction by using a wet etching process, so as to obtain the side groove 19, in step S102, during the process of forming the conductive layer 50, the common bit line 60 is formed in the side groove 19, the common bit line 60 is electrically connected with the bit line of the same layer, and the common bit line 60 adjacent in the direction perpendicular to the substrate 100 is insulated by the dielectric layer 11.

As an example, please continue to refer to fig. 11, after forming the conductive layer 50, further includes:

Step S111, removing the dummy word line 20 to form a word line hole;

In step S112, word lines extending along the direction perpendicular to the substrate 100, a gate dielectric layer (not shown) and a channel layer (not shown) between the gate dielectric layer and the conductive layer are formed in the word line holes, the gate dielectric layer circumferentially surrounds the word lines, the channel layer circumferentially surrounds the gate dielectric layer, and the channel layers adjacent in the vertical direction are insulated from each other by the gate dielectric layer.

As an example, please continue to refer to fig. 11, after the dummy word line 20 is removed in step S111, an initial word line hole is obtained, and then the dielectric layer 11 is laterally etched through the initial word line hole to increase the size of the initial word line hole in the etched dielectric layer 11, so that the size of the initial word line hole in the etched dielectric layer 11 is larger than the size of the initial word line hole in the conductive layer 50, thereby obtaining a word line hole. The word line hole disconnects the first electrode (one of the source and drain electrodes) and the second electrode (the other of the source and drain electrodes) of the transistor connected at the time of the second replacement of the sacrificial layer.

Then, a channel layer is formed on the inner surface of the word line hole in the conductive layer 50, a gate dielectric layer covering the channel layer and extending in the oz direction is formed in the word line hole, and then a word line extending in the oz direction is formed in the word line hole. Adjacent channel layers along the oz direction are mutually insulated through the gate dielectric layer so as to reduce parasitic capacitance and leakage current, thereby improving the working efficiency of the transistor and improving the yield of the vertical oxide channel device. The material of the channel layer may be indium tin oxide, i.e., ITO (Indium Tin Oxide) thin film. The material of the gate conductive layer is selected from indium tin oxide, polysilicon, copper, tungsten, aluminum, copper alloy, titanium nitride, tantalum nitride, and combinations thereof. The gate dielectric layer may be formed of a material selected from the group consisting of silicon dioxide (silicon oxide ₂), silicon oxynitride (silicon oxide N), silicon nitride, aluminum oxide (Al ₂O₃), aluminum oxynitride (AlON), and combinations thereof. The gate dielectric layer may also be a high-k dielectric material (a dielectric material having a dielectric constant greater than or equal to 3.9), or a low-k dielectric material (a dielectric constant greater than or equal to 2.5 and less than 3.9), an ultra-low-k dielectric material (a dielectric constant less than 2.5), a ferroelectric material, an antiferroelectric material, silicon carbide (SiC), or any combination thereof. The material of the word line is selected from copper, tungsten, aluminum, copper alloys, and combinations thereof.

According to the memory and the manufacturing method provided by the embodiment of the application, after the sacrificial layer and the dielectric layer are stacked, the conductive layer is used for replacing the sacrificial layer to realize the transistor and the capacitor of the memory unit, wherein the sacrificial layer of the capacitor area is replaced by the conductive layer, the conductive layer and the dielectric layer of the capacitor area are used for supporting, and then the sacrificial layer of the transistor area is replaced by the conductive layer, so that the mechanical stability of the capacitor and the transistor formed by the sacrificial layer and the dielectric layer stacking process can be improved, and the collapse risk is avoided.

In addition, the inner electrode of the capacitor is formed and then the outer electrode is formed, then the sacrifice layer is replaced by the electrode of the transistor and the bit line, and the outer electrode of the capacitor or the whole capacitor is used as a supporting frame for forming the electrode of the transistor and the bit line, so that the supporting frame does not need to be additionally manufactured.

In some embodiments, referring to FIG. 11, a memory is provided, which includes a substrate 100, word lines, bit lines 501, and an array of memory cells stacked in a vertical direction perpendicular to the substrate 100, one layer of the array of memory cells includes memory cells arranged in rows and columns in a first direction and a second direction, the first direction and the second direction intersect and are parallel to the substrate 100, adjacent memory cells in the second direction in the array of memory cells share a bit line 501 extending in the second direction, capacitors of the memory cells are located on a side of the corresponding word line facing away from the corresponding bit line 501 in the first direction, the capacitors include an inner electrode 41, an intermediate dielectric layer 42 circumferentially surrounding a side surface of the inner electrode 41, and an outer electrode 43 circumferentially surrounding a side surface of the intermediate dielectric layer 42, the inner electrode 41 is connected to the corresponding bit line 501 via the corresponding conductive layer 50, the word lines vertically intersect the conductive layer 50 adjacent in the vertical direction, the adjacent memory cells in the second direction share an outer electrode 43, and the outer electrode 43 extends in the vertical direction to the substrate 100.

As an example, please continue to refer to fig. 11, by providing adjacent memory cells along the vertical direction to share a word line extending along the vertical direction, and providing adjacent memory cells along the second direction to share a bit line 501 extending along the second direction in a layer of memory cell array, it is convenient to form a capacitor sharing an external electrode 43 extending along the second direction and the vertical direction on one side of the word line away from the corresponding bit line 501 along the first direction, and the adjacent capacitor along the first direction is utilized as a supporting frame, so that the mechanical supporting performance of a plurality of memory cells stacked on the pair of the three is guaranteed without additional manufacturing of the supporting frame, and the performance and reliability of the manufactured memory are improved.

As an example, please continue to refer to fig. 11, the inner electrode and the first electrode are patterned to form different conductive layers, because the first electrode and the inner electrode are formed by replacing the conductive layers twice, which cannot be formed for the same layer. The different layers may also be layers of the same material or layers of different materials.

The first electrode, the second electrode and the bit line are formed by patterning the same conductive film layer, because the sacrificial layers of the transistor areas and the sacrificial layers of the bit line areas of the two memory cells are etched at one time when the sacrificial layers are replaced by the conductive layers for the second time, then the conductive layers are filled, the conductive layers are an integral film layer, the first electrode and the second electrode serving as a source electrode and a drain electrode are disconnected by patterning the conductive layers, the first electrode is in contact with the inner electrode of the capacitor, and the second electrode and the bit line are in an integral structure. At this time, if the bit line region is not subjected to isolation processing, the bit lines are simultaneously connected to two rows of memory cells, and if the bit line is subjected to patterning processing, the bit line region can be divided into two bit lines, and each bit line is connected to one row of memory cells.

The memory cell further includes a channel layer located between the first electrode and the second electrode around a sidewall of the word line, the channel layer being insulated from the word line by a gate dielectric layer.

One of the bit lines is connected with each second electrode of two adjacent columns of memory cells, wherein the two adjacent columns of memory cells are distributed in a mirror symmetry mode relative to the bit line;

The bit lines, the second electrodes and the first electrodes of the two rows of memory cells are formed by replacing sacrificial layers between two adjacent dielectric layers once;

the first electrodes, the second electrodes and the bit lines are formed by patterning the same conductive film layer.

Illustratively, the dielectric layer and the outer electrode are formed before the bit line is formed after the inner electrode is formed, and the dielectric layer and the outer electrode serve as a support frame.

The dielectric layer and the external electrode cover the inner electrode of each memory cell stacked in the area where the memory cells connected by the bit line are located, each inner electrode connected to the same bit line has upper and lower surfaces and side surfaces and an end surface far away from the bit line, and the dielectric layer and the external electrode cover only the upper and lower surfaces and the side surfaces of each inner electrode;

The dielectric layer and the external electrode are formed by replacing the dielectric layer of the capacitor region.

As an example, referring to fig. 11, adjacent memory cells in a first direction in a layer of memory cell array share a bit line 501 extending in a second direction, so as to reduce the volume of the memory cell array and reduce the complexity and cost of manufacturing the bit line 501.

As an example, please continue to refer to fig. 11, the memory further includes a common bit line 60 located at one side of the memory cell array along the second direction, the common bit line 60 is electrically connected with the bit lines 501 of the same layer, so that the bit lines 501 of the same layer are led out through the corresponding common bit line 60, and thus the bit lines 501 of each layer are selected simultaneously through the common bit line 60 of each layer, so that the complexity of the internal circuit wiring of the memory is reduced, and the volume of the memory is reduced.

As an example, please continue to refer to fig. 11, the dimension of the common bit line 60 along the first direction is larger than the dimension of the bit line 501 along the first direction to reduce the connection resistance of the common bit line 60 and the common bit line 501.

As an example, please continue to refer to fig. 11, the area of the inner electrode 41 covered by the intermediate dielectric layer 42 is larger than or equal to the area of the inner electrode 41 covered by the outer electrode 43, so that the adjacent inner electrodes 41 along the second direction and the vertical direction are insulated from each other via the intermediate dielectric layer 42.

As an example, please continue to refer to fig. 11, the intermediate dielectric layer 42 has an opening (not shown) exposing the target end face 41a of the inner electrode 41, where the target end face 41a is the end face of the inner electrode 41 located on the side of the corresponding word line away from the corresponding bit line 501 along the first direction, so as to facilitate the electrical connection between the target end face of the inner electrode 41 and the ground line, reduce the size and manufacturing complexity of the memory, and improve the performance and reliability of the memory.

As an example, please continue with reference to fig. 11, the material of the inner electrode 41 is selected from the group consisting of doped silicon, polysilicon, copper, tungsten, aluminum, copper alloy, titanium nitride, nitride buttons, and combinations thereof.

As an example, with continued reference to fig. 11, the material of the conductive layer 50 is selected from copper, tungsten, aluminum, copper alloys, and combinations thereof.

As an example, with continued reference to fig. 11, the material of the outer electrode 43 is selected from the group consisting of doped silicon, polysilicon, copper, tungsten, aluminum, copper alloy, titanium nitride, nitride buttons, and combinations thereof.

In some embodiments, the present disclosure provides an electronic device comprising a memory as in any of the embodiments of the present disclosure. Such as, but not limited to, consumer electronics, home electronics, vehicle electronics, financial terminal products, and the like. Consumer electronics such as cell phones, tablet computers, notebook computers, desktop displays, computer all-in-one machines, and the like. Household electronic products are, for example, intelligent door locks, televisions, refrigerators, wearable devices and the like. The vehicle-mounted electronic products are, for example, vehicle-mounted navigator, vehicle-mounted DVD and the like. Financial terminal products such as terminals for ATM machines, self-service transactions, etc.

Note that the above embodiments are for illustrative purposes only and are not meant to limit the present disclosure.

In this specification, each embodiment is described in a progressive manner, and each embodiment is mainly described by differences from other embodiments, and identical and similar parts between the embodiments are all enough to be referred to each other.

The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.

The foregoing examples merely represent several embodiments of the present disclosure, which are described in more detail and are not to be construed as limiting the scope of the disclosure. It should be noted that variations and modifications can be made by those skilled in the art without departing from the spirit of the disclosure, which are within the scope of the disclosure. Accordingly, the scope of protection of the present disclosure should be determined by the following claims.

Claims (14)

1. A memory, comprising:

The memory cell array is positioned on a substrate and is stacked along the direction vertical to the substrate, and each layer of memory cell array comprises memory cells distributed along rows and columns in a first direction and a second direction;

a plurality of word lines extending in a direction perpendicular to the substrate, penetrating through the memory cell arrays of each layer, each of the word lines being connected to the plurality of memory cells;

A plurality of bit lines extending in the second direction, each bit line being connected to at least one column of memory cells in one memory cell array;

each memory unit comprises a transistor and a capacitor which are distributed in sequence in the first direction, wherein the capacitor comprises an inner electrode extending in the first direction, a dielectric layer and an outer electrode which cover the inner electrode in sequence, and the transistor comprises a first electrode electrically connected with the inner electrode and a second electrode connected with the bit line;

A dielectric layer is arranged between any two layers of memory cell arrays;

the internal electrode is formed by replacing a sacrificial layer between two adjacent dielectric layers, and the first electrode, the second electrode and the bit line are formed by replacing the sacrificial layer between two adjacent dielectric layers after the internal electrode is formed.

2. The memory of claim 1, wherein the inner electrode and the first electrode are patterned from different conductive layers;

The first electrode, the second electrode and the bit line are formed by patterning the same conductive layer.

3. The memory of claim 1, wherein the memory cell further comprises a channel layer located between the first electrode and the second electrode around a sidewall of the word line, the channel layer being insulated from the word line by a gate dielectric layer.

4. The memory of claim 1, wherein one of said bit lines is connected to each second electrode of two adjacent columns of memory cells, said two adjacent columns of memory cells being mirror symmetrically distributed about said bit line;

The bit lines, the second electrodes and the first electrodes of the two rows of memory cells are formed by replacing a sacrificial layer between two adjacent dielectric layers at one time, and the first electrodes, the second electrodes and the bit lines are formed by patterning the same conductive layer.

5. The memory of claim 4, wherein the dielectric layer and the outer electrode are formed after forming the inner electrode and before forming the bit line, the outer electrode acting as a support frame.

6. The memory of claim 5 wherein said dielectric layer and said outer electrode cover a column of memory cells and each inner electrode of each memory cell of said column of memory cells stacked in a vertical direction, said dielectric layer and said outer electrode being replaced with a dielectric layer of a capacitor region.

7. The memory of claim 1 wherein the dielectric layer is silicon oxide and the sacrificial layer is silicon nitride or silicon oxynitride.

8. An electronic device comprising the memory of any one of claims 1-7.

9. A method of manufacturing a memory, comprising:

Providing a substrate, and forming a plurality of dielectric layers and a plurality of sacrificial layers on the substrate, wherein the dielectric layers and the sacrificial layers are alternately distributed;

The dielectric layer and the sacrificial layer are subjected to a patterning process to form a plurality of grooves perpendicular to the substrate, a plurality of first sacrificial strips which extend along a first direction and are distributed at intervals along a second direction and are in one-to-one correspondence with the memory cells, and second sacrificial strips which are intersected with the plurality of first sacrificial strips are arranged among the grooves, the dielectric layer stacked with the plurality of first sacrificial strips and the second sacrificial strips of each layer is also arranged among the grooves, the first direction is a row direction, the second direction is a column direction, and the row direction and the column direction are parallel to the substrate;

The first sacrificial strip sequentially comprises a capacitor region and a transistor region in a first direction, and the transistor region is close to the second sacrificial strip;

removing the capacitance area of the first sacrificial strip through an etching process, exposing the dielectric layers adjacent in the vertical direction, and reserving the transistor area of the first sacrificial strip;

filling a conductive layer between the exposed dielectric layers to replace the capacitance area of the first sacrificial strip, so as to form an inner electrode;

And removing the transistor area of the first sacrificial strip and the second sacrificial strip through an etching process after the inner electrode is formed, exposing the adjacent dielectric layers in the vertical direction, filling a conductive layer between the adjacent dielectric layers, and replacing the transistor area and the second sacrificial strip to form a first electrode, a second electrode and a bit line which are in contact with the inner electrode.

10. The method of manufacturing a memory device according to claim 9, wherein before forming the internal electrode, the trench is filled with the same material as the dielectric layer, a word line hole penetrating each of the dielectric layer and each of the sacrificial layers is formed in the transistor region of the first sacrificial strip, and a dummy word line is filled in the word line hole.

11. The method of manufacturing a memory device according to claim 9, wherein the plurality of first sacrificial strips and the second sacrificial strips of each layer are formed as a unitary structure, the first electrode and the second electrode are spaced apart from each other, and the second electrode and the bit line are formed as a unitary structure.

12. The method of claim 10, wherein removing the first sacrificial strip of each capacitor region by an etching process exposes the dielectric layer adjacent in a vertical direction, and wherein retaining the first sacrificial strip of the transistor region comprises:

Removing the dielectric layer between adjacent dielectric layers in the vertical substrate direction, and sequentially filling a first conductive layer between adjacent dielectric layers to serve as an internal electrode.

13. The method of manufacturing a memory according to claim 12, further comprising, after the manufacturing of the internal electrode, before the manufacturing of the first electrode, the second electrode, and the bit line:

and sequentially depositing a dielectric layer and a conductive layer on the exposed inner electrode, wherein the conductive layer is an outer electrode of the capacitor, and the outer electrode is used as a supporting frame.

14. The method of claim 10, wherein removing the transistor region of the first sacrificial strip and the second sacrificial strip to expose adjacent dielectric layers, comprises:

And removing the sacrificial layer between the adjacent dielectric layers in the vertical direction by a wet process to expose the dielectric layers of the first electrode, the second electrode and the bit line region.