CN120222306B - Photovoltaic input port coupling voltage suppression circuit and photovoltaic system - Google Patents
Photovoltaic input port coupling voltage suppression circuit and photovoltaic systemInfo
- Publication number
- CN120222306B CN120222306B CN202510707847.1A CN202510707847A CN120222306B CN 120222306 B CN120222306 B CN 120222306B CN 202510707847 A CN202510707847 A CN 202510707847A CN 120222306 B CN120222306 B CN 120222306B
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
- H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
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Abstract
The invention discloses a photovoltaic input port coupling voltage suppression circuit and a photovoltaic system, which comprise a plurality of resistors, a plurality of operational amplifiers, a plurality of switching tubes, a diode and a relay, wherein one end of each resistor R1 of the plurality of resistors is connected with a coupling voltage V2 and a public end of the relay K1, the other end of each resistor is connected with an in-phase end of the operational amplifier U1, the output end of each operational amplifier U1 is connected with an inverting end and one end of each resistor R4, the other end of each resistor R4 is connected with one end of each resistor R6 and the in-phase end of each operational amplifier U3, the inverting end of each operational amplifier U3 is connected with one end of each resistor R5 and one end of each resistor R8, the other end of each output end of each operational amplifier U3 is connected with the grid electrode of a MOS tube Q1, the source electrode of each MOS tube Q1 is connected with one end of each CE1 line or each CE2 line, the other end of each CE1 line is connected with a normally-closed contact of the relay K1, the other end of each operational amplifier U2 is connected with the other, the other end of each resistor R5 is connected with the other, the in-phase end of each operational amplifier U2 is provided with a normally-on voltage difference reference voltage of each MOS tube Q1, and the normally-open contact of the relay K1 is connected with one end of each photovoltaic end is connected with one end.
Description
Technical Field
The invention relates to the technical field of photovoltaics, in particular to a photovoltaic input port coupling voltage suppression circuit and a photovoltaic system.
Background
The function of the photovoltaic inverter is to convert direct current generated by the photovoltaic panel into alternating current so as to meet the electricity demand of a power grid or a load, a plurality of input ends are provided for a typical photovoltaic inverter, each port can be connected with one or a plurality of photovoltaic panel components, and aiming at the voltage coupling problem in the photovoltaic inversion process, the patent CN118783384a proposes a photovoltaic input port coupling voltage suppression circuit and a photovoltaic system solution, the solution can effectively release coupling voltage on a no-input line by setting an accurate threshold voltage mode, however, as the output voltage of the photovoltaic panel can fluctuate along with the change of illumination intensity and temperature, the fluctuation can be further amplified after the inversion and the coupling process, a dynamic coupling voltage which is difficult to accurately predict is formed, the driving voltage of a switching tube can deviate from an optimal working interval, when the deviation amplitude exceeds the VGS breakdown threshold value of the switching tube, faults such as device burnout or starting failure are extremely easy to be caused, and the switching tube is in a cut-off state when the coupling voltage approaches to the threshold value due to the switching tube itself, so that residual voltage which is difficult to eliminate can be generated.
Disclosure of Invention
Aiming at the defects of the prior art, the invention provides a photovoltaic input port coupling voltage suppression circuit and a photovoltaic system, and solves the problems in the background art.
The photovoltaic input port coupling voltage suppression circuit comprises a plurality of resistors, a plurality of operational amplifiers, a plurality of switching tubes, a diode and a relay, wherein one end of each resistor R1 is connected with a coupling voltage V2 and a common end of each relay K1, the other end of each resistor is connected with an in-phase end of each operational amplifier U1, the output end of each operational amplifier U1 is connected with a reverse phase end and one end of each resistor R4, the other end of each resistor R4 is connected with one end of each resistor R6 and the in-phase end of each operational amplifier U3, the reverse phase end of each operational amplifier U3 is connected with one end of each resistor R5, one end of each resistor R8 is connected, the output end of each resistor R8 is connected with the other end of each resistor R1 and the grid electrode of each MOS transistor, the source electrode of each MOS transistor Q1 is connected with one end of a CE1 circuit or a CE2 circuit, the other end of each CE1 circuit is connected with the normally-closed contact of the relay K1, the output end of each operational amplifier U2 is connected with the reverse phase end and the other end of each resistor R5, the operational amplifier U2 is provided with MOS transistor Q1 on-voltage difference reference voltage, the normally-open contact of each relay K1 is connected with the input voltage V1 and the in-phase end of each resistor R10, one end of each resistor R10 is connected with one end of the resistor R6 and the other, the other end of the resistor R1 is connected with the other end of the same end of the transistor Q1 and the power coil is connected with the other 1;
In order to solve the burning and starting faults caused by the deviation of the driving voltage when the coupling voltage changes and the starting faults caused by the deviation of the driving voltage exceeding a breakdown threshold value and the bleeding residues generated when the coupling voltage approaches but does not reach the threshold value, the VGS voltage of the MOS tube Q1 is controlled to be always at an optimal working point by sampling the coupling voltage V2, wherein the input voltage of a photovoltaic input end is marked as V1, the coupling voltage on a line is marked as V2, a resistor R1 firstly samples and detects the coupling voltage V2 on a photovoltaic input end, the sampling voltage is fed back to the same-phase end of the operational amplifier U1, the inverting end of the operational amplifier U1 is connected with the output end of the operational amplifier U1, the operational amplifier U1 isolates the output coupling voltage V2, the signal of the output end of the operational amplifier U1 is fed back to the same-phase end of the operational amplifier U3 after being looped through a resistor R4 and a resistor R6, and simultaneously the optimal differential voltage parameter signal of the grid electrode of the MOS tube Q1 is input to the source of the same-phase end of the operational amplifier U2 and is isolated by the output end of the operational amplifier U2 through a resistor R5, after the output end of the operational amplifier U3 forms feedback with the inverting end of the operational amplifier U3 through a resistor R8, the voltage difference input to the non-inverting end of the operational amplifier U3 and the inverting end of the operational amplifier U3 outputs the optimal driving voltage VGS based on the current V2 voltage to the grid electrode of the MOS tube Q1, so that the driving voltage VGS deviation of the MOS tube Q1 exceeds a breakdown threshold value when the coupling voltage V2 changes is avoided, when the operational amplifier U3 outputs the MOS tube Q1, the MOS tube Q1 is conducted, the source electrode of the MOS tube Q1 discharges the coupling voltage V2 through a CE1 or CE2 back-stage circuit, the output end of the operational amplifier U3 compensates the negative pressure to the grid electrode of the MOS tube Q1 to enable the MOS tube Q1 to be still at the optimal working point to discharge the residual voltage, the resistor R10 is a sampling resistor for sampling the input voltage V1 of the photovoltaic input end and inputting the input voltage V1 to the non-inverting end of the operational amplifier U4, when the non-rail device is adopted in the operational amplifier, a reference voltage is set by a resistor R7 and a resistor R9 or a power supply, the voltage parameter is larger than the offset voltage, when the non-rail device is adopted in the operational amplifier, the operational amplifier U4 outputs a grounding terminal potential when the non-rail device is not input in the operational amplifier U4, the resistor R7 can be removed at the moment, when the input voltage V1 of the photovoltaic input terminal is true, the operational amplifier U4 compares the voltage of the non-rail device and the non-rail device, the output signal is transmitted to the base electrode of a triode Q2, the triode Q2 is conducted, one end of a coil of a relay K1 is closed through a resistor R11, the collector electrode of the triode Q2, the emitter electrode of the triode Q2 and the grounding terminal loop, the auxiliary contact of the relay K1 is normally open, the connection between V2 and the source electrode of the MOS tube Q1 is disconnected, when the input voltage V1 of the photovoltaic input terminal is false, the relay K1 is reset to be in a drawing state, and a CE1 circuit or a CE2 circuit is connected with the source electrode of the MOS tube Q1 to limit current.
The digital potentiometer comprises a resistor, a plurality of operational amplifiers, a capacitor, an inverter and a digital potentiometer, wherein one end of the resistor R15 in the resistor, the 3 pin of the digital potentiometer and the other end of the CE2 are connected in a circuit, the other end of the resistor is connected with one end of the resistor R16 and the same-phase end of the operational amplifier U7, the inverting end of the operational amplifier U7 is connected with one end of the capacitor C1, one end of the resistor R17 is connected with the other end of the resistor R16, the other end of the resistor R17 and the inverting end of the operational amplifier U6, the same-phase end of the operational amplifier U6 is provided with voltage drop change point reference voltage of the resistor R15 and the resistor R16, the 1 pin of the digital potentiometer U5 is connected with the output end of the operational amplifier U6, the 5 pin is connected with the 6 pin and one end of the CE2 circuit, the 2 pin is connected with the output end of the inverter U8, the 7 pin is connected with the ground, the input end of the inverter U8 is connected with the output end of the operational amplifier U4, and the other end of the capacitor C1 is connected with the ground;
Wherein, when the fluctuation range of the coupling voltage V2 is overlarge, the coupling voltage V2 can be connected with the source electrode of the MOS tube Q1 through CE2, so that the discharge rate of the MOS tube Q1 is kept consistent when the coupling voltage V2 changes, the occurrence of overcurrent and discharge slow voltage accumulation is avoided, wherein, the resistance input end of the digital potentiometer U5 is used as a current limiting auxiliary contact connected with the normally closed relay K1, the cursor and the resistance output end are connected in parallel and then connected with the source electrode of the MOS tube Q1, the seventh pin of the digital potentiometer U5 is connected with the ground in default when no upper control is performed, the second pin of the digital potentiometer U5 is controlled by the output end of the inverter U8, when the input voltage V1 of the photovoltaic input end is false, the inverting end of the operational amplifier U4 is larger than the voltage of the same-phase end of the operational amplifier U4, the voltage is output when the operational amplifier U4 is cut off or is not on, the voltage potential is lower than the conduction positive pressure of the NMOS tube inside the inverter U8, the inverter U8 still inverts the output signal to the second pin of the digital potentiometer U5, when the second pin of the digital potentiometer U5 is input, the digital potentiometer U5 is ready to be regulated from high resistance to low resistance, a regulating signal is input to the first pin of the digital potentiometer U5 by the operational amplifier U6, meanwhile, the coupling voltage is sampled by the resistor R15 and then is input to the in-phase end of the operational amplifier U7, the coupling voltage at the end of the resistor R15 is input to the output end of the operational amplifier U7, the voltage of the connecting end of the sampling capacitor C1 and the resistor R17 is input to the output end of the operational amplifier U7 by the resistor R16, when the digital potentiometer U5 is electrified, the voltage of the in-phase end of the operational amplifier U7 is greater than the voltage of the inverting end of the operational amplifier U7, the output signal is fed back to the capacitor C1 by the resistor R17, the coupling voltage V2 at the end of the resistor R15 is fed back to the output end of the operational amplifier U7 by the resistor R16 when the voltage of the inverting end of the operational amplifier U7 is increased by the resistor R17 and the voltage of the capacitor C1 is not output by the operational amplifier U7, when the voltage of the end of the capacitor C1 is lower than the same-phase end of the operational amplifier U7, the operational amplifier U7 outputs the voltage of the connecting end of the resistor R15 and the resistor R16 to be pulled up again, the resistor R17 and the capacitor C1 are integrated again, when the coupling voltage V2 changes, the voltage drop of the connecting end of the resistor R15 and the resistor R16 is increased, a signal is fed back to the inverting end of the operational amplifier U6 during the voltage drop period of the resistor R15 and the resistor R16 by the output end of the operational amplifier U7, the voltage drop change point reference voltage of the resistor R15 and the resistor R16 is arranged at the same-phase end of the U6, the operational amplifier U6 outputs a signal to the first pin of the digital potentiometer U5, the digital potentiometer U5 is controlled to be adjusted to be low-resistance from high resistance step by step, the discharging rate of the MOS tube Q1 is consistent when the coupling voltage V2 changes, the relay K1 coil is closed to disconnect the source connection of the V2 and the MOS tube Q1 again when the coupling voltage V1 is true, and the reference voltage can be set by resistor voltage division or power supply at the same-phase end of the operational amplifier U2.
Preferably, the circuit further comprises a resistor, wherein the two ends of the CE1 circuit are connected with a resistor R12 in series;
when the coupling voltage V2 is connected to the source of the MOS transistor Q1 through the CE1 line, the loop of V2 is grounded through the normally closed contact of the relay K1, the resistor R12, the source of the MOS transistor Q1, and the drain of the MOS transistor Q1, and the current is limited by the resistor R12.
Preferably, the in-phase end of the operational amplifier U2 is connected with one end of a resistor R2 and one end of a resistor R3, the other end of the resistor R3 is connected with a power supply, and the other end of the resistor R2 is connected with a grounding end;
the non-inverting terminal of the operational amplifier U2 can set the reference voltage through resistor voltage division or power supply.
Preferably, the circuit further comprises a resistor, wherein one end of the resistor R9 in the resistor is connected with the inverting end of the operational amplifier U4, and the other end of the resistor is connected with the grounding end;
when the non-rail device is adopted by the operational amplifier U4, the reference voltage is set by the resistor R7 and the resistor R9 or a power supply, the voltage parameter is larger than the offset voltage, and when the non-input end of the operational amplifier U4 is not used by the rail operational amplifier, the output of the operational amplifier U4 is the ground terminal potential, and at the moment, only the resistor R9 can be adopted.
Preferably, the power supply circuit further comprises a resistor, wherein one end of the resistor R7 in the resistor is connected with the inverting end of the operational amplifier U4, and the other end of the resistor is connected with a power supply;
When the non-rail device is adopted by the operational amplifier, the inverting terminal of the operational amplifier U4 is provided with reference voltage by a resistor R7 and a resistor R9 or a power supply, and the voltage parameter is larger than the offset voltage.
Preferably, the power supply circuit also comprises a plurality of resistors, wherein one end of a resistor R14 in the plurality of resistors is connected with one end of a resistor R13 and the same-phase end of an operational amplifier U6, and the other end of the resistor R13 is connected with a grounding end;
the non-inverting terminals of the operational amplifier U6 and the operational amplifier U2 can be used for setting reference voltage through resistor voltage division or power supply.
The invention also provides a photovoltaic system, which comprises any photovoltaic input port coupling voltage suppression circuit.
The photovoltaic input port coupling voltage suppression circuit and the photovoltaic system provided by the invention have the following beneficial effects:
The voltage of the driving voltage VGS can be always in an optimal working interval when the coupling voltage is changed, faults are avoided after the deviation amplitude exceeds the breakdown threshold value, and compensation is performed to remove residual voltage when the coupling voltage is lower than the conduction threshold value. The voltage release rate can be controlled when the coupling voltage fluctuation is large, and overcurrent and voltage accumulation are avoided.
Drawings
Fig. 1 is a schematic diagram of a photovoltaic input port coupling voltage suppression circuit according to the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The invention provides a photovoltaic input port coupling voltage suppression circuit which comprises a plurality of resistors, a plurality of operational amplifiers, a plurality of switching tubes, a diode and a relay, wherein one end of each resistor R1 of the plurality of resistors is connected with a common end of a coupling voltage V2 and a common end of the relay K1, and the other end of each resistor R1 is connected with an in-phase end of the operational amplifier U1; the output end of the operational amplifier U1 is connected with the inverting end and the resistor R4 end, the other end of the resistor R4 is connected with the resistor R6 end and the same-phase end of the operational amplifier U3, the inverting end of the operational amplifier U3 is connected with the resistor R5 end and the resistor R8 end, the output end is connected with the other end of the resistor R8 and the grid electrode of the MOS transistor Q1, the source electrode of the MOS transistor Q1 is connected with one end of a CE1 line or a CE2 line, the other end of the CE1 line is connected with the normally closed contact of the relay K1, the output end of the operational amplifier U2 is connected with the inverting end and the other end of the resistor R5, the same-phase end of the operational amplifier U2 is provided with the MOS transistor Q1 conduction voltage difference reference voltage, the normally open contact of the relay K1 is connected with the input voltage V1 of the resistor R10 end, the other end of the resistor R10 is connected with the same-phase end of the operational amplifier U4, the output end of the operational amplifier U4 is connected with the base electrode of the triode Q2, the collector electrode of the triode Q2 is connected with one end of the resistor R11, the other end of the resistor R11 is connected with the anode of the D1, one end of the coil of the relay K1 is connected with the other end of the relay, the cathode of the MOS transistor Q1 is connected with the power source, the drain electrode of the triode Q2 is connected with the emitter.
The digital potentiometer comprises a resistor, a plurality of operational amplifiers, a capacitor, an inverter and a digital potentiometer, wherein one end of the resistor R15 in the resistor is connected with the other end of the CE2 in a line manner, the other end of the resistor is connected with one end of the resistor R16 and the same-phase end of the operational amplifier U7, the inverting end of the operational amplifier U7 is connected with one end of the capacitor C1 and one end of the resistor R17, the other end of the resistor R16, the other end of the resistor R17 and the inverting end of the operational amplifier U6 are connected, the 1 pin of the digital potentiometer U5 is connected with the output end of the operational amplifier U6, the 5 pin is connected with one end of the CE2 in a line manner, the 2 pin is connected with the output end of the inverter U8, the 7 pin is connected with the ground end of the inverter U8 in an input end of the operational amplifier U4, and the other end of the capacitor C1 is connected with the ground end of the operational amplifier U1.
Specifically, the circuit also comprises a resistor, and the two ends of the CE1 circuit are connected in series with a resistor R12.
Specifically, the in-phase end of the operational amplifier U2 is connected with one end of the resistor R2 and one end of the resistor R3, the other end of the resistor R3 is connected with a power supply, and the other end of the resistor R2 is connected with a grounding end.
Specifically, the resistor is further comprised, one end of the resistor R9 in the resistor is connected with the inverting end of the operational amplifier U4, and the other end of the resistor R9 is connected with the grounding end.
Specifically, the power supply circuit further comprises a resistor, wherein one end of the resistor R7 in the resistor is connected with the inverting end of the operational amplifier U4, and the other end of the resistor is connected with a power supply.
The resistor comprises a resistor R14, a resistor R13, an operational amplifier U6 and a grounding terminal, wherein the resistor R14 is connected with the same-phase terminal of the resistor R13; the other end of the resistor R13 is connected with a power supply.
The invention also provides a photovoltaic system comprising the photovoltaic input port coupling voltage suppression circuit.
Referring to fig. 1, in an embodiment, to solve the burnout and start-up faults caused by the deviation of the driving voltage beyond the breakdown threshold when the coupling voltage changes and the residual leakage generated when the coupling voltage approaches but does not reach the threshold, the VGS voltage of the MOS transistor Q1 is always at the optimal operating point by sampling the coupling voltage V2, wherein the input voltage of the photovoltaic input terminal is marked as V1, the coupling voltage on the line is marked as V2, the resistor R1 firstly samples and detects the coupling voltage V2 on the photovoltaic input terminal, the sampled voltage is fed back to the in-phase terminal of the op-amp U1, the inverting terminal of the op-amp U1 is connected with the output terminal of the op-amp U1, the op-amp U1 isolates the output coupling voltage V2, the signal of the output terminal of the op-amp U1 is fed back to the in-amp U3 through the resistor R4 and the resistor R6 loop, and the optimal differential voltage parameter signal of the gate to the source of the op-amp U2 is input to the inverting terminal of the op-amp U3 through the resistor R5, after the output end of the operational amplifier U3 forms feedback with the inverting end of the operational amplifier U3 through a resistor R8, the voltage difference input to the non-inverting end of the operational amplifier U3 and the inverting end of the operational amplifier U3 outputs the optimal driving voltage VGS based on the current V2 voltage to the grid electrode of the MOS tube Q1, so that the driving voltage VGS deviation of the MOS tube Q1 exceeds a breakdown threshold value when the coupling voltage V2 changes is avoided, when the operational amplifier U3 outputs the MOS tube Q1, the MOS tube Q1 is conducted, the source electrode of the MOS tube Q1 discharges the coupling voltage V2 through a CE1 or CE2 back-stage circuit, the output end of the operational amplifier U3 compensates the negative pressure to the grid electrode of the MOS tube Q1 to enable the MOS tube Q1 to be still at the optimal working point to discharge the residual voltage, the resistor R10 is a sampling resistor for sampling the input voltage V1 of the photovoltaic input end and inputting the input voltage V1 to the non-inverting end of the operational amplifier U4, when the operational amplifier adopts a non-rail device, a reference voltage is set by a resistor R7 and a resistor R9 or a power supply, the voltage parameter is larger than offset voltage, when the operational amplifier adopts a rail operational amplifier, the operational amplifier U4 outputs a ground terminal potential when the non-rail device adopts the non-rail operational amplifier, the resistor R7 can be removed, when the input voltage V1 of the photovoltaic input terminal is true, the operational amplifier U4 compares the voltage of the non-rail device and outputs a signal to the base electrode of a triode Q2, the triode Q2 is conducted, one end of a coil of a relay K1 is closed by a resistor R11, the collector electrode of the triode Q2, the emitter electrode of the triode Q2 and a ground terminal loop, an auxiliary contact of the relay K1 is normally open, the connection between V2 and the source electrode of the MOS tube Q1 is disconnected, when the input voltage V1 of the photovoltaic input terminal is false, a CE1 line or a CE2 line is connected with the source electrode of the MOS tube Q1 to limit current, and when the coupling voltage V2 is connected with the MOS tube Q1 by the CE1 line, the normally closed contact of the MOS tube Q1, the relay K1 is connected with the drain electrode of the MOS tube Q1 by the resistor R12, and the drain electrode of the MOS tube Q1.
Referring to fig. 1, in an embodiment, when the fluctuation range of the coupling voltage V2 is too large, the coupling voltage V2 can be connected with the source of the MOS transistor Q1 through CE2, so that the discharging rate of the MOS transistor Q1 is kept consistent when the coupling voltage V2 changes, and over-current and slow-voltage accumulation are avoided, wherein the resistance input end of the digital potentiometer U5 is used as a current-limiting auxiliary contact connected with the normally closed relay K1, the cursor and the resistance output end are connected in parallel and then connected with the source of the MOS transistor Q1, the seventh pin of the digital potentiometer U5 is connected with ground by default when no upper control is performed, the second pin of the digital potentiometer U5 is controlled by the output end of the inverter U8, when the input voltage V1 of the photovoltaic input end is false, the inverting end of the operational amplifier U4 is greater than the voltage of the same-phase end of the operational amplifier U4, the operational amplifier U4 outputs an offset voltage when the non-rail is cut off, the voltage potential is lower than the conduction positive pressure of the NMOS transistor inside the inverter U8, the inverter U8 still inverts the output signal to the second pin of the digital potentiometer U5, when the second pin of the digital potentiometer U5 is input, the digital potentiometer U5 is ready to be regulated from high resistance to low resistance, a regulating signal is input to the first pin of the digital potentiometer U5 from the operational amplifier U6, meanwhile, the coupling voltage is sampled by the resistor R15 and then is input to the in-phase end of the operational amplifier U7, the coupling voltage V2 at the end of the resistor R15 is fed back to the output end of the operational amplifier U7 through the resistor R16, the voltage of the connecting end of the capacitor C1 and the resistor R17 is integrated, the voltage of the in-phase end of the operational amplifier U7 is larger than the voltage of the in-phase end of the operational amplifier U7, the output signal is fed back to the capacitor C1 through the resistor R17 when the voltage of the in-phase end of the operational amplifier U7 is increased, the coupling voltage V2 at the end of the resistor R15 is fed back to the output end of the operational amplifier U7 through the resistor R16, the voltage of the connecting end of the resistor R15 and the resistor R16 is reduced, meanwhile, the voltage of the end of the capacitor C1 is fed back to the output end of the operational amplifier U7 through the resistor R17, the voltage of the capacitor C1 is gradually reduced, when the voltage of the end of the capacitor C1 is lower than the same-phase end of the operational amplifier U7, the operational amplifier U7 outputs the voltage which enables the connecting end of the resistor R15 and the resistor R16 to be pulled up again, the resistor R17 and the capacitor C1 are integrated again, when the coupling voltage V2 changes, the voltage drop of the connecting end of the resistor R15 and the resistor R16 increases, a signal is fed back to the inverting end of the operational amplifier U6 during the voltage drop of the resistor R15 and the resistor R16 by the output end of the operational amplifier U7, the voltage drop change point reference voltage of the resistor R15 and the resistor R16 is arranged at the same-phase end of the U6, the output signal of the operational amplifier U6 is controlled to be gradually reduced to low-resistance by the high-resistance, the release rate of the MOS tube Q1 is enabled to be consistent when the coupling voltage V2 changes, the coil of the relay K1 is closed again, the connection between the MOS tube Q2 and the source of the MOS tube Q1 is disconnected when the input voltage V1 is true, and the voltage of the operational amplifier U2 can be set through the resistor or the voltage divider.
Although embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made hereto without departing from the spirit and principles of the present invention.
Claims (8)
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| CA2406500C (en) * | 2001-10-01 | 2008-04-01 | Research In Motion Limited | An over-voltage protection circuit for use in a charging circuit |
| CN104466898A (en) * | 2013-09-24 | 2015-03-25 | 成都新方洲信息技术有限公司 | Overvoltage protective device for internet-of-things radio frequency emitter |
| CN108574263A (en) * | 2017-03-10 | 2018-09-25 | 深圳市三诺声智联股份有限公司 | A kind of over-pressed and surge protection circuit |
| CN108471231B (en) * | 2018-04-23 | 2020-11-03 | 陕西雷能电子科技有限公司 | Absorption device for absorbing back electromotive force |
| CN112769102B (en) * | 2019-11-04 | 2025-08-08 | 苏州海鹏科技有限公司 | Photovoltaic inverter and its DC bus capacitor protection circuit |
| CN118783384A (en) * | 2024-08-08 | 2024-10-15 | 深圳正泰电源系统有限公司 | Photovoltaic input port coupling voltage suppression circuit and photovoltaic system |
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| CN101055983A (en) * | 2006-04-13 | 2007-10-17 | 艾默生网络能源系统有限公司 | Hardware overvoltage breaking-off circuit |
| CN103107518A (en) * | 2012-12-24 | 2013-05-15 | 深圳创动科技有限公司 | Photovoltaic inverter and protector thereof |
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| CN120222306A (en) | 2025-06-27 |
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