CN120264829A - Semiconductor structure - Google Patents
Semiconductor structure Download PDFInfo
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- CN120264829A CN120264829A CN202510420924.5A CN202510420924A CN120264829A CN 120264829 A CN120264829 A CN 120264829A CN 202510420924 A CN202510420924 A CN 202510420924A CN 120264829 A CN120264829 A CN 120264829A
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- layer
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- conductive layer
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- sidewall
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/113—Isolations within a component, i.e. internal isolations
- H10D62/115—Dielectric isolations, e.g. air gaps
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Abstract
The invention provides a semiconductor structure. The semiconductor structure is provided with the grooves between the adjacent contact pads, and the insulating filling layer filled in the grooves is formed by at least two insulating parts, so that the internal stress of the insulating material in the grooves can be relieved more effectively, and the problem that the adjacent semiconductor devices are damaged due to the high-strength internal stress of the insulating material in the grooves can be solved.
Description
Technical Field
The present disclosure relates to semiconductor technology, and more particularly, to a semiconductor structure.
Background
For semiconductor processing, internal stress has a significant impact on the reliability of the semiconductor device. In particular, as semiconductor technology continues to develop, the size of semiconductor devices continues to shrink, and the effects of internal stresses in semiconductor structures on semiconductor devices become more and more pronounced. In general, the material filled in the grooves generates more internal stress during high temperature processes, which is more likely to affect adjacent semiconductor devices.
Disclosure of Invention
The invention aims to provide a semiconductor structure to solve the problem that the semiconductor device is easily damaged due to high-strength internal stress in the conventional semiconductor structure.
In order to solve the above technical problems, the present invention provides a semiconductor structure, comprising:
The semiconductor device comprises a substrate, wherein at least one semiconductor device and an interlayer dielectric layer are formed in the substrate, and the interlayer dielectric layer covers the semiconductor device;
At least two interconnection structures including a contact plug penetrating the interlayer dielectric layer and extending to the semiconductor device, and a contact pad covering the top of the contact plug and extending to cover part of the top surface of the interlayer dielectric layer, and
A recess between adjacent contact pads, the recess also extending down to stop in the interlayer dielectric layer, and
And an insulation filling layer filled in the groove, and the insulation filling layer includes at least two insulation parts.
Optionally, the insulation filling layer comprises at least two first insulation parts, the two first insulation parts cover two opposite side walls of the groove, the two first insulation parts define a recess in the middle area of the groove, and the semiconductor structure further comprises a shielding layer, wherein the shielding layer covers the contact pad and the insulation filling layer and fills the recess.
Optionally, the bottom of the recess extends to the bottom of the groove, the covering layer fills the recess and extends to the bottom of the groove, and a space is further formed in a portion of the covering layer corresponding to the recess.
Optionally, the semiconductor device comprises a gate conductive layer formed on the top surface of the substrate, the interlayer dielectric layer comprises a shielding layer covering the top surface of the gate conductive layer and a side wall structure covering the side wall of the gate conductive layer and the side wall of the shielding layer, wherein the groove extends downwards into the shielding layer from between adjacent contact pads in the height direction, the groove transversely extends into the side wall structure from the shielding layer in the width direction, the depth value of the groove is not larger than the height value of the gate conductive layer, and the width dimension of the groove is larger than the width dimension of the gate conductive layer.
Optionally, the insulation filling layer further includes a second insulation portion, the second insulation portion covers the bottom of the groove, a gap is formed between the second insulation portion and the first insulation portion, and the gap extends from a corner where the bottom wall and the side wall of the groove are connected to each other toward the direction of the recess.
Optionally, the bottom of the recess extends to the second insulating portion and communicates the void with the recess, and the covering layer fills the recess and closes the opening of the first void.
Optionally, the semiconductor device comprises a gate conductive layer formed on the top surface of the substrate, the interlayer dielectric layer comprises a shielding layer covering the top surface of the gate conductive layer and a side wall structure covering the side wall of the gate conductive layer and the side wall of the shielding layer, wherein the groove extends downwards into the shielding layer from between adjacent contact pads in the height direction, the groove transversely extends into the side wall structure from the shielding layer in the width direction, and the depth value of the groove is not larger than the height value of the gate conductive layer.
Optionally, the semiconductor device includes a gate conductive layer formed on a top surface of the substrate, and the interlayer dielectric layer includes a shielding layer covering the top surface of the gate conductive layer and a sidewall structure covering sidewalls of the gate conductive layer and sidewalls of the shielding layer;
The grooves extend downwards into the shielding layer from between adjacent contact pads in the height direction, the grooves extend transversely into the side wall structure from the shielding layer in the width direction, and the depth value of the grooves is larger than the height value of the grid electrode conducting layer.
Optionally, a void is also formed in a portion of the cover layer corresponding to the recess.
Optionally, a gap is formed between the two first insulating portions in a middle region of the recess, and the gap extends in a height direction below the recess.
Optionally, the cover layer fills the recess and closes the top opening of the void.
Optionally, the semiconductor device comprises a gate conductive layer formed on the top surface of the substrate, and a first source/drain region and a second source/drain region formed in the substrate, wherein the first source/drain region and the second source/drain region are respectively located on two sides of the gate conductive layer, the first source/drain region and the second source/drain region are respectively provided with the interconnection structure, and a contact pad corresponding to the first source/drain region and a contact pad corresponding to the second source/drain region respectively extend transversely from two sides of the gate conductive layer towards the gate conductive layer.
Optionally, the interlayer dielectric layer comprises a shielding layer covering the top surface of the gate conductive layer and a side wall structure covering the side wall of the gate conductive layer and the side wall of the shielding layer, wherein the contact pad corresponding to the first source/drain region and the contact pad corresponding to the second source/drain region respectively extend transversely from two sides of the gate conductive layer to the side wall structure.
Optionally, the recess extends laterally from the shielding layer into the sidewall structure in a width direction, and the recess extends down into the shielding layer from between adjacent contact pads in a height direction.
In the semiconductor structure provided by the invention, the grooves are arranged between the adjacent contact pads, and the grooves are filled with insulating filling layers for separating the adjacent contact pads. And, the insulating filling layer filled in the groove is constituted by at least two insulating portions. Compared with the method for filling the grooves by only filling the grooves with one insulating material with a larger volume, the method for filling the grooves by at least two insulating parts can more effectively relieve the internal stress of the insulating material in the grooves, so that the problem of damage to adjacent semiconductor devices caused by the high-strength internal stress of the insulating material in the grooves can be solved.
Further, the insulating material filled in the grooves may be formed with voids (for example, voids may be formed between adjacent insulating portions), so that stress release of the insulating material can be achieved by using the voids, and internal stress of the insulating material filled in the grooves can be further reduced.
Drawings
FIG. 1 is a schematic diagram of a semiconductor structure according to a first embodiment of the present invention;
fig. 2 is a schematic diagram of a semiconductor structure according to a second embodiment of the invention;
FIG. 3 is a schematic diagram of a semiconductor structure according to a third embodiment of the present invention;
Fig. 4 is a schematic diagram of a semiconductor structure in a fourth embodiment of the invention.
Wherein, the reference numerals are as follows:
100-a substrate;
110-a first source/drain region;
120-second source/drain regions;
200-gate conductive layer;
210-a first conductive layer;
220-a second conductive layer;
230-a third conductive layer;
300-an interconnect structure;
310-contact plugs;
320-contact pads;
400-interlayer dielectric layer;
410-a masking layer;
420-isolating side walls;
430-isolating the dielectric layer;
500-insulating filling layers;
500 a-recessing;
510-a first insulating portion;
520-a second insulating part;
510 a-a first void;
520 a-a second void;
600-covering layer;
600 a-void.
Detailed Description
The semiconductor structure according to the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.
Example 1
Fig. 1 is a schematic view of a semiconductor structure according to a first embodiment of the present invention, as shown in fig. 1, where the semiconductor structure includes:
A substrate 100, wherein at least one semiconductor device and an interlayer dielectric layer 400 are formed in the substrate 100, and the interlayer dielectric layer 400 covers the semiconductor device;
At least two interconnection structures 300, the interconnection structures 300 including a contact plug 310 and a contact pad 320, the contact plug 310 penetrating the interlayer dielectric layer 400 and extending to the semiconductor device, the contact pad 320 covering a top of the contact plug 310 and extending to cover a portion of a top surface of the interlayer dielectric layer 400, and
A recess between adjacent contact pads 320 of the bit line, the recess also extending down to stop in the interlayer dielectric layer 400, and
An insulation filling layer filled in the groove, and the insulation filling layer includes at least two insulation parts (e.g., two first insulation parts 510 shown in fig. 1).
The grooves are formed by etching the interlayer dielectric layer 400 using the adjacent contact pads 320 as a mask, so as to ensure that the adjacent contact pads 320 are separated from each other, and avoid the problem of electrical connection of the adjacent contact pads due to the residual conductive material when the contact pads 320 are manufactured.
In the present embodiment, the insulating filling layer filled in the groove is also made up of at least two insulating portions. It should be noted that filling the recess with a plurality of insulating portions is more advantageous for achieving stress relief of the insulating material in the recess than filling the recess with only one larger volume of insulating portions. Wherein, each insulating part in the insulating filling layer can be formed by adopting the same material, for example, the material of each insulating part comprises silicon nitride or silicon oxide.
With continued reference to fig. 1, the insulating filling layer includes at least two first insulating portions 510, and the two first insulating portions 510 cover two opposite sidewalls of the recess. In this embodiment, the first insulating portion 510 also covers the sidewalls of the contact pad 320 exposed to the recess.
Further, two of the first insulating portions 510 can define a recess 500a in a middle region of the recess. Specifically, two opposite first insulating portions 510 extend from two opposite sidewalls of the recess toward the middle region of the recess, and the recess 500a is defined by the boundaries of the two first insulating portions 510. In this embodiment, the top of the recess 500a is not higher than the top of the groove.
With continued reference to fig. 1, the semiconductor structure further includes a capping layer 600, the capping layer 600 covering the contact pads 320 and the insulating fill layer and filling the recesses 500a.
In this embodiment, the bottom of the recess 500a also extends to the bottom of the groove, that is, the two first insulating parts 510 are separated from each other by the recess 500a located in the middle region. Based on this, the cover layer 600 fills the recess 500a and can extend to the bottom of the groove.
It should be noted that, the recess 500a is located in a space region of the groove, and the cover layer 600 fills the recess 500a, and based on this, it can be considered that the cover layer 600 is at least partially filled in the groove. Therefore, in the groove of the present embodiment, not only the insulation filling layer (including the two first insulation portions 510) but also a part of the cover layer 600 is filled, so that the groove is filled with at least three insulation portions.
The cover layer 600 may be formed of the same material as the insulating filling layer, for example, silicon nitride may be used. The cover layer 600 is formed by using the same material as the insulating filling layer, so that the insulating filling layer and the cover layer 600 have the same or similar thermal expansion coefficients, and the problem of internal stress increase caused by the difference of thermal expansion between different materials can be avoided.
In an alternative, a void 600a may be further formed in a portion of the cover 600 corresponding to the recess 500 a.
Specifically, the width dimension of the recess 500a is at least partially determined by the dimension of the space between the two first insulating portions 510, and the first insulating portions 510 are filled in the grooves, so that the dimension of the space between the two first insulating portions 510 is smaller, and accordingly the width dimension of the defined recess 500a is smaller. And, the recess 500a extends downward in the depth direction to the bottom of the groove, so that the depth value of the recess 500a corresponds to the depth value of the groove. Thus, the aspect ratio of the recess 500a can be made large, and thus the cover layer 600 is easy to form the void 600a in the portion corresponding to the recess 500a when filling the recess 500 a.
In this embodiment, a pit is further formed in the bottom of the recess 500a corresponding to the groove, so that the depth of the recess 500a can be further increased. For example, the bottom of the recess 500a may be made lower than the bottom of the first insulation portion 510. This corresponds to an increase in the aspect ratio of the recess 500a, which may further facilitate the formation of the void 600a in the cap layer 600.
Note that, since a void is formed in the insulating material corresponding to the groove (i.e., a void 600a is formed in a portion of the cover layer 600 corresponding to the groove), stress release of the insulating material filled in the groove can be further achieved by using the void 600 a. For example, when a high temperature process is performed on the semiconductor structure, the insulating material in the groove can realize stress release by using the gap 600a, so that the problem that other components are damaged due to the high-strength stress extrusion of the insulating material in the groove is avoided.
In particular, when the recess is formed directly above the semiconductor device, high-strength internal stress of the insulating material filled in the recess may damage the semiconductor device. As shown in fig. 1, in the present embodiment, an insulating filling layer and a cover layer 600 filled in the recess are formed directly above the semiconductor device.
With continued reference to fig. 1, in this embodiment, the semiconductor device includes, for example, a transistor. Wherein the transistor includes a gate conductive layer 200 formed on the top surface of the substrate 100, and first and second source/drain regions 110 and 120 formed in the substrate 100, the first and second source/drain regions 110 and 120 being located at both sides of the gate conductive layer 200, respectively.
In this embodiment, the gate conductive layer 200 includes a first conductive layer 210, a second conductive layer 220, and a third conductive layer 230 stacked. The material of the first conductive layer 210 includes polysilicon, the material of the second conductive layer 220 includes titanium nitride, and the material of the third conductive layer 230 includes tungsten.
Wherein the interconnection structure 300 is disposed on the first source/drain region 110 and the second source/drain region 120, respectively. Specifically, the contact plugs 310 corresponding to the first source/drain regions and the contact plugs 310 corresponding to the second source/drain regions are respectively formed at both sides of the gate conductive layer 200 and vertically extend to the first source/drain regions 110 and the second source/drain regions 120 of the substrate 100 to be electrically connected to the first source/drain regions 110 and the second source/drain regions 120. And contact pads 320 corresponding to the first source/drain regions and contact pads 320 corresponding to the second source/drain regions extend laterally from both sides of the gate conductive layer 200 in a direction toward the gate conductive layer 200, respectively.
Further, the interlayer dielectric layer 400 includes a shielding layer 410 covering the top surface of the gate conductive layer 200, and an isolation sidewall 420 covering the sidewall of the gate conductive layer 200 and the sidewall of the shielding layer 410.
Specifically, the isolation sidewall 420 is, for example, a stacked structure sequentially covering the gate conductive layer 200. In this embodiment, the isolation sidewall 420 includes a first isolation layer, a second isolation layer, and a third isolation layer that sequentially cover the gate conductive layer 200 from inside to outside. The first isolation layer and the third isolation layer may be formed of the same material, for example, each include silicon oxide, and the second isolation layer may be formed of a material including silicon nitride, for example, so as to form the isolation sidewall 420 of the ONO structure. And, the material of the shielding layer 410 may also include silicon nitride.
In this embodiment, two contact pads 320 corresponding to the first source/drain region 110 and the second source/drain region 120 respectively extend laterally from two sides of the gate conductive layer 200 to above the isolation sidewall 420 in a direction toward the gate conductive layer 200. Based on this, the grooves between the adjacent contact pads 320 extend laterally in the width direction, i.e. from the shielding layer 410 into the isolation sidewall 420, and in this embodiment, the grooves extend laterally in the width direction into the second isolation layer of the isolation sidewall 420, so that the width dimension of the grooves is correspondingly greater than the width dimension of the gate conductive layer 220.
And the grooves extend downward in the height direction from between adjacent contact pads 320 into the masking layer 410 and the isolation sidewall 420. The depth H2 of the groove may be not greater than the height H1 of the semiconductor device above the top surface of the substrate, and in this embodiment, the depth H2 of the groove is not greater than the height H1 of the gate conductive layer 200.
As described above, the width dimension of the groove is larger than the width dimension of the gate conductive layer 200, and thus it is considered that in the present embodiment, the aspect ratio of the groove is small, so that two first insulating portions 510 spaced apart from each other can be formed in the groove, and the two first insulating portions 510 can be spaced apart from each other by the recess 500a having a larger dimension. In this embodiment, the bottom of the recess 500a further extends down into the shielding layer 410, so that the portion of the shielding layer 410 corresponding to the recess 500a is further submerged.
Further, the outer edge boundary of the first insulating portion 510 extends beyond the outer edge boundary of the gate conductive layer 200, and covers the contact pad 320 and the sidewall of the isolation sidewall 410 exposed in the recess.
With continued reference to fig. 1, the interlayer dielectric layer 400 further includes an isolation dielectric layer 430, the isolation dielectric layer 430 is formed on the periphery of the isolation sidewall 420 away from the gate conductive layer 200, and the conductive plug 310 penetrates through the isolation dielectric layer 430.
In addition, in the present embodiment, a void 600a is formed in a portion of the cover layer 600 corresponding to the recess 500 a. However, in other embodiments, a gap may be formed between the cover layer 600 and the insulating filling layer, for example, a gap may be formed between the cover layer 600 and the first insulating portion 510.
Example two
The difference from the first embodiment is that in this embodiment, the insulation filling layer further includes a second insulation portion covering the bottom of the groove.
Fig. 2 is a schematic diagram of a semiconductor structure in a second embodiment of the present invention, as shown in fig. 2, in this embodiment, the insulation filling layer 500 includes two first insulation portions 510 and a second insulation portion 520, where the first insulation portions 510 cover the sidewalls of the grooves, and the second insulation portions 520 cover the bottoms of the grooves.
Further, a gap (i.e., a first gap 510 a) is formed between the second insulating portion 520 and the first insulating portion 510, and the first gap 510a between the first insulating portion 510 and the second insulating portion 520 extends in the direction of the recess 500a from the corner where the bottom wall and the side wall of the recess are connected to each other. The first gap 510a extends obliquely upward from the corner, for example. In this embodiment, the first voids 510a are formed between the two first insulating portions 510 and the second insulating portion 520, so as to relieve the internal stress of the insulating filling layer 500.
With continued reference to fig. 2, the bottom of the recess 500a extends further down into the second insulating portion 520, i.e., a pit is formed in a portion of the second insulating portion 520 corresponding to between the two first insulating portions 510. Thus, the first space 510a and the recess 500a can be communicated with each other. In this embodiment, the first void 510a communicates with the recess 500a on the side wall of the recess 500a, that is, the position of the opening of the first void 510a exposed into the recess 500a is higher than the bottom position of the recess 500 a.
Wherein the opening size of the recess 500a is larger than the opening size of the first gap 510 a. And, the cover 600 fills the recess 500a and closes the opening of the first void 510a, so that the first void 510a between the first insulating part 510 and the second insulating part 520 may be maintained.
In this embodiment, the grooves extend laterally from the shielding layer 410 to the first isolation layer of the isolation sidewall 420 in the width direction. And, the depth H2 of the recess is not greater than the height H1 of the gate conductive layer 200, and the recess 500a does not extend to the bottom of the recess, so that the depth of the recess 500a is smaller. Therefore, compared with the first embodiment, the depth-to-width ratio of the recess 500a is smaller in this embodiment, and in this case, for example, no void is formed in the portion of the cover layer 600 corresponding to the recess 500 a.
Example III
The difference between the second embodiment and the second embodiment is that, in the present embodiment, the depth H2 of the groove is greater than the height H1 of the gate conductive layer, so that the groove has a larger aspect ratio, and the aspect ratio of the recess can be correspondingly increased, so that a gap is formed in a portion of the cover layer corresponding to the recess.
Fig. 3 is a schematic diagram of a semiconductor structure in a third embodiment of the present invention, as shown in fig. 3, in this embodiment, the depth of the recess extending downward in the height direction in the shielding layer 410 is lower, so that the depth H2 of the recess is greater than the height H1 of the gate conductive layer, and the recess has a larger aspect ratio.
Accordingly, the recess 500a between the two first insulating portions 510 may have a larger aspect ratio. In this way, the portion of the cover 600 that fills the recess 500a is formed with the void 600a. Similar to the embodiment, the bottom of the recess 500a may further extend into the second insulating portion 520, thereby facilitating a further increase in the aspect ratio of the recess 500 a.
That is, in the present embodiment, for the groove with a large aspect ratio, the filled insulating material may include two first insulating portions 510, second insulating portions 520 and part of the cap layer 600, and a gap 510a is formed between adjacent first insulating portions 510 and second insulating portions 520, and a gap 600a is also formed at a portion of the cap layer 600 filled in the groove, so that stress resistance of the insulating material filled in the groove may be further improved.
Example IV
The difference from the third embodiment is that in this embodiment, the recess does not extend to the second insulating portion, and the two first insulating portions are close to each other in the middle region of the groove and further form a void.
Fig. 4 is a schematic diagram of a semiconductor structure in a fourth embodiment of the present invention, as shown in fig. 4, a gap (i.e., a second gap 520 a) is also formed between the two first insulation portions 510, and the second gap 520a located between the two first insulation portions 510 extends in the height direction below the recess 500 a. That is, the top of the second void 520a communicates with the recess 500 a.
In this embodiment, a space between the first insulating part 510 and the second insulating part 520 (i.e., the first space 510 a) extends obliquely upward from the corner of the groove and communicates with the bottom of the second space 520 a.
With continued reference to fig. 4, the cover 600 fills the recess 500a and closes the top opening of the second void 520 a. That is, both the second void 520a between the two first insulating parts 510 and the first void 510a between the first insulating parts 510 and the second insulating parts 520 may be reserved for achieving stress relief of the insulating material filled in the grooves.
It should be noted that, compared with the three phases of the embodiment, the recess 500a in the present embodiment does not extend down to the second insulating portion 520, so that the recess 500a has a smaller aspect ratio, and thus no void is formed in the portion of the cover layer 600 corresponding to the recess 600 a.
In summary, in the semiconductor structure described above, the insulating filling layer filled in the groove includes at least two insulating portions, and filling the groove with a plurality of insulating portions is more advantageous in achieving stress relief of the insulating material filled in the groove than filling the groove with only one insulating material having a larger volume, so that the problem that the insulating material filled in the groove damages the adjacent semiconductor device due to high-strength internal stress can be alleviated.
Further, the insulating material filled in the grooves may be formed with voids (for example, voids are formed between adjacent insulating portions), so that stress release of each insulating portion may be further achieved by using the voids, and internal stress of the insulating material in the grooves may be more effectively relieved.
It should be noted that, in the present description, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different manner from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other.
It should be further noted that although the present invention has been disclosed in the preferred embodiments, the above embodiments are not intended to limit the present invention. Many possible variations and modifications of the disclosed technology can be made by anyone skilled in the art without departing from the scope of the technology, or the technology can be modified to be equivalent. Therefore, any simple modification, equivalent variation and modification of the above embodiments according to the technical substance of the present invention still fall within the scope of the technical solution of the present invention.
It should be further understood that the terms "first," "second," "third," and the like in this specification are used merely for distinguishing between various components, elements, steps, etc. in the specification and not for indicating a logical or sequential relationship between the various components, elements, steps, etc., unless otherwise indicated.
It should also be understood that the terminology described herein is for the purpose of describing particular embodiments only, and is not intended to limit the scope of the present invention. It must be noted that, as used herein and in the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. For example, reference to "a step" or "an apparatus" means a reference to one or more steps or apparatuses, and may include sub-steps as well as sub-apparatuses. All conjunctions used should be understood in the broadest sense. And, the word "or" should be understood as having the definition of a logical "or" rather than a logical "exclusive or" unless the context clearly indicates the contrary. Furthermore, implementation of the methods and/or apparatus in embodiments of the invention may include performing selected tasks manually, automatically, or in combination.
Claims (23)
1. A semiconductor structure, comprising:
A substrate;
a gate conductive layer on the top surface of the substrate;
a shielding layer covering the top surface of the gate conductive layer;
The side wall structure covers the side wall of the grid electrode conducting layer and the side wall of the shielding layer;
The interconnection structure comprises a contact plug and a contact pad, the contact plug is positioned on one side of the side wall structure away from the grid electrode conducting layer and extends to the substrate, and the contact pad covers the top of the contact plug;
A recess located at one side of the contact pad near the gate conductive layer, the recess extending downward into the shielding layer in the height direction and extending laterally from the shielding layer into the sidewall structure in the width direction, and
And the insulation filling layer is filled in the groove and comprises at least two insulation parts, and the at least two insulation parts are simultaneously contacted with the shielding layer and the side wall structure.
2. The semiconductor structure of claim 1, wherein the insulating fill layer comprises at least two first insulating portions covering two opposing sidewalls of the recess, the two first insulating portions defining a recess in a middle region of the recess;
and the semiconductor structure further comprises a covering layer, wherein the covering layer covers the contact pad and the insulating filling layer and fills the recess.
3. The semiconductor structure of claim 2, wherein a bottom of the recess extends to a bottom of the recess, the cap layer fills the recess and extends to a bottom of the recess, and a void is formed in a portion of the cap layer corresponding to the recess.
4. The semiconductor structure according to claim 2, wherein a second void is formed between the two first insulating portions in a middle region of the recess, the second void extending in a height direction below the recess.
5. The semiconductor structure of claim 2, wherein a width dimension of the recess is greater than a width dimension of the gate conductive layer, a depth value of the recess is not greater than a height value of the gate conductive layer, and a portion of the cap layer corresponding to the recess has no void formed therein.
6. The semiconductor structure of claim 1, wherein said semiconductor structure comprises at least two of said interconnect structures, said recess is located between adjacent ones of said contact pads, and said gate conductive layer is located between adjacent ones of said contact plugs.
7. The semiconductor structure of claim 1, wherein at least one semiconductor device is formed in the substrate, the semiconductor device comprising the gate conductive layer and first and second source/drain regions formed in the substrate, the interconnect structures being disposed on the first and second source/drain regions, respectively, and contact pads corresponding to the first and second source/drain regions extending laterally from both sides of the gate conductive layer to above the sidewall structures, respectively, in a direction toward the gate conductive layer.
8. A semiconductor structure, comprising:
A substrate;
a gate conductive layer on the top surface of the substrate;
a shielding layer covering the top surface of the gate conductive layer;
The side wall structure covers the side wall of the grid electrode conducting layer and the side wall of the shielding layer;
The at least two interconnection structures are respectively positioned at two sides of the grid electrode conductive layer, each interconnection structure comprises a contact plug and a contact pad, each contact plug is positioned at one side of the side wall structure away from the grid electrode conductive layer and extends to the substrate, and each contact pad covers the top of each contact plug;
a recess between the contact pads of the at least two interconnect structures, and
The insulation filling layer is filled in the groove, and comprises at least two first insulation parts and one second insulation part, the first insulation parts cover the side walls of the groove, the second insulation parts cover the bottoms of the groove, the two first insulation parts define a recess in the middle area of the groove, a first gap is formed between the second insulation parts and the first insulation parts, and the first gap extends from the corner where the bottom wall and the side walls of the groove are connected to each other to the direction of the recess.
9. The semiconductor structure of claim 8, further comprising a cap layer covering the contact pad and the insulating fill layer and filling the recess.
10. The semiconductor structure of claim 9, wherein a depth of the recess is greater than a height of the gate conductive layer, and a void is further formed in a portion of the cap layer corresponding to the recess.
11. The semiconductor structure of claim 8, wherein a bottom of the recess extends to the second insulating portion and communicates the first void with the recess, and wherein the cap layer fills the recess and closes an opening of the first void.
12. The semiconductor structure of claim 8, wherein a second void is formed between the two first insulating portions in a middle region of the recess, the second void extending in a height direction below the recess, the cap layer filling the recess and closing a top opening of the second void.
13. The semiconductor structure of claim 8, wherein the recess extends in a height direction from between adjacent contact pads down into the masking layer, the recess extends in a width direction laterally from the masking layer into the sidewall structure, a depth value of the recess is no greater than a height value of the gate conductive layer, and a width dimension of the recess is greater than a width dimension of the gate conductive layer.
14. The semiconductor structure of claim 13, wherein no void is formed in a portion of the cap layer corresponding to the recess.
15. The semiconductor structure of claim 8, wherein the semiconductor device comprises the gate conductive layer and first and second source/drain regions formed in the substrate, the first and second source/drain regions being located on respective sides of the gate conductive layer, the first and second source/drain regions being provided with the interconnect structure, and contact pads corresponding to the first and second source/drain regions extending laterally from respective sides of the gate conductive layer to above the sidewall structure in a direction toward the gate conductive layer.
16. A semiconductor structure, comprising:
A substrate;
A gate conductive layer on the top surface of the substrate, the gate conductive layer having a first sidewall and a corresponding second sidewall;
A shielding layer covering the top surface of the gate conductive layer, the shielding layer having a third sidewall and a corresponding fourth sidewall;
The side wall structure covers the side wall of the grid electrode conducting layer and the side wall of the shielding layer;
the at least two interconnection structures are respectively positioned at two sides of the grid electrode conductive layer, each interconnection structure comprises a contact plug and a contact pad, each contact plug is positioned at one side of the side wall structure away from the grid electrode conductive layer and extends to the substrate, the bottommost part of each contact plug is in contact with the substrate, and the contact pad covers the top part of each contact plug;
The insulating filling layer comprises a first insulating part and a second insulating part, wherein the second insulating part is positioned between the first insulating parts and completely covers the top of the shielding layer, the first insulating part is simultaneously in direct contact with the side walls of two adjacent contact pads, and the second insulating part is arranged between the shielding layer and the first insulating part.
17. The semiconductor structure of claim 16, further comprising a recess in a side of the contact pad adjacent to the gate conductive layer, the recess extending down in a height direction into the masking layer, the recess extending laterally from the masking layer into the sidewall structure in a width direction, the insulating fill layer being in the recess.
18. A semiconductor structure, comprising:
A substrate;
A gate conductive layer on the top surface of the substrate, the gate conductive layer having a first sidewall and a corresponding second sidewall;
A shielding layer covering the top surface of the gate conductive layer, the shielding layer having a third sidewall and a corresponding fourth sidewall;
The side wall structure covers the side wall of the grid electrode conducting layer and the side wall of the shielding layer;
At least two interconnection structures respectively located at two sides of the gate conductive layer, the interconnection structures including a contact plug and a contact pad, the contact plug being located at one side of the sidewall structure away from the gate conductive layer and extending to the substrate, the bottommost part of the contact plug being in contact with the substrate, the contact pad covering the top part of the contact plug, and
The insulation filling layer is positioned between the at least two interconnection structures and is used for isolating two adjacent interconnection structures;
Wherein orthographic projection of a side wall of the contact pad, which is close to the gate conductive layer, in an extending direction of the contact plug and the gate conductive layer are separated from each other and do not intersect.
19. The semiconductor structure of claim 18, further comprising a recess in a side of said contact pad adjacent said gate conductive layer, said recess extending down in a height direction into said masking layer, said recess extending laterally from said masking layer into said sidewall structure in a width direction, said insulating fill layer being located within said recess.
20. A semiconductor structure, comprising:
A substrate;
A gate conductive layer on the top surface of the substrate, the gate conductive layer having a first sidewall and a corresponding second sidewall;
A shielding layer covering the top surface of the gate conductive layer, the shielding layer having a third sidewall and a corresponding fourth sidewall;
The side wall structure covers the side wall of the grid electrode conducting layer and the side wall of the shielding layer;
At least two interconnection structures respectively located at two sides of the gate conductive layer, the interconnection structures including a contact plug and a contact pad, the contact plug being located at one side of the sidewall structure away from the gate conductive layer and extending to the substrate, the contact pad covering the top of the contact plug, and
An insulating fill layer comprising a first insulating portion having a first surface in contact with a sidewall of the contact pad, a second surface in contact with the sidewall structure, and a third surface in contact with a top of the masking layer, the first surface, the second surface, and the third surface being joined together.
21. The semiconductor structure of claim 20, further comprising a recess in a side of said contact pad adjacent said gate conductive layer, said recess extending down in a height direction into said masking layer, said recess extending laterally from said masking layer into said sidewall structure in a width direction, said insulating fill layer being located within said recess.
22. A semiconductor structure, comprising:
A substrate;
A gate conductive layer on the top surface of the substrate, the gate conductive layer having a first sidewall and a corresponding second sidewall;
A shielding layer covering the top surface of the gate conductive layer, the shielding layer having a third sidewall and a corresponding fourth sidewall;
The side wall structure covers the side wall of the grid electrode conducting layer and the side wall of the shielding layer;
At least two interconnection structures respectively located at two sides of the gate conductive layer, the interconnection structures including a contact plug and a contact pad, the contact plug being located at one side of the sidewall structure away from the gate conductive layer and extending to the substrate, the contact pad covering the top of the contact plug, and
And the insulation filling layer is positioned between the at least two interconnection structures and comprises a first insulation part and a second insulation part, wherein the second insulation part is positioned between the first insulation parts and is simultaneously in direct contact with two side walls corresponding to the side wall structures, and the second insulation part is in direct contact with the shielding layer.
23. The semiconductor structure of claim 22, further comprising a recess in a side of said contact pad adjacent said gate conductive layer, said recess extending down in a height direction into said masking layer, said recess extending laterally from said masking layer into said sidewall structure in a width direction, said insulating fill layer being located within said recess.
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