CN120261315A - Chip 3D stacking packaging method and chip 3D stacking packaging structure - Google Patents
Chip 3D stacking packaging method and chip 3D stacking packaging structure Download PDFInfo
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- CN120261315A CN120261315A CN202411988763.1A CN202411988763A CN120261315A CN 120261315 A CN120261315 A CN 120261315A CN 202411988763 A CN202411988763 A CN 202411988763A CN 120261315 A CN120261315 A CN 120261315A
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Abstract
The invention discloses a chip 3D stacking and packaging method which comprises the steps of providing a wafer, manufacturing a surface circuit and a metal covering part located at a first position on an electrode surface of the wafer far away from a substrate, wherein the surface circuit electrically connects the metal covering part with the electrode on the wafer, forming silicon holes penetrating through the substrate on the wafer on the metal covering part, thinning the substrate on the back of the wafer to enable the silicon holes to penetrate through the wafer respectively to form the first wafer, sequentially pasting and stacking a plurality of first wafers together through insulating adhesive films at intervals to form a stacking structure, enabling the silicon holes to be opposite, penetrating through insulating adhesive films opposite to the silicon holes in the stacking structure to enable a plurality of silicon holes in the stacking structure to penetrate through to form deep holes, forming a metal layer which is full of the deep holes on the surface of the deep holes, cutting the stacking structure along a cutting path to form a plurality of independent 3D stacking and packaging structures. The invention has small volume and good electric connection effect.
Description
Technical Field
The present invention relates to the field of semiconductors, and in particular, to 3D stacked packaging of chips.
Background
The advanced packaging is actively developed nowadays, but a larger part of products depend on the traditional wire bonding packaging, but if the products adapting to the traditional wire bonding packaging are to be changed into the advanced packaging process, the following situations usually occur:
1. Advanced processes such as Fan-Out (Fan Out WAFER LEVEL PACKAGE, FOWLP))/eWLB (Embedded WAFER LEVEL Ball GRID ARRAY, embedded Ball grid array)/TMV (Through Mold Via) are used, but the package size of the chip is increased to some extent.
2. Changing the Layout design of the chip (changing the Metal layer design) and changing the package substrate or frame design is costly, and Tape out (Tape out) time is long and overall cost is high.
3. Some of the chips are large, and the package form can be changed by using Fan-in (all called Fan-in Wafer-LEVEL PACKAGE, FI-WLP, technology of packaging Integrated Circuits (ICs) at a Wafer level) and changing the design of a substrate, but the chips cannot realize vertical interconnection of chip stacks.
Therefore, a chip 3D stacking and packaging method and structure capable of solving the above-mentioned problems are urgently needed.
Disclosure of Invention
The invention aims to provide a chip 3D stacking and packaging method and a chip 3D stacking and packaging structure, which have small volume and good electrical connection effect.
In order to achieve the above purpose, the invention provides a chip 3D stacking packaging method, which comprises the steps of 1, providing a wafer, manufacturing a surface circuit and a metal covering part at a first position on an electrode surface of the wafer far away from a substrate, wherein the surface circuit electrically connects the metal covering part with an electrode on the wafer, 2, forming a silicon hole penetrating through the substrate of the wafer on the metal covering part, thinning the substrate on the back of the wafer, enabling the silicon hole to penetrate through the wafer respectively to form a first wafer, 3, sequentially pasting and stacking a plurality of first wafers together through insulating adhesive films at intervals to form a stacking structure, enabling the silicon holes to be opposite, 4, penetrating through the insulating adhesive films opposite to the silicon holes in the stacking structure to enable a plurality of silicon holes in the stacking structure to penetrate through to form deep holes, 5, forming a metal layer penetrating through the substrate on the back of the wafer, enabling the silicon hole to penetrate through the wafer to form a top layer, 6, and cutting the surface of the circuit on the top of the stacking structure to form a plurality of independent deep hole D stacking structure along the stacking structure, and forming a plurality of cut lines.
Preferably, the chip 3D stacking packaging method further comprises the step of manufacturing a second wafer, wherein the wafer is provided, a silicon hole penetrating to a wafer substrate is formed at a first position of the wafer, the substrate on the back of the wafer is thinned, the silicon hole penetrates through the wafer to form the second wafer, in the step 3, a plurality of first wafers are sequentially stuck and stacked together at intervals through insulating adhesive films, meanwhile, the electrode faces of the first wafers are stuck and stacked above the topmost second wafer at intervals through the insulating adhesive films to form a stacking structure, the stacking number of the first wafers is one or more, and in the step 5, surface circuits for electrically connecting the metal layers of the deep holes and the electrodes are further manufactured on the electrode faces of the first wafers. The first half of the first wafer and the second wafer have the same steps, and can be manufactured at one time.
Preferably, the chip 3D stack packaging method further comprises the step of manufacturing a third wafer, wherein the wafer is provided, surface circuits and metal covering parts are manufactured on electrode surfaces of the wafers far away from the substrate, the metal covering parts are electrically connected with electrodes on the wafer through the surface circuits, the substrate on the back of the wafer is thinned to form the third wafer, in the step 3, the electrode surfaces of the third wafer are upwards and are adhered and stacked below the second wafer on the bottommost layer at intervals through insulating adhesive films while a plurality of first wafers are adhered and stacked together at intervals through the insulating adhesive films in sequence, so that a stacked structure is formed, and the number of the stacked first wafers is one or more. The scheme ensures that the wafer at the bottommost layer of the stacked structure has no through silicon holes, and has high structural stability.
Preferably, before the substrate on the back of the wafer is thinned when the third wafer is manufactured, laser drilling holes penetrating through the metal layer on the surface of the wafer are formed at the first position of the wafer, and in step 3, the deep holes comprise the silicon holes and the laser drilling holes on the third wafer. According to the embodiment, after the metal layer is formed in the deep hole, the electrical connection effect of the metal layer and the bottommost wafer is better.
Preferably, the metal covering part surrounds the dicing channel area, the area of the metal covering part is larger than the area of the silicon hole, the diameter of the silicon hole is larger than the width of the dicing channel, and in step 6, the metal layer on the silicon hole and the silicon hole is divided into two parts along the center line of the silicon hole to form a semi-annular metal channel positioned at the edge of the 3D stacked package structure. According to the scheme, the silicon hole is formed in the side edge of the 3D stacked packaging structure, the 3D stacked packaging structure is high in structural stability and not easy to break, and the stress stability is good, so that the stability of the 3D stacked packaging structure cannot be affected due to different materials of the metal layer and the wafer.
Specifically, forming a silicon hole penetrating through the substrate of the first wafer at the metal covering part specifically comprises cutting a first position by using laser and cutting a metal layer penetrating through the cutting channel to form a laser drilling hole, and etching the silicon hole penetrating through the substrate at the laser drilling hole by using TSV technology.
Preferably, the metal covering part is in a ring shape, a whole block shape or a block shape with a through hole. The metal covering part is a copper ring or a copper block formed by electroplating.
Preferably, in step 5, a top layer line for electrically connecting the metal layer of the deep hole and the electrode is further formed on the top surface of the stacked structure. And finally, carrying out a top layer circuit again, so that the connection stability between the metal layer and the electrode is high.
Specifically, the step 5 includes forming a metal deposition layer on the whole surface of the top surface of the stacked structure and the whole surface of the deep hole, then forming a metal layer on the metal deposition layer through an electroplating process, and forming a top layer circuit on the metal layer on the top surface of the stacked structure through a photoetching and etching process. The metal layer and the top layer circuit are firstly deposited and then electroplated, so that the cost is low. Of course, the metal layer may be directly deposited in the deep hole.
Preferably, in step 6, conductive bumps are further fabricated on the top-layer circuit for use as solder tails of the 3D stacked package structure.
Preferably, in the step 5, a metal layer is deposited on the surface of the deep hole to form a metal layer fully distributed in the deep hole, and the formed metal layer is stably connected with the wall of the deep hole.
Preferably, the insulating adhesive film is a DAF film or an NCF film, or the like.
Preferably, in the step 3, the electrode faces of the plurality of first wafers face upwards and are sequentially adhered and stacked together at intervals through insulating adhesive films.
The invention also provides a chip 3D stacking and packaging structure which is manufactured by the chip 3D stacking and packaging method.
The invention also provides a chip 3D stacked package structure, which comprises a plurality of bare chips, wherein the bare chips are relatively stacked together in sequence from bottom to top to form a stacked structure, insulating layers are arranged between adjacent bare chips at intervals, the electrode surface of each bare chip is provided with a surface circuit and a metal covering part positioned at a first position, the surface circuit electrically connects the metal covering part and the electrode on the wafer, the surface circuit at the top of the stacked structure is a top layer circuit, the stacked structure is also provided with a deep hole penetrating through the metal covering part, the deep hole penetrates through at least to the metal covering part at the top surface of the bottommost bare chip from the top surface of the stacked structure, and the wall of the deep hole is provided with a metal layer electrically connected with each metal covering part.
Preferably, a drilling hole is formed in the metal covering part of the bottommost bare die, the tail end of the deep hole is communicated to the drilling hole, and the scheme increases the electric connection area between the metal layer and the metal covering part of the bottommost bare die.
Preferably, the metal covering part extends to the side edge of the stacking structure, and the deep hole is concavely formed in the side edge of the stacking structure, so that the 3D stacking packaging structure of the chip has high structural stability.
Specifically, the cross section of the deep hole is in a notch shape. The cross section of the deep hole is semicircular or arched.
Preferably, the metal layer is fully distributed on the wall of the deep hole.
Preferably, the metal layer is an electroplated layer electroplated on the wall of the deep hole.
Preferably, the top circuit is provided with a conductive bump in a protruding manner.
Preferably, the metal covering part is located at a side surface of the stacked structure, and the deep hole is a half hole.
Compared with the prior art, the invention only needs to form conductive circuits on the surfaces of the wafers, superimpose the wafers and then form the drilled deep holes, and form metal layers on the deep holes to electrically connect a plurality of stacked wafers through the metal layers and the conductive circuits, thus the invention has the advantages of simple process, low cost, small structure volume and thin thickness, and simple process, low cost and high yield when stacking, and ensures that adjacent wafers are stuck and solidified through insulating adhesive films. In still another aspect, the silicon hole is disposed on the metal covering part, and then the metal layer is disposed in step 5, so that the metal layer is tightly connected with the metal covering part, and the electrical connection channel formed by the metal layer takes the shortest path of the whole stacked structure, so that the electrical connection performance is good.
Drawings
Fig. 1 is a flowchart of a method for 3D stacked packaging of chips in embodiment 1 of the present invention.
Fig. 2 is a flowchart of step S1 in embodiment 1 of the present invention.
Fig. 3 is a partial block diagram of a wafer after surface wiring is formed in accordance with the present invention.
Fig. 4 is a flow chart of forming a silicon hole on a wafer in embodiment 1 of the present invention.
Fig. 5 is an enlarged view of the portion a in fig. 1.
Fig. 6 is a flow chart of the fabrication of a third wafer of the present invention.
Fig. 7 is a flowchart of a method for 3D stacked packaging of chips in embodiment 2 of the present invention.
Fig. 8 is a flow chart of the fabrication of a second wafer according to the present invention.
Fig. 9 is a flowchart of a method for 3D stacked packaging of chips in embodiment 3 of the present invention.
Detailed Description
In order to describe the technical content, the constructional features, the achieved objects and effects of the present invention in detail, the following description is made in connection with the embodiments and the accompanying drawings.
Example 1:
referring to fig. 1, the invention provides a chip 3D stack packaging method, which includes steps S1 to S7.
S1, referring to fig. 1, a wafer 1 is provided, a surface line 103 and a metal cover 102 located at a first position are formed on an electrode surface of the wafer 1, which is far away from a substrate, and the surface line 103 electrically connects the metal cover 102 and the electrode 102 on the wafer 1.
Referring to fig. 2, specifically, step S1 includes steps S11 to 14.
S11, providing the wafer 1, and cleaning and preparing the wafer 1.
And S12, coating photoresist on the electrode surface of the wafer 1, and performing mask plate photoetching.
And S13, developing and Plasma processing are carried out on the wafer 1 to form a photoetching pattern.
S14, electroplating is performed on the electrode surface of the wafer 1, and then photoresist is removed and etched to fabricate the surface line 103.
Referring to fig. 3, a partial structure of the electrode surface of wafer 1 is shown.
In this embodiment, the surface circuit 103 is fabricated according to the RDL process, which is well known to those skilled in the art and will not be described in detail herein.
S2, referring to fig. 1, a silicon hole 21 penetrating to the substrate of the wafer 1 is formed in the metal cover 102.
Referring to fig. 4, step S2 specifically includes cutting the first location using a laser to form a laser drilled hole 22 and etching a silicon via 21 through to the substrate at the laser drilled hole 22 using TSV technology.
Preferably, the first position of the present invention is the scribe line 104 on the wafer 1, and in step 21, the Metal and Oxide/Nitride layers on the scribe line 104 are penetrated during laser dicing, and even the Oxide/Nitride layers are also penetrated.
S3, referring to FIG. 1, the substrate on the back side of the wafer 1 is thinned, so that the silicon holes 21 respectively penetrate through the wafer 1 to form a first wafer 1a.
S4, referring to fig. 1, a plurality of first wafers 1a are sequentially adhered and stacked together at intervals by an insulating adhesive film 30 to form a stacked structure, and the silicon holes 21 are located opposite to each other.
Specifically, an insulating adhesive film 30 is attached to the back surface of the first wafer 1a, and then a plurality of first wafers 1a are stacked in order and the insulating adhesive film 30 is cured. Wherein the insulating adhesive film 30 is a DAF film, an NCF film, or the like.
S5, referring to fig. 1, the insulating adhesive film 30 opposite to the silicon holes 21 in the stacked structure is penetrated, so that the insulating adhesive film 30 is perforated, so that a plurality of the silicon holes 21 in the stacked structure are penetrated to form deep holes 20. Wherein the size of the through hole on the insulating adhesive film 30 is the same as that of the silicon hole 21.
S6, referring to FIG. 1, a metal layer 40 is formed on the surface of the deep hole 20 and is fully distributed in the deep hole 20, and a surface line 103 on the top of the stacked structure is a top layer line.
Preferably, in step S6, a top-level circuit for electrically connecting the metal layer 40 and the electrode 102 of the deep hole 20 is further formed on the top surface of the stacked structure.
Specifically, a metal deposition layer is formed on the entire top surface of the stacked structure and the entire deep hole 20, then a metal layer 40 is formed on the metal deposition layer through an electroplating process, and a top layer line is formed on the metal layer 40 on the top surface of the stacked structure using a photolithography and etching process. Of course, the metal layer 40 may be directly deposited directly in the recess 20. Wherein the metal deposition layer may be generated by a physical deposition technique or a chemical deposition technique.
Preferably, in step S6, conductive bumps are further formed on the top-level circuit, wherein the conductive bumps are formed as solder fillets using bump formation techniques.
S7, referring to FIG. 1, the stacked structure is cut along dicing streets to form a plurality of independent 3D stacked package structures 100.
Referring to fig. 1 and 5, the metal cover 102 surrounds the dicing street 104, the area of the metal cover 102 is larger than the area of the silicon hole 21, the diameter of the silicon hole 21 is larger than the width of the dicing street 104, and in step S7, the metal cover is cut along the center line of the silicon hole 21 to divide the silicon hole 21 and the metal layer 40 on the silicon hole 21 into two halves, thereby forming a semi-annular metal channel at the edge of the 3D stacked package structure 100. According to the scheme, the silicon holes 21 are formed in the side edges of the 3D stacked package structure 100, the 3D stacked package structure 100 is high in structural stability, not prone to breakage and good in stress stability, and the stability of the 3D stacked package structure 100 cannot be affected due to the fact that materials of the metal layer 40 and the wafer 1 are different.
Example 2:
In contrast to embodiment 1, in this embodiment, the chip 3D stack package method further includes a step of fabricating a third wafer 1, referring to fig. 6, the step of fabricating the third wafer 1 includes S11, providing the wafer 1, fabricating a surface line 103 on an electrode surface of the wafer 1 away from the substrate and a metal cover 102 located at a first position, where the surface line 103 electrically connects the metal cover 102 and the electrode 102 on the wafer 1, and a specific operation manner of this step may refer to a first half portion fabricated on the first wafer 1a in embodiment 1. And S13, thinning the substrate on the back surface of the wafer 1 to form a third wafer 1c.
Specifically, the chip 3D stack packaging method comprises the steps of S1 to S7.
S1, referring to fig. 1, a wafer 1 is provided, a surface line 103 and a metal cover 102 located at a first position are formed on an electrode surface of the wafer 1, which is far away from a substrate, and the surface line 103 electrically connects the metal cover 102 and the electrode 102 on the wafer 1.
Referring to fig. 2, specifically, step S1 includes steps S11 to 14.
S11, providing the wafer 1, and cleaning and preparing the wafer 1.
And S12, coating photoresist on the electrode surface of the wafer 1, and performing mask plate photoetching.
And S13, developing and Plasma processing are carried out on the wafer 1 to form a photoetching pattern.
S14, electroplating is performed on the electrode surface of the wafer 1, and then photoresist is removed and etched to fabricate the surface line 103.
Referring to fig. 3, a partial structure of the electrode surface of wafer 1 is shown.
S2, referring to fig. 1, in the wafer 1 of the first portion, a silicon hole 21 penetrating to the substrate of the wafer 1 is formed in the metal covering portion 102.
Referring to fig. 4, step S2 specifically includes S21 using a laser to cut the first location to form a laser drilled hole 22, S22 using TSV technology to etch a silicon hole 21 through to the substrate at the laser drilled hole 22.
Preferably, the first position of the present invention is the scribe line 104 on the wafer 1, and in step 21, the Metal and Oxide/Nitride layers on the scribe line 104 are penetrated during laser dicing, and even the Oxide/Nitride layers are also penetrated.
S3, in referring to fig. 1, in the wafer 1 of the first portion, the substrate on the back side of the wafer 1 is thinned, so that the silicon holes 21 respectively penetrate through the wafer 1 to form a first wafer 1a.
In the second portion of the wafer 1, the substrate on the back side of the wafer 1 is thinned so that the silicon holes 21 respectively penetrate through the wafer 1 to form a third wafer 1c.
S4a, referring to fig. 7, one or more first wafers 1a are sequentially adhered to and stacked on the third wafer 1c at intervals by insulating adhesive films 30, thereby forming a stacked structure with the silicon holes 21 located opposite to each other.
Specifically, an insulating adhesive film 30 is attached to the back surface of the first wafer 1a, and then one or more first wafers 1a are sequentially stacked on the third wafer 1c and the insulating adhesive film 30 is cured. Wherein the insulating adhesive film 30 is a DAF film, an NCF film, or the like.
Preferably, referring to fig. 6, the step of fabricating the third wafer 1 further includes step S12a, further forming a laser drilling 22 penetrating the metal layer 40 on the surface of the wafer 1 at the first position of the wafer 1, and in step S4, the silicon hole 21 is opposite to the laser drilling 22, and the deep hole 20 includes the silicon hole 21 and the laser drilling 22 on the third wafer 1.
S5a, referring to fig. 7, the insulating adhesive film 30 opposite to the silicon holes 21 in the stacked structure is penetrated, so that the insulating adhesive film 30 is perforated, so that a plurality of the silicon holes 21 in the stacked structure are penetrated to form deep holes 20.
S6a, referring to fig. 7, a metal layer 40 is formed on the surface of the deep hole 20 and is covered with the deep hole 20, and the surface line 103 on the top of the stacked structure is a top layer line.
Preferably, in step S6a, a top-level circuit for electrically connecting the metal layer 40 and the electrode 102 of the deep hole 20 is further formed on the top surface of the stacked structure.
Specifically, a metal deposition layer is formed on the whole surface of the top surface of the stacked structure and the whole surface of the deep hole 20 by a physical deposition technique or a chemical deposition technique, then a metal layer 40 is formed on the metal deposition layer by an electroplating process, and a top layer circuit is formed on the metal layer 40 on the top surface of the stacked structure by using a photolithography and etching process. Of course, the metal layer 40 may be directly deposited directly in the recess 20.
Preferably, in step S6a, conductive bumps are further formed on the top-level circuit, wherein the conductive bumps are formed as solder fillets using bump formation techniques.
S7a, cutting the stacked structure along the cutting path to form a plurality of independent 3D stacked package structures 100a.
Referring to fig. 7 and 5, the metal cover 102 surrounds the dicing street 104, the area of the metal cover 102 is larger than the area of the silicon hole 21, the diameter of the silicon hole 21 is larger than the width of the dicing street 104, and in step S7, the metal cover is cut along the center line of the silicon hole 21 to divide the silicon hole 21 and the metal layer 40 on the silicon hole 21 into two halves, thereby forming a semi-annular metal channel at the edge of the 3D stacked package structure 100.
Referring to fig. 5, the cross section of the deep hole 20 is in a notch shape. Wherein the cross section of the deep hole 20 is semicircular or arched. The metal layer 40 is fully distributed on the wall of the deep hole 20. Wherein, the metal layer 40 is a plating layer plated on the wall of the deep hole 20.
Example 3:
In embodiment 3, unlike embodiments 1 and 2, a step of manufacturing a second wafer 1b is further included.
The step of fabricating the second wafer 1b includes:
referring to fig. 8, a wafer 1 is provided. A silicon hole 21 is formed at a first position of the wafer 1 penetrating to a substrate of the wafer 1. Specifically, steps S11 to S14a are included.
The substrate on the back side of the wafer 1 is thinned, so that the silicon hole 21 penetrates through the wafer 1 to form a second wafer 1b.
S11, providing the wafer 1, and cleaning and preparing the wafer 1.
And S12, coating photoresist on the electrode surface of the wafer 1, and performing mask plate photoetching.
And S13b, developing and Plasma processing are performed on the wafer 1 to form a photoetching pattern.
Step S13b includes S131b cutting the first location using a laser to form a laser drilled hole 22, S132b etching a silicon hole 21 through to the substrate at the laser drilled hole 22 using TSV technology.
S14b, a silicon hole 21 penetrating to the wafer substrate is formed at the first position of the wafer 1.
Specifically, the chip 3D stack packaging method comprises the steps of S1b to S4b.
S1b, providing a first wafer 1a, providing a second wafer 1b, and providing a third wafer 1c. The manufacturing methods of the first wafer 1a, the second wafer 1b, and the third wafer 1c are as described above, and will not be described in detail here.
And S2b, one or more first wafers 1a are sequentially stuck and stacked on the third wafer 1c at intervals through the insulating adhesive film 30, and a second wafer 1b is stuck and stacked on the first wafer 1a through the insulating adhesive film 30, so that a stacked structure is formed, and the positions of the silicon holes 21 are opposite.
Specifically, an insulating adhesive film 30 is attached to the back surface of the first wafer 1a, an insulating adhesive film 30 is attached to the back surface of the second wafer 1b, and then one second wafer 1b and one or more first wafers 1a are stacked in sequence on the third wafer 1c and the insulating adhesive film 30 is cured. Wherein the insulating adhesive film 30 is a DAF film, an NCF film, or the like. Of course, the third wafer 1c may not be stacked.
Preferably, referring to fig. 6, the step of fabricating the third wafer 1 further includes step S12a, further forming a laser drilling 22 penetrating the metal layer 40 on the surface of the wafer 1 at the first position of the wafer 1, and in step S4, the silicon hole 21 is opposite to the laser drilling 22, and the deep hole 20 includes the silicon hole 21 and the laser drilling 22 on the third wafer 1.
And S3b, penetrating through the insulating adhesive film 30 opposite to the silicon holes 21 in the stacked structure, so that holes are punched in the insulating adhesive film 30, and a plurality of silicon holes 21 in the stacked structure penetrate through to form deep holes 20.
And S4b, forming a metal layer 40 which is fully distributed in the deep holes 20 on the surface of the deep holes 20, wherein a surface circuit 103 at the top of the stacked structure is a top layer circuit.
Preferably, in step S4b, a top-level circuit for electrically connecting the metal layer 40 and the electrode 102 of the deep hole 20 is further formed on the top surface of the stacked structure.
Specifically, a metal deposition layer is formed on the whole surface of the top surface of the stacked structure and the whole surface of the deep hole 20 by a physical deposition technique or a chemical deposition technique, then a metal layer 40 is formed on the metal deposition layer by an electroplating process, and a top layer circuit is formed on the metal layer 40 on the top surface of the stacked structure by using a photolithography and etching process. Of course, the metal layer 40 may be directly deposited directly in the recess 20.
Preferably, in step S4b, conductive bumps are further formed on the top-level circuit, wherein the conductive bumps are formed as solder fillets using bump formation techniques.
S5b, cutting the stacked structure along the cutting path to form a plurality of independent 3D stacked package structures 100b.
Referring to fig. 7 and 5, the metal cover 102 surrounds the dicing street 104, the area of the metal cover 102 is larger than the area of the silicon hole 21, the diameter of the silicon hole 21 is larger than the width of the dicing street 104, and in step S7, the metal cover is cut along the center line of the silicon hole 21 to divide the silicon hole 21 and the metal layer 40 on the silicon hole 21 into two halves, thereby forming a semi-annular metal channel at the edge of the 3D stacked package structure 100.
Referring to fig. 5, the cross section of the deep hole 20 is in a notch shape. Wherein the cross section of the deep hole 20 is semicircular or arched. The metal layer 40 is fully distributed on the wall of the deep hole 20. Wherein, the metal layer 40 is a plating layer plated on the wall of the deep hole 20.
Referring to fig. 1, 5, 7 and 9, the chip 3D stacked package structure 100 formed by the package of the present invention includes a plurality of die, the die are stacked in turn from bottom to top to form a stacked structure, an insulating layer is disposed between adjacent die at intervals, an electrode surface of each die has a surface line 103 and a metal covering portion 102 located at a first position, the surface line 103 electrically connects the metal covering portion 102 and the electrode 102 on the wafer 1, the surface line 103 on the top of the stacked structure is a top line, the stacked structure is further provided with a deep hole 20 penetrating through the metal covering portion 102, the deep hole 20 penetrates from the top surface of the stacked structure at least to the metal covering portion 102 on the top surface of the die at the lowest layer, and a metal layer 40 electrically connected with each metal covering portion 102 is disposed on the wall of the deep hole 20.
Preferably, a drill hole is formed in the metal covering portion 102 of the bottommost die, and the end of the deep hole 20 is connected to the drill hole, which increases the electrical connection area between the metal layer 40 and the metal covering portion 102 of the bottommost die. Wherein the drilling is laser drilling.
Preferably, the metal covering portion 102 extends to a side of the stacked structure, and the deep hole 20 is concavely formed on the side of the stacked structure, so that the 3D stacked chip package structure 100 has high structural stability.
Referring to fig. 5, the cross section of the deep hole 20 is in a notch shape. Wherein the cross section of the deep hole 20 is semicircular or arched. The metal layer 40 is fully distributed on the wall of the deep hole 20. Wherein, the metal layer 40 is a plating layer plated on the wall of the deep hole 20.
Preferably, the top circuit is provided with a conductive bump.
The deep hole 20 may penetrate through the entire 3D stacked package structure 100 of the chip, may penetrate through only the surface of the bottommost die, or may penetrate through the surface of the bottommost die to drill holes.
In the above embodiment, the surface wiring is copper wiring, aluminum wiring, or the like. The metal layer 40 is a metal such as Ti/Cu/Ta/TaN.
The foregoing description of the preferred embodiments of the present invention is not intended to limit the scope of the claims, which follow, as defined in the claims.
Claims (21)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN202411988763.1A CN120261315A (en) | 2024-12-31 | 2024-12-31 | Chip 3D stacking packaging method and chip 3D stacking packaging structure |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202411988763.1A CN120261315A (en) | 2024-12-31 | 2024-12-31 | Chip 3D stacking packaging method and chip 3D stacking packaging structure |
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