CN120261417A

CN120261417A - Electronic devices, substrates, and electronic devices

Info

Publication number: CN120261417A
Application number: CN202410016370.8A
Authority: CN
Inventors: 刘筱逸; 冀伟田; 李小秋; 梁腾和
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2024-01-03
Filing date: 2024-01-03
Publication date: 2025-07-04

Abstract

The embodiment of the application provides an electronic device, a substrate and electronic equipment, and relates to the technical field of semiconductors. The electronic device comprises a substrate, a first chip, a second chip, a heat conducting medium, a heat radiating plate and a heat conducting wall, wherein the first chip and the second chip are arranged in a stacked mode. The substrate comprises a heat transfer structure, the first chip is close to the substrate relative to the second chip, and orthographic projection of the first chip on the substrate overlaps with the heat transfer structure. The heat conducting medium is positioned on one side of the second chip far away from the first chip and is connected with the second chip. The heat dissipation plate is positioned on one side of the heat conduction medium far away from the second chip and is connected with the heat conduction medium. The heat conducting wall is positioned between the heat conducting medium and the substrate and connects the heat conducting medium and the substrate. In the embodiment of the application, the heat emitted by the first chip can be conducted to the heat dissipation plate through the heat transfer structure, the heat conduction wall and the heat conduction medium, so that the heat transfer path between the first chip and the heat dissipation plate is increased, the heat dissipation capacity of the first chip is improved, and the performance of the first chip is improved.

Description

Electronic device, substrate, and electronic apparatus

Technical Field

Embodiments of the present application relate to the field of semiconductor technologies, and in particular, to an electronic device, a substrate, and an electronic apparatus.

Background

The electronic device comprises a substrate, a first chip and a second chip which are stacked, and a heat dissipation plate. The first chip is close to the substrate relative to the second chip, and the heat dissipation plate is positioned on one side of the second chip away from the first chip.

In the related art, heat emitted by the first chip needs to be conducted to the heat dissipation plate through the second chip, so that the second chip affects heat dissipation of the first chip, and therefore heat dissipation of the first chip is difficult, and performance of the first chip is affected.

Disclosure of Invention

The embodiment of the application provides an electronic device, a substrate and electronic equipment, which are used for improving the heat dissipation capacity of a first chip and increasing the heat dissipation capacity of the first chip, so that the performance of the first chip is improved.

In one aspect, an embodiment of the present application provides an electronic device. The electronic device comprises a substrate, a first chip, a second chip, a heat conducting medium, a heat radiating plate and a heat conducting wall, wherein the first chip and the second chip are arranged in a stacked mode. The substrate includes a heat transfer structure. The first chip is close to the substrate relative to the second chip, and orthographic projection of the first chip on the substrate overlaps with the heat transfer structure. The heat conducting medium is positioned on one side of the second chip far away from the first chip and is connected with the second chip. The heat dissipation plate is positioned on one side of the heat conduction medium far away from the second chip and is connected with the heat conduction medium. The heat conducting wall is positioned between the heat conducting medium and the substrate and connects the heat conducting medium and the substrate.

In the embodiment of the application, the heat emitted by the first chip can be conducted to the heat transfer structure and is conducted to the heat conducting wall through the heat transfer structure, and the heat conducting wall can conduct the heat to the heat dissipation plate through the heat conducting medium. That is, the heat emitted from the first chip can be firstly conducted downward (in a direction close to the substrate) to the heat transfer structure, and then conducted upward (in a direction away from the substrate) to the heat dissipation plate. Therefore, the heat emitted by the first chip is not required to be conducted to the heat dissipation plate through the second chip, a heat transfer path between the first chip and the heat dissipation plate is increased, the influence of the second chip on heat dissipation of the first chip is reduced, the heat dissipation capacity of the first chip is improved, the heat dissipation capacity of the first chip is increased, the risk that the first chip cannot work normally due to overhigh temperature is reduced, and the performance of the first chip is improved.

In addition, through setting up heat transfer structure and heat conduction wall, reduced the heat that first chip conduction was kept away from first chip one side to the base plate, reduced the influence that the base plate led to the fact to first chip heat dissipation, improved the heat dispersion of first chip, increased the heat dissipation of first chip, reduced the too high risk that leads to first chip unable normal work of temperature, improved the performance of first chip.

It can be understood that the heat emitted by the first chip and the second chip can be also transversely (parallel to the direction of the substrate) conducted to the heat conducting wall, and the heat conducting wall conducts the heat to the heat radiating plate through the heat conducting medium, so that the heat transfer path between the second chip of the first chip and the heat radiating plate is increased, the heat radiating capacity of the first chip and the second chip is improved, the heat radiating capacity of the first chip and the second chip is increased, the risk that the first chip and the second chip cannot work normally due to overhigh temperature is reduced, and the performance of the first chip and the second chip is improved.

In some possible implementations, the orthographic projection of the first chip on the substrate is within the range of the heat transfer structure. The arrangement is such that heat emitted by the first chip is conducted to the heat transfer structure and rapidly spread over the heat transfer structure. The heat transfer structure can conduct heat to the heat conducting wall, and the heat conducting wall can conduct heat to the heat radiating plate through the heat conducting medium, so that the heat radiating capacity of the first chip is improved, the heat radiating capacity of the first chip is increased, and the performance of the first chip is improved.

In some possible implementations, the substrate includes a plurality of conductive layers and a plurality of insulating layers alternately stacked, the plurality of conductive layers including a heat transfer conductive layer, the heat transfer conductive layer including a heat transfer structure. The substrate further comprises a solder mask layer, and the solder mask layer covers a conductive layer. The solder mask layer is provided with a window, and the window penetrates through the solder mask layer along the thickness direction of the solder mask layer to expose the conductive layer covered by the solder mask layer. The heat conductive wall includes a body portion and a filler portion connected to each other. The body portion is located between the substrate and the heat transfer medium. The filling part is filled in the open window and is connected with the heat transfer structure. By the arrangement, the influence of the solder mask layer on connection between the heat conducting wall (the filling part) and the heat transfer structure can be reduced, the thermal resistance between the heat conducting wall and the heat transfer structure is reduced, the heat dissipation capacity of the first chip is improved, and the heat dissipation capacity of the first chip is increased.

In some possible implementations, the solder mask covers the heat transfer conductive layer, the fenestration exposes the heat transfer structure, and the filler is connected to the heat transfer structure, or the conductive layer includes a conductive connection layer that covers the conductive connection layer and is connected to the heat transfer structure. The conductive connecting layer is exposed out of the window, and the filling part is connected with the conductive connecting layer. So set up, can improve the convenience and the flexibility of being connected between filling portion and the heat transfer structure, satisfy different demands.

In some possible implementations, the heat conductive wall further includes a connection portion connecting the main body portion and the filling portion. By the arrangement, the convenience of connection between the main body part and the filling part can be improved.

In some possible implementations, the material of the body portion includes a metal, an alloy, or silicon, the material of the filler portion includes a metal, an alloy, or silicon, and the material of the connection portion includes a metal or an alloy. By the arrangement, the thermal resistance of the heat conducting wall can be reduced, the heat dissipation capacity of the chip assembly (including the first chip and the second chip which are arranged in a laminated mode) is improved, the heat dissipation capacity of the chip assembly is increased, and the flexibility of the heat conducting wall in material selection can be improved.

In some possible implementations, the material of the body portion includes copper, the material of the filler portion includes copper, and the material of the connection portion includes solder or nickel-gold. By the arrangement, the thermal resistance of the heat conducting wall can be reduced, the heat dissipation capacity of the chip assembly (including the first chip and the second chip which are arranged in a laminated mode) is improved, and the heat dissipation capacity of the chip assembly is increased.

In some possible implementations, the electronic device further includes a shield case that houses the first chip and the second chip that are stacked. The shielding cover comprises a cover plate and a side wall, and the cover plate is connected with the side wall. The cover plate is located one side of the second chip far away from the first chip, and the heat dissipation plate is located one side of the cover plate far away from the second chip. The side wall is disposed adjacent to the thermally conductive wall. The shielding cover is arranged to cover the first chip and the second chip (namely the chip assembly) which are arranged in a stacked mode, so that radio frequency interference of other radio frequency devices on the substrate, caused by the first chip and the second chip, can be reduced, and the radio frequency interference of the first chip and the second chip, caused by other radio frequency devices on the brush substrate, can be reduced. The heat dissipation plate is arranged on one side, far away from the substrate, of the cover plate, the heat dissipation plate can play a role in uniform temperature heat exchange on the chip assembly (including the first chip and the second chip which are arranged in a laminated mode), the heat dissipation plate can be arranged outside the shielding cover, and the influence of the shielding cover on heat dissipation of the heat dissipation plate is reduced.

In some possible implementations, the shield can houses the first chip, the second chip, and the thermally conductive wall. Wherein the heat conducting medium comprises a cover plate. So set up for the heat conduction wall can be through apron with heat conduction to the heating panel. And compared with the heat conduction wall arranged outside the shielding case, the shielding case can protect the heat conduction wall, and the risk of damaging the heat conduction wall is reduced.

In some possible implementations, a thermal interface material is filled between the cover plate and an end of the thermally conductive wall remote from the base plate. Wherein the thermally conductive medium comprises a thermal interface material between the thermally conductive wall and the cover plate. So set up, can reduce the thermal resistance between heat conduction wall and the heating panel, improve the heat dispersion of chip assembly (including the first chip and the second chip of range upon range of setting), increase the heat dissipation capacity of chip assembly to improve the performance of chip assembly.

In some possible implementations, a thermal interface material is filled between the first and second chips and the thermally conductive wall in a stacked arrangement. So set up, can reduce the thermal resistance between chip subassembly (including the first chip and the second chip of range upon range of setting) and the heat conduction wall, the thermal resistance that reduces the heat when transversely (being on a parallel with the direction of base plate) conduction promptly for the heat that the chip subassembly was given off can be conducted to the heat conduction wall rapidly, and conduct to the heating panel through heat conduction wall and heat conduction medium, improve the heat dispersion of chip subassembly, increase the heat dissipation capacity of chip subassembly, thereby improve the performance of chip subassembly.

In some possible implementations, the thermally conductive wall is located outside the shield. By the arrangement, compared with the arrangement of the shielding cover and the chip assembly (including the first chip and the second chip which are arranged in a stacked mode) and the heat conducting wall, electromagnetic interference caused by the heat conducting wall to the chip assembly can be reduced.

In some possible implementations, a thermal interface material is filled between the end of the heat conducting wall away from the substrate and the heat dissipating plate. Wherein the heat conducting medium comprises a thermal interface material between the heat conducting wall and the heat dissipating plate. So set up, after the heat conduction that the chip subassembly (including the first chip and the second chip of range upon range of setting) given off to the heat conduction wall, can be via thermal interface material conduction to the heating panel, reduced the thermal resistance between heat conduction wall and the heating panel, improve the heat dispersion of chip subassembly, increase the heat dissipation capacity of chip subassembly to improve the performance of chip subassembly.

In some possible implementations, a thermal interface material is filled between the side wall and the thermally conductive wall. So set up, can reduce the thermal resistance between lateral wall and the heat conduction wall, that is, reduce the thermal resistance of heat when horizontal (the direction that is on a parallel with the base plate) conduction for the heat of chip subassembly (including the first chip and the second chip of range upon range of setting) conduction to the lateral wall can conduct to the heat conduction wall rapidly, and conduct to the heating panel through heat conduction wall and heat conduction medium, improve the heat dispersion of chip subassembly, increase the heat dissipation capacity of chip subassembly, thereby improve the performance of chip subassembly.

In some possible implementations, a thermal interface material is filled between a side of the second chip remote from the first chip and the cover plate. So set up, can reduce the thermal resistance between second chip and the apron, improve the heat dispersion of chip assembly (including the first chip and the second chip of range upon range of setting), increase the heat dissipation capacity of chip assembly, reduced the too high risk that leads to the unable normal work of chip assembly of temperature, improved the performance of chip assembly.

In some possible implementations, a thermal interface material is filled between the cover plate and the heat dissipation plate. So set up, can reduce the thermal resistance between apron and the heating panel, improve the heat dispersion of chip assembly (including the first chip and the second chip of range upon range of setting), increase the heat dissipation capacity of chip assembly, reduced the too high risk that leads to the unable normal work of chip assembly of temperature, improved the performance of chip assembly.

In some possible implementations, the thermally conductive wall is annular, and the thermally conductive wall surrounds the first and second chips that are stacked. So set up for the heat conduction wall can be with the heat conduction to the heating panel that the different positions of chip assembly (including the first chip and the second chip of range upon range of setting give off, improves the heat dispersion of chip assembly, increases the chip assembly heat dissipation capacity.

In some possible implementations, the thermally conductive wall is cylindrical. By the arrangement, the structure of the heat conducting wall can be simplified, and miniaturization of the electronic device is facilitated.

In some possible implementations, the number of thermally conductive walls is a plurality, the plurality of thermally conductive walls surrounding the first and second chips in a stacked arrangement. So set up for the heat conduction wall can be with the heat conduction to the heating panel that the different positions of chip assembly (including the first chip and the second chip of range upon range of setting give off, improves the heat dispersion of chip assembly, increases the chip assembly heat dissipation capacity.

In some possible implementations, the heat spreader plate is a vacuum vapor chamber. By the arrangement, the heat dissipation plate can play a role in carrying out uniform temperature heat dissipation on the chip assembly (including the first chip and the second chip which are stacked).

In another aspect, embodiments of the present application provide a substrate. The substrate includes a plurality of conductive layers and a plurality of insulating layers alternately stacked. The multi-layer conductive layer includes a heat transfer conductive layer including a heat transfer structure.

It will be appreciated that the substrate is used to electrically connect with the chip assembly (including the first chip and the second chip in a stacked arrangement). The multi-layer conductive layer comprises a heat transfer conductive layer, the heat transfer conductive layer comprises a heat transfer structure, and heat emitted by the first chip can be conducted to the heat transfer structure and rapidly spread on the heat transfer structure. The heat transfer structure can conduct heat to the heat conducting wall, and the heat conducting wall can conduct heat to the heat radiating plate through the heat conducting medium, so that the heat radiating capacity of the first chip is improved, the heat radiating capacity of the first chip is increased, and the performance of the first chip is improved.

In yet another aspect, an embodiment of the present application provides an electronic device. The electronic equipment comprises a shell and the electronic device, wherein the electronic device is positioned in an accommodating space enclosed by the shell.

The electronic device provided by the embodiment of the application comprises the electronic device, so that the electronic device has all the beneficial effects and is not described herein.

Drawings

Fig. 1 is a schematic structural diagram of an electronic device according to some embodiments of the present application;

FIG. 2 is an exploded view of an electronic device according to some embodiments of the present application;

Fig. 3 is a schematic structural diagram of an electronic device according to some embodiments of the present application;

FIG. 4 is a schematic cross-sectional view of FIG. 3 along the direction A-A according to some embodiments of the present application;

FIG. 5 is a schematic cross-sectional view of FIG. 3 along the direction A-A according to other embodiments of the present application;

FIG. 6 is a schematic cross-sectional view of FIG. 3 along the direction A-A according to still other embodiments of the present application;

FIG. 7 is a schematic cross-sectional view of FIG. 3 along the direction A-A according to still other embodiments of the present application;

FIG. 8 is a schematic cross-sectional view of FIG. 3 along the direction A-A according to still other embodiments of the present application;

FIG. 9 is a schematic cross-sectional view of FIG. 3 along the direction A-A according to still other embodiments of the present application;

FIG. 10 is a top view of an electronic device according to some embodiments of the present application;

FIG. 11 is a top view of an electronic device according to other embodiments of the present application;

FIG. 12 is a top view of an electronic device according to still other embodiments of the present application;

Fig. 13 is a top view of an electronic device according to still other embodiments of the present application.

Detailed Description

The following description of the embodiments of the present disclosure will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all, of the embodiments of the present disclosure. All other embodiments obtained by one of ordinary skill in the art based on the embodiments provided by the present disclosure are within the scope of the present disclosure.

Throughout the specification and claims, the term "comprising" is to be interpreted as an open, inclusive meaning, i.e. "comprising, but not limited to, unless the context requires otherwise. In the description of the present specification, the terms "one embodiment," "some embodiments," "example embodiments," "examples," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with the embodiment or example is included in at least one embodiment or example of the present disclosure. The schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics may be combined in any suitable manner in any one or more embodiments or examples.

The terms "first" and "second" are used below for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the embodiments of the present disclosure, unless otherwise indicated, the meaning of "a plurality" is two or more.

At least one of "A, B and C" has the same meaning as at least one of "A, B or C" and each includes a combination of A, B and C of a alone, B alone, C alone, a combination of a and B, a combination of a and C, a combination of B and C, and a combination of A, B and C.

"A and/or B" includes three combinations of A only, B only, and a combination of A and B.

As used herein, "parallel", "perpendicular", "equal" includes the stated case as well as the case that approximates the stated case, the range of which is within an acceptable deviation range as determined by one of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., limitations of the measurement system). For example, "parallel" includes absolute parallel and approximately parallel, where the range of acceptable deviation of approximately parallel may be, for example, within 5 ° of deviation, and "perpendicular" includes absolute perpendicular and approximately perpendicular, where the range of acceptable deviation of approximately perpendicular may also be, for example, within 5 ° of deviation. "equal" includes absolute equal and approximately equal, where the difference between the two, which may be equal, for example, is less than or equal to 5% of either of them within an acceptable deviation of approximately equal.

Fig. 1 is a schematic structural diagram of an electronic device according to some embodiments of the present application. Fig. 2 is an exploded view of an electronic device according to some embodiments of the present application. Fig. 3 is a schematic structural diagram of an electronic device according to some embodiments of the present application. FIG. 4 is a schematic cross-sectional view of FIG. 3 along the direction A-A according to some embodiments of the present application. It will be appreciated that fig. 1 and 2 only show a portion of the components included in the electronic device 300, and the actual shape, actual size, actual position, actual configuration, etc. of these components are not limited by fig. 1 and 2.

As shown in fig. 1 and 2, an embodiment of the present application provides an electronic device 300. The electronic device 300 may be a mobile phone, a tablet computer (tablet personal computer), a laptop computer (english: laptop computer), a personal digital assistant (english: personal DIGITAL ASSISTANT, abbreviated to PDA), a camera, a personal computer, a notebook computer, a smart watch, a vehicle-mounted device, a wearable device, augmented reality (english: augmented reality, abbreviated to AR) glasses, AR helmets, virtual Reality (VR) glasses, VR helmets, servers, switches, bridges (also called bridges), repeaters, routers, or gateways (also called protocol converters), and the like. It will be appreciated that embodiments of the present application are not particularly limited to the particular form of electronic device 300.

In some examples, electronic device 300 includes a housing 301. Taking the electronic device 300 as a mobile phone, as shown in fig. 2, the housing 301 may include a front frame 301a, a middle frame 301b, and a rear case 301c. The middle frame 301b includes a border 301b1 and a middle plate 301b2. The frame 301b1 is an annular structure, the front frame 301a is connected to one side edge of the frame 301b1, the rear case 301c is connected to one side edge of the frame 301b1 away from the front frame 301a, and the front frame 301a, the frame 301b1, and the rear case 301c can define an accommodation space.

For example, the front frame 301a and the rear case 301c may be connected to the frame 301b1 by means of a snap-fit or adhesive connection, respectively. The front frame 301a and the rear case 301c may be connected to the frame 301b1 in the same manner or may be connected to each other in different manners.

The middle plate 301b2 is a flat plate structure, and it is understood that the middle plate 301b2 serves as a skeleton of the electronic device 300 and plays a supporting role. The middle plate 301b2 is located in the accommodating space surrounded by the front frame 301a, the frame 301b1 and the rear case 301c, and is connected to the frame 301b 1. Illustratively, the bezel 301b1 can enclose the board 301b2. The middle plate 301b2 may be connected to the frame 301b1 by welding, bonding, or the like. Or the middle plate 301b2 and the frame 301b1 may be integrally formed, so as to improve the connection reliability between the two.

Taking the electronic device 300 as a mobile phone, as shown in fig. 2, the electronic device 300 may further include a display panel 302 and a camera component 303.

It will be appreciated that the display panel 302 is used to display image information. The display panel 302 may be used to display still images, such as pictures or photographs, or the display panel 302 may be used to display moving images, such as video or game visuals. The display panel 302 may be an organic light-emitting diode (OLED) display panel, a Liquid crystal display panel (Liquid CRYSTAL DISPLAY, LCD), or the like. Or the display panel 302 may be other types of display panels.

The front frame 301a may be provided with a first through hole (not shown in the drawing) penetrating the front frame 301a in the thickness direction of the front frame 301a. The display panel 302 is located in the accommodating space between the middle plate 301b2 and the front frame 301a, and is embedded in the first through hole to be connected with the front frame 301a, so that the front frame 301a is prevented from shielding image information displayed by the display panel 302.

It will be appreciated that the camera assembly 303 is capable of performing image acquisition functions. The electronic device 300 may include one or more camera assemblies 303. As shown in fig. 2, the rear case 301c is provided with a second through hole 301c1, and the second through hole 301c1 penetrates the rear case 301c in the thickness direction of the rear case 301c. The camera module 303 is located in the accommodating space between the middle plate 301b2 and the rear housing 301c, and is embedded in the second through hole 301c1 to be connected with the rear housing 301c, so that the rear housing 301c is prevented from shielding the camera module 303.

When the number of the camera modules 303 is plural, the number of the second through holes 301c1 may be one, and the plural camera modules 303 are embedded in one second through hole 301c 1. Alternatively, the number of the second through holes 301c1 may be plural, and at least one camera module 303 is embedded in one second through hole 301c 1.

In some examples, as shown in fig. 2, the electronic apparatus 300 further includes an electronic device 200, where the electronic device 200 is located in an accommodating space enclosed by the housing 301.

For example, the electronic device 200 may be located in the accommodation space between the middle plate 301b2 and the rear case 301c, or the electronic device 200 may be located in the accommodation space between the middle plate 301b2 and the front frame 301 a. Embodiments of the present application do not further limit the location of the electronic device 200 within the housing 301.

It can be appreciated that the electronic device 200 is disposed in the accommodating space enclosed by the housing 301, so that the housing 301 can function to protect the electronic device 200 and reduce the risk of damaging the electronic device 200.

In some examples, as shown in fig. 3 and 4, the electronic device 200 includes a substrate 210, a package structure 100, and a plurality of chips 221. Illustratively, at least two chips 221 are stacked to form a chip assembly 220, and the package structure 100 is capable of packaging the chip assembly 220 to function as a protection for the chip assembly 220. The chip assembly 220 may be electrically connected with the substrate 210.

It will be appreciated that only the package structure 100 is shown in fig. 3, the chip assembly 220 enclosed by the package structure 100, etc. are not shown. For clarity of illustration, fig. 3 shows only one package structure 100, and the number of package structures 100 included in the electronic device 200 is not further limited in the embodiment of the present application.

By way of example, the substrate 210 may be a printed circuit board (english: printed circuit board; english: PCB) or a package substrate, etc. When the substrate 210 is a printed circuit board, the substrate 210 may be a motherboard of the electronic device 300. It is understood that embodiments of the present application are not further limited to the specific form of the substrate 210.

In some examples, as shown in fig. 4, the substrate 210 includes a plurality of conductive layers 211 and a plurality of insulating layers 212 alternately stacked.

Illustratively, the material of the conductive layer 211 is metal to improve the conductive properties of the conductive layer 211. For example, the material of the conductive layer 211 may be copper, aluminum, gold, silver, or the like. Conductive layer 211 may have conductive traces disposed thereon to which chip assembly 220 is electrically connected.

The insulating layer 212 is located between two adjacent conductive layers 211 to function as an electrical isolation. The material of the insulating layer 212 may be a fiberglass epoxy material. Or the insulating layer 212 may be other insulating materials. The materials of the conductive layer 211 and the insulating layer 212 are not further limited in the embodiments of the present application.

In some examples, as shown in fig. 4, the substrate 210 further includes a solder mask 214, the solder mask 214 covering the conductive layer 211. For example, the solder resist 214 covers the exposed one conductive layer 211 after the plurality of conductive layers 211 and the plurality of insulating layers 212 are alternately stacked. The solder mask 214 may be solder mask ink and serves as an electrical isolation.

For example, before the chip assembly 220 is electrically connected to the conductive trace, a pad window may be opened on the solder mask layer 214, and the pad window penetrates the solder mask layer 214 in a thickness direction of the solder mask layer 214 to expose the pad, which is electrically connected to the conductive trace. The chip assembly 220 is soldered to the pads so that the chip assembly 220 can be electrically connected to the conductive traces of the substrate 210.

By way of example, the electronic device 200 may include one, two, or more chip assemblies 220. When the number of the chip assemblies 220 is plural, the plural chip assemblies 220 may be disposed on the substrate 210 at intervals and electrically connected with the substrate 210, respectively. The chip assembly 220 may include two, three, or more chips 221 in a stacked arrangement. When the number of the chip assemblies 220 is plural, the number of the chips 221 in different chip assemblies 220 may be the same or different.

It will be appreciated that, in order to clearly illustrate the structure of the drawings, only two chips 221 are illustrated in fig. 4, and the number of chips 221 included in the chip assembly 220 in the embodiment of the present application is not further limited. The embodiment of the present application takes the chip assembly 220 including the first chip 2211 and the second chip 2212 stacked together as an example, and the description will be continued. That is, the electronic device 200 includes a first chip 2211 and a second chip 2212 stacked.

In some examples, as shown in fig. 4, the first chip 2211 is close to the substrate 210 relative to the second chip 2212. In an example, the first chip 2211 is electrically connected to the substrate 210, and the second chip 2212 is electrically connected to the first chip 2211. Or the second chip 2212 may be electrically connected to the substrate 210. Embodiments of the present application are not further limited in this regard.

For example, the electronic device 200 may also include other chips (chips other than the first chip 2211 and the second chip 2212), such as a third chip 2213. The third chip 2213 is disposed at a distance from the chip assembly 220, and the third chip 2213 is electrically connected to the substrate 210. That is, at least two chips 221 stacked in the chip assembly 220 may be a part of the chips 221 of the plurality of chips 221 included in the electronic device 200. The number of chips 221 included in the electronic device 200 is not further limited in the embodiments of the present application.

The types of the first chip 2211 and the second chip 2212 may be the same or different. For example, the first chip 2211 may be a System On Chip (SOC), and the second chip 2212 may be a double rate synchronous dynamic random access memory (doubledata rate synchronous dynamic random access memory, DDR SDRAM). Or the first chip 2211 and the second chip 2212 may be other chips, such as a central processing unit (english: central processing unit, english: CPU), an image processor (english: graphics processing unit, english: GPU), or a low-power-consumption double-rate synchronous dynamic random access memory.

The third chip 2213 may be a power line chip or a general flash memory storage (english: universal Flash Storage, english: USF) chip, etc. It is understood that the embodiments of the present application do not further limit the kinds of the first chip 2211, the second chip 2212 and the third chip 2213.

As shown in fig. 4, the chip 221 (e.g., the first chip 2211 and the second chip 2212) includes a chip body 221a and a package 221b. The chip body 221a may be a bare chip (english: singledie), and the package portion 221b wraps the chip body 221a to protect the chip body 221 a. The encapsulation part 221b may include an encapsulation Substrate (SUB) 221b1, a molding compound (molding) 221b2, and solder balls 221b3.

The chip body 221a is located on the package substrate 221b1 and electrically connected to the package substrate 221b1, and the molding compound 221b2 encapsulates the chip body 221a. The solder ball 221b3 is located on a side of the package substrate 221b1 away from the chip body 221a, and is electrically connected to the package substrate 221b 1. The solder balls 221b3 are used for soldering with other components or chips. Thus, the chip body 221a can be electrically connected to other components through the solder balls 221b 3.

For example, the solder balls 221b3 of the first chip 2211 may be soldered with the substrate 210 so that the first chip 2211 can be electrically connected with the substrate 210. The first chip 2211 may include a bonding portion, and the solder ball 221b3 of the second chip 2212 may be bonded to the bonding portion of the first chip 2211 so that the second chip 2212 can be electrically connected to the first chip 2211.

For example, the number of the solder balls 221b3 may be plural and arranged in an array to form a solder ball array (english: ball GRID ARRAY, english: BGA).

The package structure 100 encapsulates the chip assembly 220 to function as a protection for the chip assembly 220. By way of example, the package structure 100 may package the chip assembly 220 and a plurality of other chips (e.g., the third chip 2213) disposed on the substrate 210 at intervals. In some examples, the process of packaging at least two chips 221 arranged in layers may be referred to as package on layers (english: package on package, english: POP).

In some examples, as shown in fig. 4, the package structure 100 includes a shield 130, i.e., the electronic device 200 includes the shield 130. Illustratively, the shield 130 and the die 221 are located on the same side of the substrate 210. The shield case 130 houses the first chip 2211 and the second chip 2212 (the chip assembly 220) stacked. For example, the shield can 130 can also house a third chip 2213.

The shield 130 can function as electromagnetic shielding. For example, the shield can 130 can block electromagnetic fields generated by the first chip 2211 and the second chip 2212 from propagating outside the shield can 130, and the shield can 130 can block electromagnetic fields of other radio frequency devices on the substrate 210 from entering the shield can 130 to interfere with the first chip 2211 and the second chip 2212.

That is, the first chip 2211 and the second chip 2212 stacked and disposed by the shielding case 130 are disposed, so that radio frequency interference of other radio frequency devices on the substrate 210 by the first chip 2211 and the second chip 2212 can be reduced, and radio frequency interference of other radio frequency devices on the substrate 210 by the first chip 2211 and the second chip 2212 can be reduced.

In some examples, as shown in fig. 4, the shield 130 includes a cover 130a and a sidewall 130b, the cover 130a being connected to the sidewall 130 b. The cover plate 130a is located at a side of the second chip 2212 away from the first chip 2211, and the side wall 130b encloses the first chip 2211 and the second chip 2212 which are stacked.

The shield can 130 includes a cover plate 130a and sidewalls 130b such that the shield can 130 can house the chip assembly 220. In some examples, the sidewall 130b and the cover plate 130a may be integrally formed to improve connection reliability therebetween. For example, as shown in fig. 4, a gap may be provided between the side wall 130b and the chip assembly 220 (the first chip 2211 and the second chip 2212 that are stacked).

By way of example, the material of the shield 130 may be a metal, such as copper foil, stainless steel, etc., to function as a shield for electron radiation. In some examples, the shield 130 may be formed by stamping. It will be appreciated that the material of the shielding case 130, the processing technique, and the like are not further limited by the embodiments of the present application.

In some examples, as shown in fig. 4, the package structure 100 further includes a heat dissipation plate 110, i.e., the electronic device 200 further includes the heat dissipation plate 110. The heat dissipation plate 110 is located at a side of the cover plate 130a away from the second chip 2212. By way of example, the heat dissipating plate 110 may be a vacuum vapor chamber (hereinafter referred to as VC).

Illustratively, the heat dissipation plate 110 has an evaporation end and a condensation end disposed opposite to each other, and the evaporation end is in contact with the cover plate 130 a. The heat emitted from the chip assembly 220 (the first chip 2211 and the second chip 2212 which are stacked together) can be conducted to the cover plate 130a, the refrigerant in the heat dissipation plate 110 absorbs the heat conducted from the chip assembly 220 to the cover plate 130a at the evaporation end and flows to the condensation end, and after the heat is released by condensation at the condensation end, the heat flows back to the evaporation end, so that the heat dissipation plate 110 can perform the function of heat dissipation at the same temperature for the chip assembly 220.

The heat dissipation plate 110 is disposed at a side of the cover plate 130a away from the second chip 2212, so that the heat dissipation plate 110 can perform uniform temperature heat dissipation on the first chip 2211 and the second chip 2212. And, the heat dissipation plate 110 can be located outside the shielding case 130, so as to reduce the influence of the shielding case 130 on the heat dissipation of the heat dissipation plate 110.

The power consumption of the current electronic device 300 increases greatly, and the heat generation amount of the chip assembly 220 increases. Taking the first chip 2211 as an example, in the POP package structure, the first chip 2211 and the second chip 2212 are stacked, and the heat dissipation plate 110 is located on a side of the second chip 2212 away from the first chip 2211, so that heat dissipated by the first chip 2211 needs to be conducted to the heat dissipation plate 110 through the second chip 2212.

Since the second chip 2212 generates heat, and the thermal conductivity of the second chip 2212 is low, the second chip 2212 blocks the heat emitted by the first chip 2211 from being conducted to the heat dissipation plate 110. In addition, the insulating layer 212 of the substrate 210 has a low thermal conductivity, which blocks heat dissipated by the first chip 2211 from being conducted to the substrate 210.

In this way, heat is accumulated in and around the first chip 2211, so that the temperature of the first chip 2211 is increased, which increases the risk that the first chip 2211 cannot work properly due to the excessive temperature, and affects the performance of the first chip 2211.

FIG. 5 is a schematic cross-sectional view of FIG. 3 along the direction A-A in accordance with other embodiments of the present application.

In some cases, as shown in fig. 5, the substrate 210 includes a first substrate 210a and a second substrate 210b, the first substrate 210a and the second substrate 210b are stacked, and the first substrate 210a and the second substrate 210b are electrically connected through an electrical connection structure 213. By doing so, the number of components electrically connected to the substrate 210 can be increased.

As illustrated in fig. 5, the cavity between the first substrate 210a and the second substrate 210b is filled with a thermal interface material T to reduce thermal resistance between the first substrate 210a and the second substrate 210 b.

It will be appreciated that the insulating layer 212 blocks heat emitted from the first chip 2211 from being conducted on the substrate 210, so that even if the cavity between the first substrate 210a and the second substrate 210b is filled with the thermal interface material T, the thermal conductivity of the substrate 210 in the axial direction (the lamination direction of the first substrate 210a and the second substrate 210 b) is still far lower than the thermal conductivity of the substrate 210 in the plane (parallel to the surface of the substrate 210), which affects the heat dissipation capacity of the chip assembly 220 (especially the first chip 2211).

FIG. 6 is a schematic cross-sectional view of FIG. 3 along the direction A-A according to still other embodiments of the present application. FIG. 7 is a schematic cross-sectional view of FIG. 3 along the direction A-A according to still other embodiments of the present application. FIG. 8 is a schematic cross-sectional view of FIG. 3 along the direction A-A according to still other embodiments of the present application. FIG. 9 is a schematic cross-sectional view of FIG. 3 along the direction A-A according to still other embodiments of the present application.

Based on this, as shown in fig. 6 and 7, an embodiment of the present application provides an electronic device 200, where the electronic device 200 includes a substrate 210, a first chip 2211 and a second chip 2212 (i.e. a chip assembly 220) stacked together, and a package structure 100, and the package structure 100 includes a heat conducting medium 140, a heat dissipation plate 110, and a heat conducting wall 120.

That is, as shown in fig. 6 and 7, the electronic device 200 includes a substrate 210, a first chip 2211 and a second chip 2212 (i.e. a chip assembly 220) stacked together, a heat conducting medium 140, a heat dissipating plate 110, and a heat conducting wall 120. It is to be understood that the above embodiments of the present application have been illustrated by the first chip 2211, the second chip 2212, the heat dissipation plate 110, etc., and will not be described herein.

In some examples, as shown in fig. 6 and 7, the multi-layer conductive layer 211 of the substrate 210 includes a heat transfer conductive layer 211a, the heat transfer conductive layer 211a including a heat transfer structure (not shown), that is, the substrate 210 includes a heat transfer structure. The front projection of the first chip 2211 on the substrate 210 overlaps the heat transfer structure.

For example, one heat transfer conductive layer 211a may be included in the multi-layer conductive layer 211, and two, three, or more heat transfer conductive layers 211a may be included in the multi-layer conductive layer 211. The material of the heat transfer conductive layer 211a may be copper. For example, the heat transfer conductive layer 211a may include only a heat transfer structure, or the heat transfer conductive layer 211a may include conductive traces in addition to the heat transfer structure.

It will be appreciated that the heat transfer structure has a relatively high thermal conductivity. Providing the heat transfer conductive layer 211a includes a heat transfer structure, which can increase the metal (e.g., copper) content in the heat transfer conductive layer 211a, thereby increasing the heat conductive property of the heat transfer conductive layer 211 a. For example, the heat transfer structure is electrically connected to a Ground (GND) and may be a GND network.

The orthographic projection of the first chip 2211 on the substrate 210 overlaps with the heat transfer structure, that is, the arrangement position of the first chip 2211 corresponds to the arrangement position of the heat transfer structure. For example, the front projection of the first chip 2211 on the substrate 210 may completely overlap the heat transfer structure, or the front projection of the first chip 2211 on the substrate 210 may also partially overlap the heat transfer structure.

The orthographic projection of the first chip 2211 on the substrate 210 overlaps the heat transfer structure, so that the heat emitted by the first chip 2211 can be conducted to the heat transfer structure, and the heat can be rapidly diffused on the heat transfer structure and conducted to other components (such as the heat conducting wall 120), so that the heat transfer structure can play a role of rapid uniform temperature heat dissipation.

In some examples, as shown in fig. 6 and 7, the heat conducting medium 140 is located on a side of the second chip 2212 remote from the first chip 2211, and is connected to the second chip 2212. The heat dissipation plate 110 is located at a side of the heat conduction medium 140 away from the second chip 2212, and is connected to the heat conduction medium 140. The heat conductive wall 120 is located between the heat conductive medium 140 and the substrate 210, and connects the heat conductive medium 140 and the substrate 210.

It will be appreciated that the heat conductive wall 120 is connected to the substrate 210 such that the heat transfer structure is capable of conducting heat emitted by the first chip 2211 to the heat conductive wall. And, the heat conductive wall 120 is connected with the heat conductive medium 140, and the heat conductive medium 140 is connected with the heat dissipation plate 110, so that the heat conductive wall 120 can conduct the heat emitted from the first chip 2211 to the heat dissipation plate 110 through the heat conductive medium 140.

That is, the heat emitted by the first chip 2211 can be firstly conducted downward (in the direction close to the substrate 210) to the heat transfer structure, and then conducted upward (in the direction far away from the substrate 210) to the heat conducting wall 120 and conducted to the heat dissipating plate 110 via the heat conducting medium 140, so that the heat transfer path between the first chip 2211 and the heat dissipating plate 110 is increased, the influence of the second chip 2212 on the heat dissipation of the first chip 2211 is reduced, the heat dissipation capacity of the first chip 2211 is improved, the heat dissipation capacity of the first chip 2211 is increased, and the performance of the first chip 2211 is improved.

The heat emitted from the first chip 2211 and the second chip 2212 may also be transferred to the heat conductive wall 120 transversely (parallel to the direction of the substrate 210) and transferred to the heat dissipation plate 110 via the heat conductive wall 120 and the heat conductive medium 140, so that a heat transfer path between the first chip 2211 and the second chip 2212 and the heat dissipation plate 110 is increased, a heat dissipation capacity of the first chip 2211 and the second chip 2212 is improved, a heat dissipation capacity of the first chip 2211 and the second chip 2212 is increased, and performance of the first chip 2211 and the second chip 2212 is improved. It is understood that the heat conducting medium 140 is located on the side of the second chip 2212 away from the first chip 2211, so that the heat emitted by the second chip 2212 can be conducted to the heat dissipation plate 110 via the heat conducting medium 140.

It is understood that the heat conductive medium 140 can function to conduct heat of the heat conductive wall 120 to the heat dissipation plate 110. For example, the heat conducting medium 140 may be the cover plate 130a of the shielding case 130, the heat conducting medium 140 may be the thermal interface material T between the heat conducting wall 120 and the cover plate 130a, and the heat conducting medium 140 may be the thermal interface material T between the heat conducting wall 120 and the heat dissipating plate 110.

In an embodiment of the present application, the heat emitted by the first chip 2211 can be conducted to the heat transfer structure, and is conducted to the heat conducting wall 120 through the heat transfer structure, and the heat conducting wall 120 can conduct the heat to the heat dissipating plate 110 through the heat conducting medium 140. That is, the heat emitted from the first chip 2211 can be firstly transferred to the heat transfer structure downward (in a direction approaching the substrate 210), and then transferred to the heat dissipation plate 110 upward (in a direction away from the substrate 210). In this way, the heat emitted by the first chip 2211 does not need to be conducted to the heat dissipation plate 110 through the second chip 2212, so that a heat transfer path between the first chip 2211 and the heat dissipation plate 110 is increased, the influence of the second chip 2212 on the heat dissipation of the first chip 2211 is reduced, the heat dissipation capacity of the first chip 2211 is improved, the heat dissipation capacity of the first chip 2211 is increased, the risk that the first chip 2211 cannot work normally due to overhigh temperature is reduced, and the performance of the first chip 2211 is improved.

In addition, by arranging the heat transfer structure and the heat conducting wall 120, heat conducted from the first chip 2211 to the side, far away from the first chip 2211, of the substrate 210 is reduced, the influence of the substrate 210 on heat dissipation of the first chip 2211 is reduced, the heat dissipation capacity of the first chip 2211 is improved, the heat dissipation capacity of the first chip 2211 is increased, the risk that the first chip 2211 cannot work normally due to overhigh temperature is reduced, and the performance of the first chip 2211 is improved.

It can be appreciated that the heat emitted by the first chip 2211 and the second chip 2212 can also be transferred to the heat-conducting wall 120 transversely (parallel to the direction of the substrate 210), the heat-conducting wall 120 transfers the heat to the heat-dissipating plate 110 through the heat-conducting medium 140, the heat transfer path between the first chip 2211 and the second chip 2212 and the heat-dissipating plate 110 is increased, the heat dissipation capacity of the first chip 2211 and the second chip 2212 is improved, the heat dissipation capacity of the first chip 2211 and the second chip 2212 is increased, the risk that the first chip 2211 and the second chip 2212 cannot work normally due to overhigh temperature is reduced, and the performance of the first chip 2211 and the second chip 2212 is improved.

It will be appreciated that embodiments of the present application enable board-level enhanced heat dissipation structures for POP packages by providing thermally conductive walls 120 and heat transfer structures.

In some examples, the material of the thermally conductive wall 120 may include a metal, an alloy, or silicon (e.g., monocrystalline silicon or polycrystalline silicon) to increase the thermal conductivity of the thermally conductive wall 120, thereby increasing the heat dissipation capability of the first chip 2211 and the second chip 2212.

For example, when the material of the heat conductive wall 120 includes a metal or an alloy, the material of the heat conductive wall 120 may include at least one of copper, aluminum, gold, and silver. Or the material of the heat conducting wall 120 may also include other metals with higher heat conductivity coefficients, and the material of the heat conducting wall 120 is not further limited in the embodiments of the present application.

In some examples, the orthographic projection of the first chip 2211 on the substrate 210 is within the confines of the heat transfer structure.

So arranged, the placement position of the heat transfer structure can correspond to the placement position of the chip 220. In this way, the heat dissipated by the first chip 2211 can be conducted to the heat transfer structure and rapidly spread on the heat transfer structure, the heat transfer structure can conduct the heat to the heat conducting wall 120, and the heat conducting wall 120 can conduct the heat to the heat dissipating plate 110 through the heat conducting medium 140, so that the heat dissipating capacity of the first chip 2211 is improved, the heat dissipating capacity of the first chip 2211 is increased, and the performance of the first chip 2211 is improved.

For example, the orthographic projection of the thermally conductive wall 120 onto the substrate 210 may also be within the scope of the heat transfer structure.

Taking the material of the heat-conducting wall 120 as metal and the first chip 2211 as SOC as an example, the orthographic projection of the first chip 2211 on the substrate 210 is set within the range of the heat transfer structure, so that the ratio of the running time of the SOC at the maximum power to the original running time (i.e., the running time of the SOC at the maximum power when the heat transfer structure is not set) is about 200%.

In some examples, as shown in fig. 6 and 7, the solder mask 214 of the substrate 210 has a window (not shown) penetrating the solder mask 214 in a thickness direction of the solder mask 214, exposing the conductive layer 211 covered by the solder mask 214.

It will be appreciated that, as shown in fig. 6, when the solder resist layer 214 covers the heat transfer conductive layer 211a, the window can expose the heat transfer conductive layer 211a. As shown in fig. 7, when the solder resist layer 214 covers the other conductive layers 211 (e.g., the conductive connection layer 215) other than the heat transfer conductive layer 211a, the conductive connection layer 215 can be exposed.

As shown in fig. 6 and 7, the heat conductive wall 120 includes a body portion 121 and a filling portion 123 connected to each other. The main body 121 is located between the substrate 210 and the heat transfer medium 140, and the filling portion 123 is filled in the window and connected to the heat transfer structure.

It will be appreciated that the filler portion 123 may be directly connected to the heat transfer structure when the window is opened to expose the heat transfer conductive layer 211 a. The filling portion 123 may be indirectly connected to the heat transfer structure through the other conductive layer 211 (e.g., the conductive connection layer 215) other than the heat transfer conductive layer 211a, when the other conductive layer 211 (e.g., the conductive connection layer 215) other than the heat transfer conductive layer 211a is exposed at the opening.

The filling portion 123 is filled in the window and is connected with the heat transfer structure, the main body portion 121 is connected with the filling portion 123, the influence of the solder mask 214 on connection between the heat conducting wall 120 (the filling portion 123) and the heat transfer structure can be reduced, the thermal resistance between the heat conducting wall 120 and the heat transfer structure is reduced, the heat dissipation capacity of the first chip 2211 is improved, and the heat dissipation capacity of the first chip 2211 is increased.

In some examples, as shown in fig. 6, the solder mask layer 214 covers the heat transfer conductive layer 211a, and the fenestration exposes the heat transfer structure to which the filler 123 is connected.

By such arrangement, the connection convenience between the filling portion 123 and the heat transfer structure can be improved, and the thermal resistance between the heat conductive wall 120 and the heat transfer structure is reduced, the heat dissipation capacity of the first chip 2211 is improved, and the heat dissipation capacity of the first chip 2211 is increased.

In other examples, as shown in fig. 7, the conductive layer 211 includes a conductive connection layer 215, the solder mask layer 215 covers the conductive connection layer 215, and the conductive connection layer 215 is connected to the heat transfer structure. The conductive connection layer 215 is exposed through the window, and the filling portion 213 is connected to the conductive connection layer 215.

By the arrangement, the flexibility of connection between the filling part 213 and the heat transfer structure can be improved, and different requirements can be met.

For example, the conductive connection layer 215 and the heat transfer structure may be connected by a conductive via penetrating the insulating layer 212, so that the filling part 123 can be connected with the heat transfer structure through the conductive connection layer 215. The number of conductive vias may be multiple, with multiple conductive vias being spaced apart to reduce the thermal resistance between the conductive connection layer 215 and the heat transfer structure.

In some examples, as shown in fig. 6 and 7, the heat conductive wall 120 further includes a connection portion 122, the connection portion 122 connecting the body portion 121 and the filling portion 123.

As can be appreciated, providing the connection portion 122 to connect the body portion 121 and the filling portion 123 can improve the connection convenience therebetween.

In some examples, the material of the body portion 121 may include a metal or an alloy, e.g., the material of the body portion 121 may include copper, aluminum, gold, silver, and the like. In other examples, the material of the body portion 121 may also include silicon (e.g., monocrystalline silicon or polycrystalline silicon).

In some examples, the material of the filling portion 123 may include a metal or an alloy, for example, the material of the filling portion 123 may include copper, aluminum, gold, silver, or the like. At this time, the filling portion 123 and the heat transfer structure may be electrically connected. In other examples, the material of the filling portion 123 may also include silicon (e.g., monocrystalline silicon or polycrystalline silicon). It will be appreciated that the materials of the body portion 121 and the filler portion 123 may be the same or different.

In some examples, the material of the connection portion 122 may include a metal or an alloy, for example, the material of the connection portion 122 may include copper, aluminum, gold, silver, or the like. It will be appreciated that when the material of the body portion 121 and the filling portion 123 includes a metal or an alloy, the material of the body portion 121, the connecting portion 122, and the filling portion 123 may be the same or different.

The material of the body portion 121 is composed of metal, alloy or silicon, the material of the filling portion 123 is composed of metal, alloy or silicon, the material of the connection portion 122 is composed of metal or alloy, the thermal resistance of the heat conductive wall 120 can be reduced, the heat radiation capability of the chip assembly 220 (including the first chip 2211 and the second chip 2212 which are stacked), the heat radiation capability of the chip assembly 220 can be increased, and the flexibility of the heat conductive wall 120 in material selection can be improved.

In some examples, the material of the body portion 121 includes copper, the material of the fill portion 123 includes copper, and the material of the connection portion 122 includes solder or nickel gold.

For example, when the material of the connection part 122 includes solder, the connection part 122 may be formed by tin plating or tin spraying. When the material of the connection portion 122 includes nickel gold, the connection portion 122 may be formed using nickel gold. The body portion 121 may be connected to the filling portion 123 through the connection portion 122 by reflow soldering.

The material of the main body 121 includes copper, the material of the filling portion 123 includes copper, the material of the connecting portion 122 includes solder or nickel gold, so that the thermal resistance of the heat conductive wall 120 can be reduced, the heat dissipation capacity of the chip assembly 220 (including the first chip 2211 and the second chip 2212 which are stacked) can be improved, and the heat dissipation capacity of the chip assembly 220 can be increased.

In some examples, as shown in fig. 6, a thermal interface material (english: THERMAL INTERFACE MATERIAL, english: TIM) T is filled between the side of the second chip 2212 away from the first chip 2211 and the cover plate 130 a.

It will be appreciated that the thermal interface material T has a relatively high coefficient. The thermal interface material T is filled between the side, far away from the first chip 2211, of the second chip 2212 and the cover plate 130a of the shielding case 130, so that heat emitted by the chip assembly 220 (including the first chip 2211 and the second chip 2212 which are stacked) during operation can be conducted to the cover plate 130a through the thermal interface material T and to the heat dissipation plate 110 through the cover plate 130a, thermal resistance between the second chip 2212 and the cover plate 130a can be reduced, heat dissipation capacity of the chip assembly 220 is improved, heat dissipation capacity of the chip assembly 220 is increased, risk that the chip assembly 220 cannot work normally due to overhigh temperature is reduced, and performance of the chip assembly 220 is improved.

For example, thermal interface material T may be a flexible material such that thermal interface material T can be bonded to a side of second chip 2212 remote from first chip 2211 and cover plate 130 a. The thermal interface material T may include a polymer metal composite, a ceramic composite, a carbon-based composite, or the like. The thermal interface material T may be a thermally conductive silicone gel or a thermally conductive silicone grease, etc. It will be appreciated that embodiments of the present application do not further limit the material of the thermal interface material T.

In some examples, as shown in fig. 6, a thermal interface material T is filled between the cover plate 130a and the heat dissipation plate 110. By the arrangement, the heat conducted to the cover plate 130a by the chip assembly 220 (including the first chip 2211 and the second chip 2212 which are stacked together) can be conducted to the heat dissipation plate 110 via the thermal interface material T, so that the thermal resistance between the cover plate 130a and the heat dissipation plate 110 can be reduced, the heat dissipation capacity of the chip assembly 220 is improved, the heat dissipation capacity of the chip assembly 220 is increased, the risk that the chip assembly 220 cannot work normally due to overhigh temperature is reduced, and the performance of the chip assembly 220 is improved.

As can be appreciated, the limited accommodation space within the housing 301 limits the thickness of the thermal interface material T (the thermal interface material T between the second chip 2212 and the cover plate 130a, and the thermal interface material T between the cover plate 130a and the heat sink 110), affecting the thermal conductivity of the thermal interface material T and thus the heat dissipation capacity of the chip assembly 220. Illustratively, the thermal interface material T has a thermal conductivity of less than or equal to 6W/(mK) (units: W/mKelvin).

On the basis of filling the thermal interface material T between the chip assembly 220 and the cover plate 130a, and between the cover plate 130a and the heat dissipation plate 110, the heat conduction wall 120 and the heat transfer structure are provided, so that the heat dissipation capacity of the chip assembly 220 (especially the first chip 2211) is increased, the heat conduction area of the chip assembly 220 to the heat dissipation plate 110 is increased, and the performance of the chip assembly 20 is improved, thereby improving the performance of the electronic device 300.

In some examples, the side wall 130b of the shield 130 is disposed adjacent to the thermally conductive wall 120. For example, as shown in fig. 6 and 7, the shielding case 130 may cover the heat conducting wall 120, and the side wall 130b surrounds the heat conducting wall 120, so that the heat conducting wall 120 can be disposed adjacent to the side wall 130 b. Alternatively, as shown in fig. 8 and 9, the thermally conductive wall 120 may be located outside the shield can 130, with the thermally conductive wall 120 being disposed adjacent to the side wall 130 b.

The following exemplifies the case where the shielding case 130 is covered with the heat conductive wall 120, or the case where the heat conductive wall 120 is located outside the shielding case 130, respectively.

In some examples, as shown in fig. 6 and 7, the shield can 130 houses the first chip 2211, the second chip 221, and the thermally conductive wall 120. Wherein the heat conducting medium 140 includes a cover plate 130a.

When the shielding case 130 covers the first chip 2211, the second chip 221 and the heat conducting wall 120, the heat conducting wall 120 is located between the cover plate 130a and the substrate 210 and is disposed adjacent to the chip assembly 220, and the side wall 130b encloses the chip assembly 220 and the heat conducting wall 120.

The heat emitted from the first chip 2211 is conducted to the heat transfer structure and is conducted to the heat conductive wall 120 through the heat conductive structure. The heat on the heat conductive wall 120 is conducted to the heat dissipation plate 110 through the cover plate 120a (i.e., the heat conductive medium 140). The heat emitted from the second chip 2212 can be transferred to the heat conductive wall 120 laterally (parallel to the direction of the substrate 210), and the heat on the heat conductive wall 120 is transferred to the heat dissipation plate 110 through the cover plate 120a (i.e., the heat conductive medium 140). That is, the cover plate 130a can serve as the heat conducting medium 140 to conduct the heat on the heat conducting wall 120 to the heat dissipating plate 110.

For example, as shown in fig. 6 and 7, when the shielding case 130 houses the first chip 2211, the second chip 2212, and the heat conductive wall 120, a gap may be provided between the heat conductive wall 120 and the side wall 130 b.

The shielding cover 130 is arranged to cover the first chip 2211, the second chip 2212 and the heat conducting wall 120, so that the heat conducting wall 120 can conduct heat to the heat radiating plate 110 through the cover plate 130a, and compared with the case that the heat conducting wall 120 is arranged outside the shielding cover 130, the shielding cover 130 can protect the heat conducting wall 120, and the risk of damage to the heat conducting wall 120 is reduced.

In some examples, as shown in fig. 6 and 7, when the shielding case 130 is covered with the heat conductive wall 120, a thermal interface material T is filled between an end of the heat conductive wall 120 remote from the substrate 210 and the cover plate 130 a. Wherein the heat conductive medium 140 includes a thermal interface material T between the heat conductive wall 120 and the cover plate 130 a.

This arrangement allows heat on the thermally conductive wall 120 to be conducted through the thermal interface material T and the cover plate 130a to the heat sink, i.e., the cover plate 130a, and the thermal interface material T between the thermally conductive wall 120 and the cover plate 130a to be able to conduct the thermal medium 140.

As can be appreciated, the thermal interface material T is filled between the end of the heat conducting wall 120 far away from the substrate 210 and the cover plate 130a, so that the thermal resistance between the heat conducting wall 120 and the cover plate 130a can be reduced, and the heat emitted by the chip assembly 220 (the first chip 2211 and the second chip 2212) can be quickly conducted to the cover plate 130a through the heat conducting wall 120 and to the heat dissipating plate 110 through the cover plate 130a, so that the heat dissipating capacity of the chip assembly 220 is improved, and the heat dissipating capacity of the chip assembly 220 is increased, thereby improving the performance of the chip assembly 220.

In some examples, as shown in fig. 6 and 7, when the heat conductive wall 120 is covered by the shielding case 130, a thermal interface material T is filled between the stacked first and second chips 2211 and 2212 (i.e., the chip assembly 220) and the heat conductive wall 120. It is understood that the thermal interface material T is located between the package 221b (e.g., the package substrate 221b1 and the molding compound 221b 2) of the chip 221 and the heat conductive wall 120.

By this arrangement, the thermal resistance between the chip assembly 220 and the heat conducting wall 120, that is, the thermal resistance when heat is conducted in the transverse direction (parallel to the direction of the substrate 210) can be reduced, so that the heat emitted by the chip assembly 220 can be rapidly conducted to the heat conducting wall 120 and conducted to the heat dissipating plate 110 through the heat conducting wall 120 and the heat conducting medium 140, the heat dissipating capacity of the chip assembly 220 is improved, the heat dissipating capacity of the chip assembly 220 is increased, and the performance of the chip assembly 220 is improved.

In other examples, as shown in fig. 8 and 9, the thermally conductive wall 120 is located outside of the shield 130.

When the heat-conducting wall 120 is located outside the shielding case 130, the heat emitted by the first chip 2211 may be transferred to the heat-transferring structure, the heat-transferring structure transfers the heat to the heat-conducting wall 120, and the heat-conducting wall 120 transfers the heat to the heat-dissipating plate 110 through the heat-conducting medium 140. The heat emitted from the second chip 2212 is transferred to the heat conductive wall 120 laterally (parallel to the direction of the substrate 210), and the heat conductive wall 120 transfers the heat to the heat dissipation plate 110 through the heat conductive medium 140.

For example, as shown in fig. 9 and 10, when the thermally conductive wall 120 is located outside the shield can 130, a gap may be provided between the chip assembly 220 and the side wall 130 b.

It is appreciated that disposing the thermally conductive wall 120 outside of the shield can 130 can reduce electromagnetic interference caused by the thermally conductive wall 120 to the chip assembly 220 as compared to disposing the shield can 130 to house the chip assembly 220 and the thermally conductive wall 120.

It will be appreciated that the placement of the thermally conductive wall 120 within or outside of the shield 130 can increase the flexibility of placement of the thermally conductive wall 120 to meet different needs.

In some examples, as shown in fig. 8 and 9, when the heat conductive wall 120 is located outside the shielding case 130, a thermal interface material T is filled between an end of the heat conductive wall 120 remote from the substrate 210 and the heat dissipation plate 110. Wherein the heat conductive medium 140 includes a thermal interface material T between the heat conductive wall 120 and the heat dissipation plate 110.

After the heat emitted by the chip assembly 220 is conducted to the heat conducting wall 120, the heat can be conducted to the heat dissipating plate 110 through the thermal interface material T (the heat conducting medium 140), so that the thermal resistance between the heat conducting wall 120 and the heat dissipating plate 110 is reduced, the heat dissipating capacity of the chip assembly 220 is improved, the heat dissipating capacity of the chip assembly 220 is increased, and the performance of the chip assembly 220 is improved.

In some examples, as shown in fig. 8 and 9, thermal interface material T is filled between thermally conductive wall 120 and sidewall 130b when thermally conductive wall 120 is located outside of shield can 130.

By this arrangement, the thermal resistance between the heat conducting wall 120 and the side wall 130b, that is, the thermal resistance when heat is conducted in the transverse direction (parallel to the direction of the substrate 210) can be reduced, so that the heat conducted from the chip assembly 220 to the side wall 130b can be quickly conducted to the heat conducting wall 120 and conducted to the heat dissipating plate 110 through the heat conducting wall 120 and the heat conducting medium 140, the heat dissipating capacity of the chip assembly 220 is improved, and the heat dissipating capacity of the chip assembly 220 is increased, thereby improving the performance of the chip assembly 220.

In some examples, thermal interface material T is filled between chip assembly 220 and sidewall 130b when thermally conductive wall 120 is located outside of shield can 130.

By this arrangement, the thermal resistance between the chip assembly 220 and the side wall 130b, that is, the thermal resistance when heat is conducted in the transverse direction (parallel to the direction of the substrate 210) can be reduced, so that the heat emitted by the chip assembly 220 can be quickly conducted to the side wall 130b and conducted to the heat conducting wall 120 through the side wall 130b, the heat dissipation capacity of the chip assembly 220 is improved, the heat dissipation capacity of the chip assembly 220 is increased, and the performance of the chip assembly 220 is improved.

Taking the material of the heat conductive wall 120 as a metal and the first chip 2211 as an SOC as an example, by providing the heat conductive wall 120 and filling the thermal interface material T between the heat conductive wall 120 and the cover plate 130a (or between the heat conductive wall 120 and the heat dissipation plate 110) and between the heat conductive wall 120 and the chip assembly 220 (or between the heat conductive wall 120 and the side wall 130 b), the ratio of the running time of the SOC at the maximum power to the original running time (i.e., the running time of the SOC at the maximum power without filling the thermal interface material T between the heat conductive wall 120 and other components) is about 200%.

On this basis, the arrangement of the electrically conductive layer 211 comprising the heat transfer structure, the orthographic projection of the first chip 2211 and the heat conductive wall 120 on the substrate 210 is located within the range of the heat transfer structure, such that the ratio of the run time of the SOC at maximum power to the original run time (i.e. the run time of the SOC at maximum power without the heat transfer structure arranged and without the interface material T filled between the heat conductive wall 120 and the other components) is about 350%.

Fig. 10 is a top view of an electronic device according to some embodiments of the present application. Fig. 11 is a top view of an electronic device according to other embodiments of the present application. Fig. 12 is a top view of an electronic device according to still other embodiments of the present application. Fig. 13 is a top view of an electronic device according to still other embodiments of the present application. It will be appreciated that fig. 10 to 13 show the case where the heat conductive wall 120 is covered by the shield case 130. In order to clearly show the positional relationship of the heat conductive wall 120 and the chip assembly 220, the heat dissipation plate 110, the cover plate 130a, and the thermal interface material T between the heat dissipation plate 110 and the cover plate 130a are not shown in fig. 10 to 13.

In some examples, as shown in fig. 10, the thermally conductive wall 120 is annular, and the thermally conductive wall 120 surrounds the first chip 2211 and the second chip 2212 (i.e., the chip assembly 220) that are stacked.

By way of example, the heat conductive wall 120 may be a circular ring, a rectangular ring, etc., or may be other irregular annular structures. Taking the material of the heat conducting wall 120 as an example, the heat conducting wall 120 may be a high heat conducting metal ring.

As can be appreciated, the annular heat-conducting wall 120 surrounds the first chip 2211 and the second chip 2212 which are stacked, so that the heat-conducting wall 120 can conduct heat emitted from different positions of the chip assembly 220 to the heat dissipation plate 110, thereby improving the heat dissipation capacity of the chip assembly 220 and increasing the heat dissipation capacity of the chip assembly 220.

In some examples, as shown in fig. 11, the thermally conductive wall 120 is cylindrical.

By way of example, the thermally conductive wall 120 may be cylindrical, prismatic, etc., or may have other irregular columnar structures. Taking the material of the heat conducting wall 120 as an example, the heat conducting wall 120 may be a high heat conducting metal column. The columnar heat-conducting wall 120 may be disposed adjacent to the chip assembly 220 to conduct the heat emitted from the chip assembly 220 to the heat dissipation plate 110, thereby improving the heat dissipation capacity of the chip assembly 220 and increasing the heat dissipation capacity of the chip assembly 220.

For example, as shown in fig. 11, the columnar heat conductive wall 120 may be located at one side of the chip assembly 220 in the first direction X. Or the heat conductive wall 120 may be located at one side of the chip assembly 220 in the second direction Y. The first direction X intersects the second direction Y. In some examples, the first direction X is perpendicular to the second direction Y. It is understood that the plane in which the first direction X and the second direction Y are located is parallel to the surface of the substrate 210.

It can be appreciated that the heat conducting wall 120 is columnar, which can simplify the structure of the heat conducting wall 120 and facilitate miniaturization of the electronic device 200.

It can be appreciated that the shape of the heat conducting wall 120 is annular or columnar, so that the flexibility of setting the heat conducting wall 120 can be improved, and different requirements can be met.

In some examples, as shown in fig. 12 and 13, when the heat conductive walls 120 are columnar, the number of the heat conductive walls 120 is plural, and the plural heat conductive walls 120 surround the first chip 2211 and the second chip 2212 (i.e., the chip assembly 220) which are stacked.

By way of example, the number of columnar thermally conductive walls 120 may be two, three, four, or more. At least two of the plurality of columnar heat conductive walls 120 may be located on the same side of the chip assembly 220 along the first direction X or the second direction Y. At least two of the plurality of columnar heat conductive walls 120 may also be disposed opposite in the first direction X or the second direction Y.

The plurality of columnar heat conductive walls 120 encircle the first chip 2211 and the second chip 2212 which are stacked, so that the heat conductive walls 120 can conduct heat emitted from different positions of the chip assembly 220 to the heat dissipation plate 110, thereby improving the heat dissipation capacity of the chip assembly 220 and increasing the heat dissipation capacity of the chip assembly 220.

In summary, the embodiments of the present application have at least the following advantages:

It can be appreciated that the heat emitted by the first chip 2211 and the second chip 2212 can also be transferred to the heat-conducting wall 120 transversely (parallel to the direction of the substrate 210), the heat-conducting wall 120 transfers the heat to the heat-dissipating plate 110 through the heat-conducting medium 140, the heat transfer path between the first chip 2211 and the second chip 2212 and the heat-dissipating plate 110 is increased, the heat dissipation capacity of the first chip 2211 and the second chip 2212 is improved, the heat dissipation capacity of the first chip 2211 and the second chip 2212 is increased, the risk that the first chip 2211 and the second chip 2212 cannot work normally due to overhigh temperature is reduced, and the performance of the first chip 2211 and the second chip 2212 is improved. The foregoing is merely illustrative of the embodiments of the present application, and the present application is not limited thereto, and any person skilled in the art will recognize that changes and substitutions are within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. An electronic device, comprising:

a substrate comprising a heat transfer structure;

the heat transfer structure comprises a substrate, a first chip, a second chip, a first chip and a second chip, wherein the first chip and the second chip are stacked, and the first chip is close to the substrate relative to the second chip;

The heat conducting medium is positioned on one side of the second chip far away from the first chip and is connected with the second chip;

A heat dissipation plate disposed on a side of the heat transfer medium away from the second chip and connected with the heat transfer medium, and

And the heat conducting wall is positioned between the heat conducting medium and the substrate and is connected with the heat conducting medium and the substrate.

2. The electronic device of claim 1, wherein an orthographic projection of the first chip on the substrate is within the range of the heat transfer structure.

3. The electronic device according to claim 1 or 2, wherein the substrate comprises a plurality of conductive layers and a plurality of insulating layers which are alternately stacked, the plurality of conductive layers comprising the heat transfer conductive layer and the heat transfer conductive layer comprising a heat transfer structure, the substrate further comprising a solder resist layer covering one of the conductive layers, the solder resist layer having a window penetrating the solder resist layer in a thickness direction thereof to expose the conductive layer covered by the solder resist layer;

The heat conducting wall comprises a main body part and a filling part which are connected with each other, the main body part is positioned between the substrate and the heat conducting medium, and the filling part is filled in the open window and is connected with the heat transfer structure.

4. The electronic device of claim 3, wherein the solder mask layer covers the heat transfer conductive layer, the window exposes the heat transfer structure, the filling portion is connected to the heat transfer structure, or,

The conductive layer comprises a conductive connecting layer, the solder mask layer covers the conductive connecting layer, the conductive connecting layer is connected with the heat transfer structure, the conductive connecting layer is exposed through the window, and the filling part is connected with the conductive connecting layer.

5. The electronic device of claim 3 or 4, wherein the thermally conductive wall further comprises a connecting portion connecting the main body portion and the filling portion.

6. The electronic device of claim 5, wherein the material of the body portion comprises a metal, an alloy, or silicon, the material of the filler portion comprises a metal, an alloy, or silicon, and the material of the connection portion comprises a metal or an alloy.

7. The electronic device of claim 6, wherein the material of the main body portion comprises copper, the material of the filling portion comprises copper, and the material of the connecting portion comprises solder or nickel-gold.

8. The electronic device of any one of claims 1-7, further comprising:

the heat conducting device comprises a shielding cover, wherein the shielding cover is provided with a first chip and a second chip which are arranged in a stacked mode, the shielding cover comprises a cover plate and a side wall, the cover plate is connected with the side wall, the cover plate is located at one side, away from the first chip, of the second chip, the heat radiating plate is located at one side, away from the second chip, of the cover plate, and the side wall is arranged adjacent to the heat conducting wall.

9. The electronic device of claim 8, wherein the shield covers the first chip, the second chip, and the thermally conductive wall;

Wherein the heat conducting medium comprises the cover plate.

10. The electronic device of claim 9, wherein a thermal interface material is filled between the cover plate and an end of the thermally conductive wall remote from the substrate;

wherein the thermally conductive medium comprises a thermal interface material between the thermally conductive wall and the cover plate.

11. The electronic device of claim 9 or 10, wherein a thermal interface material is filled between the stacked first and second chips and the thermally conductive wall.

12. The electronic device of claim 8, wherein the thermally conductive wall is located outside of the shield.

13. The electronic device of claim 12, wherein a thermal interface material is filled between an end of the thermally conductive wall remote from the substrate and the heat sink;

Wherein the heat conducting medium comprises a thermal interface material between the heat conducting wall and the heat dissipating plate.

14. The electronic device of claim 12 or 13, wherein a thermal interface material is filled between the side wall and the thermally conductive wall.

15. The electronic device of any one of claims 1-14, wherein the thermally conductive wall is annular, and the thermally conductive wall surrounds the first and second chips in a stacked arrangement.

16. The electronic device of any one of claims 1-14, wherein the thermally conductive wall is columnar.

17. The electronic device of claim 16, wherein the number of thermally conductive walls is a plurality, the plurality of thermally conductive walls surrounding the stacked first and second chips.

18. The electronic device according to any one of claims 1 to 17, wherein the heat dissipation plate is a vacuum vapor chamber.

19. A substrate comprising a plurality of conductive layers and a plurality of insulating layers alternately stacked, the plurality of conductive layers comprising a heat transfer conductive layer comprising a heat transfer structure.

20. An electronic device, comprising:

A housing;

the electronic device according to any one of claims 1-18, wherein the electronic device is located in an accommodating space enclosed by the housing.