CN120263170A - Single-stage multi-mode frequency divider based on variable capacitor - Google Patents

Abstract

The present invention discloses a single-stage multi-mode frequency divider based on variable capacitance, comprising: a clock input circuit for generating a differential high-speed clock with adjustable swing according to a differential input clock; a mode switching circuit for generating differential clocks CK_1 and CKB_1, differential clocks CK_2 and CKB_2 according to the differential high-speed clock under the selection of a mode selection signal; a variable capacitance circuit for generating different capacitance values to adjust the frequency division ratio in the frequency division; a single-stage differential frequency division circuit for realizing frequency division processing of the differential input clock at different frequency division ratios according to differential clocks CK_1 and CKB_1, differential clocks CK_2 and CKB_2 under the action of different capacitance values to generate a differential frequency division output clock; a clock shaping circuit for shaping the differential frequency division output clock, eliminating the high-frequency harmonics of the differential frequency division output clock, and obtaining a low-frequency differential frequency division output clock. The present invention can realize multi-mode frequency division without a multi-stage frequency divider.

Description

Single-stage multi-mode frequency divider based on variable capacitance

Technical Field

The invention belongs to the technical field of analog integrated circuit design, and particularly relates to a single-stage multi-mode frequency divider based on a variable capacitor.

Background

With the dramatic development of wireless communication technology and the continued advancement of semiconductor manufacturing processes, rf transceiver systems have achieved monolithic integration. In many core circuits of radio frequency transceivers, a phase-locked loop-based frequency synthesizer integrating high precision, high stability and low power consumption features becomes a key factor for determining the overall performance of a radio frequency system. A particular advantage of these frequency synthesizers is their flexible frequency hopping capability, allowing switching between different communication channels, which is achieved by precisely adjusting the division ratio of the divider.

A frequency Divider or a Multi-module Divider (MMD) may convert a high frequency signal into a low frequency signal at a certain ratio. Conventionally, a multi-mode frequency divider is designed with a fixed frequency dividing ratio, but in a practical application scenario, a higher requirement is put on the configurability of the frequency dividing ratio. In response to this need, a complex architecture is often employed in conventional divide ratio configurable divider designs, where the divider consists of a multi-stage fixed divide-by-two high speed prescaler, and a low speed digital programmable divider. The multi-stage high-speed prescaler only divides the frequency of the high-speed clock to generate a low-speed clock without the capability of adjusting the frequency division ratio, and the programmable frequency divider is formed by combining a large number of triggers and logic gates and generates feedback control signals through a complex digital logic circuit, thereby greatly increasing the design complexity, occupying a large amount of chip area and accompanying higher power consumption.

Therefore, the search for a more efficient, compact, and low-power-consumption design scheme of a multi-mode frequency divider is an important research direction in the current radio frequency technology field.

Disclosure of Invention

In order to solve the above problems in the prior art, the present invention provides a single-stage multi-mode frequency divider based on a variable capacitor. The technical problems to be solved by the invention are realized by the following technical scheme:

the embodiment of the invention provides a single-stage multi-mode frequency divider based on a variable capacitor, which comprises the following components:

The clock input circuit is used for generating differential high-speed clocks CK_N and CK_P with adjustable swing according to differential input clocks CK_IN_N and CK_IN_P;

a mode switching circuit for generating differential clocks CK_1 and CKB_1, and differential clocks CK_2 and CKB_2 according to the differential high-speed clocks CK_N and CK_P under the selection of a mode selection signal, wherein when the mode selection signal is 1, CK_1 and CK_2 are in the same phase to realize even frequency division, and when the mode selection signal is 0, CK_1 and CK_2 are in opposite phases to realize odd frequency division;

a variable capacitance circuit for generating different capacitance values to adjust a frequency division ratio in frequency division;

the single-stage differential frequency dividing circuit is used for realizing frequency dividing processing of differential input clocks CK_IN_N and CK_IN_P under different frequency dividing ratios according to differential clocks CK_1 and CKB_1 and differential clocks CK_2 and CKB_2 under the action of different capacitance values so as to generate differential frequency dividing output clocks DIV_N and DIV_P;

And the clock shaping circuit is used for shaping the differential frequency division output clocks DIV_N and DIV_P, eliminating high-frequency harmonic waves of the differential frequency division output clocks DIV_N and DIV_P, and obtaining low-frequency differential frequency division output clocks CK_DIV_N and CK_DIV_P.

In one embodiment of the invention, the clock input circuit comprises:

An impedance matching circuit for realizing impedance matching of the differential input clocks ck_in_n and ck_in_p;

the CML circuit is configured to generate differential high-speed clocks ck_n and ck_p with adjustable swing according to the differential input clocks ck_in_n and ck_in_p after impedance matching.

In one embodiment of the present invention, the mode switching circuit includes:

A first cross-coupled inverter for adjusting clock duty ratios of the differential high-speed clocks ck_n and ck_p;

A transmission gate for generating differential clocks CK '_1 and CKB' _1, and differential clocks CK '_2 and CKB' _2 according to the adjusted differential high-speed clocks CK_N and CK_P under the selection of a mode selection signal, wherein when the mode selection signal is 1, CK '_1 and CK' _2 are in the same phase to realize even frequency division, and when the mode selection signal is 0, CK '_1 and CK' _2 are in opposite phases to realize odd frequency division;

A second cross-coupled inverter for adjusting the clock duty cycles of the differential clocks CK '_1 and CKB' _1 to generate the differential clocks ck_1 and ckb_1;

and a third cross-coupled inverter for adjusting the clock duty cycle of the differential clocks CK '_2 and CKB' _2 to generate the differential clocks ck_2 and ckb_2.

In one embodiment of the present invention, the variable capacitance circuit includes:

The first variable capacitance subcircuit is used for receiving the frequency division signal at the first node in the single-stage differential frequency division circuit, changing the capacitance value of the first variable capacitance subcircuit under the action of the first capacitance value control signal, generating a new frequency division signal at the first node through the change of the capacitance value, and feeding back the frequency division signal at the new first node to the single-stage differential frequency division circuit;

And the second variable capacitance subcircuit is used for receiving the frequency division signal at the second node in the single-stage differential frequency division circuit, changing the capacitance value of the second variable capacitance subcircuit under the action of the second capacitance value control signal so as to generate a new frequency division signal at the second node through the change of the capacitance value, and feeding back the frequency division signal at the new second node to the single-stage differential frequency division circuit.

IN one embodiment of the present invention, the single-stage differential frequency dividing circuit is further configured to perform frequency division processing on differential input clocks ck_in_n and ck_in_p at different frequency division ratios according to differential clocks ck_1 and ckb_1, differential clocks ck_2 and ckb_2, and the frequency division signal at the first node and the frequency division signal at the second node, so as to generate differential frequency division output clocks div_n and div_p.

In one embodiment of the present invention, the single-stage differential frequency divider circuit includes transistors M1-M6, wherein,

The source of the transistor M1 and the source of the transistor M4 are both connected with the power supply VDD, the gate of the transistor M1 is connected with the output end of the differential clock CKB_1 in the mode switching circuit, the drain of the transistor M1 is connected with the drain of the transistor M2 and the gate of the transistor M5, the drain of the transistor M1 is used as the output end of the differential frequency division output clock DIV_N, the gate of the transistor M2 is connected with the drain of the transistor M4 and the drain of the transistor M5, the drain of the transistor M4 is used as the output end of the differential frequency division output clock DIV_P, the source of the transistor M2 is connected with the drain of the transistor M3 and the second variable capacitance subcircuit, the gate of the transistor M3 is connected with the output end of the differential clock CK_1 in the mode switching circuit, the source of the transistor M3 and the source of the transistor M6 are both connected with the power supply VSS, the gate of the transistor M4 is connected with the output end of the differential clock CKB_2 in the mode switching circuit, and the source of the transistor M5 is connected with the drain of the differential clock CKB_2 in the mode switching circuit.

In one embodiment of the invention, a first node in the single-stage differential frequency dividing circuit is at the source of the transistor M5, and a second node in the single-stage differential frequency dividing circuit is at the source of the transistor M2.

In one embodiment of the present invention, the transistors M1 and M4 are PMOS transistors, and the transistors M2, M3, M5 and M6 are NMOS transistors.

In one embodiment of the invention, the clock shaping circuit comprises:

The CML clock shaping circuit is used for adjusting the common mode level of the differential frequency division output clocks DIV_N and DIV_P, amplifying swing amplitude of the differential frequency division output clocks DIV_N and DIV_P so as to eliminate high-frequency harmonic waves of the differential frequency division output clocks DIV_N and DIV_P and obtain differential frequency division pre-output clocks DIV_OUT_N and DIV_OUT_P;

and the inverter driving circuit is used for enabling the differential frequency division pre-output clocks DIV_OUT_N and DIV_OUT_P to have driving capability, so as to obtain the low-frequency differential frequency division output clocks CK_DIV_N and CK_DIV_P.

The invention has the beneficial effects that:

The invention provides a single-stage multi-mode frequency divider based on a variable capacitor, which creatively provides a multi-mode frequency divider structure from the design of a circuit structure, specifically, an input clock swing is adjusted through a clock input circuit, and the size of a capacitance value of the variable capacitor is adjusted through a variable capacitor circuit, so that the high-speed clock can be directly subjected to multi-mode frequency division through the single-stage multi-mode frequency divider, and the high-speed clock is divided into a low-speed clock. In general, compared with the design scheme of the traditional frequency divider, the single-stage multi-mode frequency divider based on the variable capacitor provided by the embodiment of the invention is more efficient and compact, has the characteristics of high speed, adjustable single-stage frequency dividing ratio, low power consumption and high sensitivity, and can realize the multi-mode frequency dividing ratio without the need of the multi-stage frequency divider.

The present invention will be described in further detail with reference to the accompanying drawings and examples.

Drawings

Fig. 1 is a schematic diagram of a single-stage multi-mode frequency divider based on a variable capacitor according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of a specific circuit implementation of a clock input circuit in a single-stage multi-modulus divider based on variable capacitance according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of a specific circuit implementation of a mode switching circuit in a single-stage multi-mode divider based on a variable capacitance according to an embodiment of the present invention;

fig. 4 is a schematic diagram of a specific circuit implementation of a variable capacitance circuit in a single-stage multi-mode frequency divider based on a variable capacitance according to an embodiment of the present invention;

fig. 5 is a schematic diagram of a specific circuit implementation of a single-stage differential frequency divider circuit in a single-stage multi-mode frequency divider based on a variable capacitor according to an embodiment of the present invention;

fig. 6 is a schematic diagram of an implementation of an equivalent circuit based on fig. 4 and 5 according to an embodiment of the present invention;

FIGS. 7 (a) - (7 (b) are diagrams of simulation results of a single-stage multi-mode frequency divider based on variable capacitance in odd frequency division according to an embodiment of the present invention;

FIGS. 8 (a) - (8 (b) are simulation result diagrams of a single-stage multi-mode frequency divider based on variable capacitance according to an embodiment of the present invention during even frequency division;

Fig. 9 is a schematic diagram of a specific circuit implementation of a clock shaping circuit in a single-stage multi-modulus divider based on variable capacitance according to an embodiment of the present invention.

Detailed Description

The present invention will be described in further detail with reference to specific examples, but embodiments of the present invention are not limited thereto.

Referring to fig. 1, an embodiment of the present invention provides a single-stage multi-mode frequency divider based on a variable capacitor, the single-stage multi-mode frequency divider includes:

The clock input circuit is used for generating differential high-speed clocks CK_N and CK_P with adjustable swing according to differential input clocks CK_IN_N and CK_IN_P;

A mode switching circuit for generating differential clocks CK_1 and CKB_1, and differential clocks CK_2 and CKB_2 according to differential high-speed clocks CK_N and CK_P under the selection of a mode selection signal, wherein when the mode selection signal is 1, CK_1 and CK_2 are in the same phase to realize even frequency division, and when the mode selection signal is 0, CK_1 and CK_2 are in opposite phases to realize odd frequency division;

a variable capacitance circuit for generating different capacitance values to adjust a frequency division ratio in frequency division;

the single-stage differential frequency dividing circuit is used for realizing frequency dividing processing of differential input clocks CK_IN_N and CK_IN_P under different frequency dividing ratios according to differential clocks CK_1 and CKB_1 and differential clocks CK_2 and CKB_2 under the action of different capacitance values so as to generate differential frequency dividing output clocks DIV_N and DIV_P;

and the clock shaping circuit is used for shaping the differential frequency division output clocks DIV_N and DIV_P, eliminating high-frequency harmonic waves of the differential frequency division output clocks DIV_N and DIV_P, and obtaining low-frequency differential frequency division output clocks CK_DIV_N and CK_DIV_P.

Next, each section will be described.

Referring to fig. 2, a clock input circuit according to an embodiment of the invention includes:

The differential high-speed clock comprises an impedance matching circuit, a CML circuit and a differential high-speed clock, wherein the impedance matching circuit is used for realizing impedance matching of differential input clocks CK_IN_N and CK_IN_P, realizing impedance matching of the differential input clocks CK_IN_N and CK_IN_P by reasonably designing resistance values, and generating differential high-speed clocks CK_N and CK_P with adjustable swing according to the differential input clocks CK_IN_N and CK_IN_P after impedance matching. The impedance matching circuit and the CML circuit may be implemented by existing circuits that implement the above functions.

Therefore, the embodiment of the invention realizes impedance matching of the differential input clock through the clock input circuit and can adjust the clock swing.

Further, referring to fig. 3, in an embodiment of the present invention, the mode switching circuit includes:

The differential high-speed clock comprises a differential high-speed clock CK_N and a differential high-speed clock CK_P, a first cross-coupled inverter for adjusting the clock duty ratio of the differential high-speed clock CK_N and the clock duty ratio of the differential high-speed clock CK_P, a transmission gate for generating differential clocks CK_1 and CKB_1 and the differential clocks CK_2 and CKB_2 according to the adjusted differential high-speed clocks CK_N and CK_P under the selection of a mode selection signal MODEL_SEL, wherein when the mode selection signal is 1, the CK_1 and the CK_2 are in the same phase to realize even frequency division, when the mode selection signal is 0, the CK_1 and the CK_2 are in opposite phase to realize odd frequency division, a second cross-coupled inverter for adjusting the clock duty ratio of the differential clocks CK_1 and CKB_1 to generate differential clocks CK_1 and CKB_1, and a third cross-coupled inverter for generating differential clocks CK_2 and CKB_2 by adjusting the clock duty ratio of the differential clocks CK_2 and CKB_2. The first cross-coupled inverter, the second cross-coupled inverter, the third cross-coupled inverter and the transmission gate can be implemented by adopting the existing circuits for realizing the functions.

Therefore, the embodiment of the invention realizes the switching of the odd/even modes of the multi-mode frequency divider through the mode switching circuit.

Further, referring to fig. 4, in an embodiment of the present invention, a variable capacitance circuit includes:

The first variable capacitor sub-circuit is used for receiving the frequency division signal at a first node in the single-stage differential frequency division circuit, changing the capacitance value of the first variable capacitor sub-circuit under the action of a first capacitance value CONTROL signal C_CONTROL1 so as to generate a new frequency division signal at the first node through the change of the capacitance value and feed back the new frequency division signal at the first node to the single-stage differential frequency division circuit, and the second variable capacitor sub-circuit is used for receiving the frequency division signal at a second node in the single-stage differential frequency division circuit and changing the capacitance value of the second variable capacitor sub-circuit under the action of a second capacitance value CONTROL signal C_CONTROL2 so as to generate the new frequency division signal at the second node through the change of the capacitance value and feed back the new frequency division signal at the second node to the single-stage differential frequency division circuit. The first variable capacitance subcircuit and the second variable capacitance subcircuit can be realized by adopting the existing circuits for realizing the functions.

Therefore, the variable capacitance circuit of the embodiment of the invention receives the frequency division signals DIV_C1 and DIV_C2 from the node of the single-stage differential frequency division circuit and receives the multi-bit capacitance CONTROL signals C_CONTROL1 and C_CONTROL2, changes the capacitance value through the multi-bit capacitance CONTROL signals C_CONTROL1 and C_CONTROL2, and feeds back the influence caused by the change of the capacitance value to the single-stage differential frequency division circuit through the node frequency division signals DIV_C1 and DIV_C2, thereby achieving the purpose of changing the frequency division ratio of the frequency divider circuit.

Further, the single-stage differential frequency dividing circuit IN the embodiment of the present invention is further configured to implement frequency division processing on the differential input clocks ck_in_n and ck_in_p at different frequency division ratios according to the differential clocks ck_1 and ckb_1, the differential clocks ck_2 and ckb_2, the frequency division signal at the first node, and the frequency division signal at the second node, so as to generate the differential frequency division output clocks div_n and div_p.

Referring to fig. 5, the single-stage differential frequency dividing circuit in the embodiment of the invention includes a transistor M1-transistor M6, wherein the source of the transistor M1 and the source of the transistor M4 are both connected to the power supply VDD, the gate of the transistor M1 is connected to the output terminal of the differential clock ckb_1 in the mode switching circuit, the drain of the transistor M1 is connected to the drain of the transistor M2 and the gate of the transistor M5, the drain of the transistor M1 is used as the output terminal of the differential frequency division output clock div_n, the gate of the transistor M2 is connected to the drain of the transistor M4 and the drain of the transistor M5, the drain of the transistor M4 is used as the output terminal of the differential frequency division output clock div_p, the source of the transistor M2 is connected to the drain of the transistor M3, the source of the transistor M3 is connected to the output terminal of the differential clock ck_1 in the mode switching circuit, the source of the transistor M6 is connected to the drain of the differential clock ckb_2 in the mode switching circuit, and the drain of the transistor M6 is connected to the output terminal of the differential clock CK2 in the mode switching circuit. Therefore, the single-stage differential frequency dividing circuit of the embodiment of the invention receives the differential clock signals ckb_1, ck_1, ck_2, ckb_2 from the mode switching circuit, outputs the differential frequency dividing output clock div_ N, DIV _p to the clock shaping circuit after frequency division, and outputs the frequency dividing signals div_c1, div_c2 at the two nodes of the first node and the second node to the variable capacitance circuit.

In the embodiment of the invention, a first node in the single-stage differential frequency dividing circuit is a source electrode of a transistor M5, a second node in the single-stage differential frequency dividing circuit is a source electrode of a transistor M2, in the embodiment of the invention, the transistors M1 and M4 are PMOS transistors, and the transistors M2, M3, M5 and M6 are NMOS transistors.

As can be seen from fig. 4 and fig. 5, in the embodiment of the present invention, a capacitor is added between the left-path transistor M2 and the transistor M3 and between the right-path transistor M5 and the transistor M6, for example, the capacitor values at the node are respectively denoted by C1 and C2 as shown by 6, and the two-phase N (N is an integer and N is greater than or equal to 2) frequency division can be implemented, the greater the capacitor value, the greater the N, and the frequency division principle of the specific single-stage differential frequency division circuit is as follows:

Div_n is high, div_p is low, left transistor M2 is off, and right transistor M5 is on. If there is no charge stored in the right-side capacitor C1, (1) under the combined action of CK_2 and CKB_2, the transistor M6 and the transistor M4 are simultaneously in an on or off state. When the transistor M6 and the transistor M4 are simultaneously in the on state, the transistor M5 is also turned on under the control of div_n, charge is injected into the capacitor C1 while charge flows from the capacitor C1 to the ground through the transistor M6, and when the transistor M6 and the transistor M4 are simultaneously in the off state, the charge amount on the capacitor C1 remains unchanged. When ck_2 charges and discharges capacitor C1 in one period, i.e. the charge on capacitor C1 has a net accumulation in one ck_2 period, the node voltage will rise correspondingly. When the node voltage rises to some extent, it can be seen that capacitor C1 is full, at which point the circuit charges node DIV_P. The node DIV_P is relatively small and will be full in one clock cycle, and the node DIV_P goes high. When the capacitor C1 is relatively large, the capacitor C1 is not fully charged to raise the node voltage for one ck_2 period, the charging process is extended to N clock cycles, and the state of the node div_p at the low level is maintained for N clock cycles until the capacitor C1 is fully charged, and the node div_p rapidly becomes at the high level. (2) On the left hand side, div_p is low, no current will charge capacitor C2, and during N clock cycles, the charge of capacitor C2 will be completely discharged to ground, node div_n remains high while transistor M1 is periodically turned on. After the node div_p rapidly goes high to turn on the left-pass transistor M3, since the node capacitance at the node div_n is small, the stored charge is small and is rapidly released to the capacitor C2, so that the node voltage div_n rapidly drops to become low.

And then the left path goes through the charge and discharge process of the right path before the left path goes through the charge and discharge process of the left path, so that the respective output levels are turned over again. The above process is repeated to achieve divide-by-N of the clock. More specifically, the single-stage differential frequency dividing circuit realizes the odd-even frequency dividing principle that:

For odd frequency division, after DIV_N becomes high level, DIV_P becomes low level; after DIV_P goes high, DIV_N goes low. The time difference between the rising edges of div_n and div_p is half a period of the output signal. For odd-number frequency division, div_n will only go high during ckb_1 being low, div_p will only go high during ckb_2 being low, when ck_1 and ck_2 are opposite in phase, i.e., ckb_1 and ckb_2 are opposite in phase, ckb_1 and ckb_2 falling edges will only differ by 0.5t+kt (k=1, 2.), T represents the input clock period, and the output signal period is 2 x (0.5t+kt) = (2k+1) T, which is an odd multiple of the input clock period, to achieve odd-number frequency division. The inventor carries out simulation on a single-stage multi-mode frequency divider based on a variable capacitor, and the simulation results are shown in fig. 7 (a) to 7 (b), so that frequency division by 3 and frequency division by 5 are respectively realized.

For even frequency division, DIV_N becomes high, DIV_P becomes low, and DIV_N becomes low after DIV_P becomes high. The time difference between the rising edges of div_n and div_p is half a period of the output signal. For even-number frequency division, div_n will only change to high level during ckb_1 is low level, div_p will only change to high level during ckb_2 is low level, when ck_1 is identical to ck_2, i.e. ckb_1 is identical to ckb_2, and ckb_1 falling edge and ckb_2 falling edge only differ by KT (k=1, 2.), the output signal period is 2KT, which is an even multiple of the input clock period, and even-number frequency division is implemented. The inventor carries out simulation on a single-stage multi-mode frequency divider based on a variable capacitor, and the simulation results are shown in fig. 8 (a) to 8 (b), so that frequency division by 4 and frequency division by 6 are respectively realized.

Further, referring to fig. 9, in an embodiment of the present invention, a clock shaping circuit includes:

The CML clock shaping circuit is used for adjusting the common mode level of the differential frequency division output clocks DIV_N and DIV_P, amplifying swing amplitude of the differential frequency division output clocks DIV_N and DIV_P to eliminate high-frequency harmonic waves of the differential frequency division output clocks DIV_N and DIV_P, obtaining differential frequency division pre-output clocks DIV_OUT_N and DIV_OUT_P, and the inverter driving circuit is used for enabling the differential frequency division pre-output clocks DIV_OUT_N and DIV_OUT_P to have driving capability and obtaining low-frequency differential frequency division output clocks CK_DIV_N and CK_DIV_P. Finally, the low-frequency differential frequency-divided output clocks ck_div_n and ck_div_p are output to the post-stage circuit. The CML clock shaping circuit and the inverter driving circuit can be realized by adopting the existing circuits for realizing the functions.

In summary, the single-stage multi-mode frequency divider based on the variable capacitor provided by the embodiment of the invention creatively provides a multi-mode frequency divider structure from the design of a circuit structure, specifically, the amplitude of an input clock is adjusted through a clock input circuit, the capacitance value of the variable capacitor is adjusted through a variable capacitance circuit, the high-speed clock can be directly subjected to multi-mode frequency division through the single-stage multi-mode frequency divider, the high-speed clock is divided into a low-speed clock, compared with the traditional high-speed pre-frequency divider, the single-stage multi-mode frequency divider has the capability of adjusting the frequency division ratio, the number of stages of the programmable frequency divider can be greatly reduced, the design complexity is reduced, the chip area is reduced, the power consumption of the frequency divider is reduced, a mode selection signal can be input to a mode switching circuit according to actual requirements, and the single-stage multi-mode frequency division can be realized under the control of the mode switching circuit, so that the single-stage multi-mode frequency division can be realized in odd frequency division or even frequency division is realized more flexibly. In general, compared with the design scheme of the traditional frequency divider, the single-stage multi-mode frequency divider based on the variable capacitor provided by the embodiment of the invention is more efficient and compact, has the characteristics of high speed, adjustable single-stage frequency dividing ratio, low power consumption and high sensitivity, and can realize the multi-mode frequency dividing ratio without the need of the multi-stage frequency divider.

In the description of the present invention, it should be understood that the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present invention, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.

Although the invention is described herein in connection with various embodiments, other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the specification and the drawings. In the description, the word "comprising" does not exclude other elements or steps, and the "a" or "an" does not exclude a plurality. Some measures are described in mutually different embodiments, but this does not mean that these measures cannot be combined to produce a good effect.

The foregoing is a further detailed description of the invention in connection with the preferred embodiments, and it is not intended that the invention be limited to the specific embodiments described. It will be apparent to those skilled in the art that several simple deductions or substitutions may be made without departing from the spirit of the invention, and these should be considered to be within the scope of the invention.

Claims (9)

1. A single-stage multi-modulus divider based on a variable capacitance, the single-stage multi-modulus divider comprising:

The clock input circuit is used for generating differential high-speed clocks CK_N and CK_P with adjustable swing according to differential input clocks CK_IN_N and CK_IN_P;

a mode switching circuit for generating differential clocks CK_1 and CKB_1, and differential clocks CK_2 and CKB_2 according to the differential high-speed clocks CK_N and CK_P under the selection of a mode selection signal, wherein when the mode selection signal is 1, CK_1 and CK_2 are in the same phase to realize even frequency division, and when the mode selection signal is 0, CK_1 and CK_2 are in opposite phases to realize odd frequency division;

a variable capacitance circuit for generating different capacitance values to adjust a frequency division ratio in frequency division;

the single-stage differential frequency dividing circuit is used for realizing frequency dividing processing of differential input clocks CK_IN_N and CK_IN_P under different frequency dividing ratios according to differential clocks CK_1 and CKB_1 and differential clocks CK_2 and CKB_2 under the action of different capacitance values so as to generate differential frequency dividing output clocks DIV_N and DIV_P;

And the clock shaping circuit is used for shaping the differential frequency division output clocks DIV_N and DIV_P, eliminating high-frequency harmonic waves of the differential frequency division output clocks DIV_N and DIV_P, and obtaining low-frequency differential frequency division output clocks CK_DIV_N and CK_DIV_P.

2. The variable capacitance-based single-stage multi-modulus divider of claim 1, wherein the clock input circuit comprises:

An impedance matching circuit for realizing impedance matching of the differential input clocks ck_in_n and ck_in_p;

the CML circuit is configured to generate differential high-speed clocks ck_n and ck_p with adjustable swing according to the differential input clocks ck_in_n and ck_in_p after impedance matching.

3. The variable capacitance-based single-stage multi-modulus divider of claim 1, wherein the mode switching circuit comprises:

A first cross-coupled inverter for adjusting clock duty ratios of the differential high-speed clocks ck_n and ck_p;

A transmission gate for generating differential clocks CK '_1 and CKB' _1, and differential clocks CK '_2 and CKB' _2 according to the adjusted differential high-speed clocks CK_N and CK_P under the selection of a mode selection signal, wherein when the mode selection signal is 1, CK '_1 and CK' _2 are in the same phase to realize even frequency division, and when the mode selection signal is 0, CK '_1 and CK' _2 are in opposite phases to realize odd frequency division;

A second cross-coupled inverter for adjusting the clock duty cycles of the differential clocks CK '_1 and CKB' _1 to generate the differential clocks ck_1 and ckb_1;

and a third cross-coupled inverter for adjusting the clock duty cycle of the differential clocks CK '_2 and CKB' _2 to generate the differential clocks ck_2 and ckb_2.

4. The variable capacitance-based single-stage multi-modulus divider of claim 1, wherein the variable capacitance circuit comprises:

The first variable capacitance subcircuit is used for receiving the frequency division signal at the first node in the single-stage differential frequency division circuit, changing the capacitance value of the first variable capacitance subcircuit under the action of the first capacitance value control signal, generating a new frequency division signal at the first node through the change of the capacitance value, and feeding back the frequency division signal at the new first node to the single-stage differential frequency division circuit;

And the second variable capacitance subcircuit is used for receiving the frequency division signal at the second node in the single-stage differential frequency division circuit, changing the capacitance value of the second variable capacitance subcircuit under the action of the second capacitance value control signal so as to generate a new frequency division signal at the second node through the change of the capacitance value, and feeding back the frequency division signal at the new second node to the single-stage differential frequency division circuit.

5. The variable capacitance based single stage multi-modulus divider of claim 4 wherein the single stage differential divider circuit is further configured to perform a division process of differential input clocks ck_in_n and ck_in_p at different division ratios based on differential clocks ck_1 and ckb_1, differential clocks ck_2 and ckb_2, and the divided signal at the first node, the divided signal at the second node to generate differential divided output clocks div_n and div_p.

6. The variable capacitance-based single-stage multi-modulus divider according to claim 4, wherein the single-stage differential divider circuit comprises transistors M1-M6, wherein,

The source of the transistor M1 and the source of the transistor M4 are both connected with the power supply VDD, the gate of the transistor M1 is connected with the output end of the differential clock CKB_1 in the mode switching circuit, the drain of the transistor M1 is connected with the drain of the transistor M2 and the gate of the transistor M5, the drain of the transistor M1 is used as the output end of the differential frequency division output clock DIV_N, the gate of the transistor M2 is connected with the drain of the transistor M4 and the drain of the transistor M5, the drain of the transistor M4 is used as the output end of the differential frequency division output clock DIV_P, the source of the transistor M2 is connected with the drain of the transistor M3 and the second variable capacitance subcircuit, the gate of the transistor M3 is connected with the output end of the differential clock CK_1 in the mode switching circuit, the source of the transistor M3 and the source of the transistor M6 are both connected with the power supply VSS, the gate of the transistor M4 is connected with the output end of the differential clock CKB_2 in the mode switching circuit, and the source of the transistor M5 is connected with the drain of the differential clock CKB_2 in the mode switching circuit.

7. The variable capacitance-based single-stage multi-modulus divider of claim 6 wherein a first node of the single-stage differential divider circuit is at the source of transistor M5 and a second node of the single-stage differential divider circuit is at the source of transistor M2.

8. The variable capacitance-based single-stage multi-modulus divider according to claim 6, wherein transistor M1 and transistor M4 are PMOS transistors, and transistor M2, transistor M3, transistor M5, and transistor M6 are NMOS transistors.

9. The variable capacitance-based single-stage multi-modulus divider of claim 1, wherein the clock shaping circuit comprises:

The CML clock shaping circuit is used for adjusting the common mode level of the differential frequency division output clocks DIV_N and DIV_P, amplifying swing amplitude of the differential frequency division output clocks DIV_N and DIV_P so as to eliminate high-frequency harmonic waves of the differential frequency division output clocks DIV_N and DIV_P and obtain differential frequency division pre-output clocks DIV_OUT_N and DIV_OUT_P;

and the inverter driving circuit is used for enabling the differential frequency division pre-output clocks DIV_OUT_N and DIV_OUT_P to have driving capability, so as to obtain the low-frequency differential frequency division output clocks CK_DIV_N and CK_DIV_P.