CN120299545B - Method, apparatus, and medium for simulating wafer processing - Google Patents

Abstract

Embodiments of the present disclosure provide methods, apparatus, and media for simulating wafer processing. In the method, for a time instant in an electrochemical deposition process of a wafer, a target processing stage for the wafer at the time instant is determined from a plurality of processing stages of the electrochemical deposition process based on a deposition state of the wafer. Based on the feature information of the wafer and the process parameters related to the electrochemical deposition process, the target processing stage is simulated to determine a simulation result for the electrochemical deposition rate corresponding to the instant. A target parameter value for the process parameter is determined based on a plurality of simulation results determined for each of the plurality of time instants.

Description

Method, apparatus and medium for simulating wafer processing

Technical Field

Embodiments of the present disclosure relate generally to the field of integrated circuits and, more particularly, relate to methods, apparatus, and media for simulating wafer processing.

Background

Electrochemical deposition is a technique for facilitating deposition of substances from an electrolyte onto an electrode by applying an electric field to the surface of the electrode, and is widely used in the fields of microelectronics industry, material science, semiconductor manufacturing, and the like. Electrochemical deposition simulation plays an important role in wafer fabrication, and can improve the reliability, efficiency and cost effectiveness of the process. However, the current electrochemical deposition technology has some problems, which affect the deposition effect.

Disclosure of Invention

In a first aspect of the present disclosure, a method for simulating a wafer processing process is provided. In the method, a target processing stage to be performed on a chip at a time is determined from a plurality of processing stages of an electrochemical deposition process based on a deposition state of the chip for the time in the electrochemical deposition process of the chip, the target processing stage is simulated based on feature structure information of the chip and process parameters related to the electrochemical deposition process to determine a simulation result for an electrochemical deposition rate corresponding to the time, and target parameter values for the process parameters are determined based on a plurality of simulation results determined for the respective times.

In some embodiments, the target processing stage includes a trench fill stage and a trench overcharging stage, and simulating the target processing stage includes:

For a target area among a plurality of areas of the chip,

Determining a time evolution factor aiming at the technological parameter based on the characteristic structure information corresponding to the target area at the moment, wherein the time evolution factor indicates the influence of the moment before the moment on the moment;

Determining a parameter value of the process parameter at a previous moment based on the time evolution factor, the correction coefficient for the process parameter and the parameter value of the process parameter at the previous moment;

simulating the target processing stage based on the parameter values of the process parameters at that time to obtain a region simulation result for the electrochemical deposition rate of the target region, and

Based on the plurality of region simulation results determined for the plurality of regions, respectively, a simulation result corresponding to the time is determined.

In a second aspect of the present disclosure, an electronic device is provided. The electronic device includes a processor, and a memory coupled to the processor. The memory has instructions stored therein that, when executed by the processor, cause the electronic device to perform a method according to the first aspect of the present disclosure.

In a third aspect of the present disclosure, a computer-readable storage medium is provided. The computer readable storage medium has a computer program stored thereon. The computer program, when executed by a processor, implements a method according to the first aspect of the present disclosure.

As will be appreciated from the following description, according to embodiments of the present disclosure, a processing stage to be performed on a chip at each time is determined based on a deposition state of the chip. The corresponding processing stages are then simulated based on the feature information and process parameters of the chip. Thereby, the accuracy of the simulation of the respective processing stage is improved. In addition, a target parameter value of the process parameter is determined based on each simulation result, and the accuracy of the determined process parameter is improved. Further, electrochemical deposition of the chip using the determined target parameter values of the process parameters may allow for quality of the chip. Other benefits will be described below in connection with the corresponding embodiments.

It should be understood that what is described in this summary is not intended to limit the critical or essential features of the embodiments of the disclosure nor to limit the scope of the disclosure. Other features of the present disclosure will become apparent from the following description.

Drawings

The above and other features, advantages and aspects of embodiments of the present disclosure will become more apparent by reference to the following detailed description when taken in conjunction with the accompanying drawings. In the drawings, wherein like or similar reference numerals designate like or similar elements, and wherein:

FIG. 1 illustrates a schematic diagram of an example environment in which embodiments of the present disclosure can be implemented;

FIG. 2 illustrates a flow chart for a simulated chip process according to some embodiments of the present disclosure;

FIG. 3 illustrates a schematic diagram of an electrochemical deposition surface topography, according to some embodiments of the present disclosure;

FIG. 4 illustrates a schematic diagram of an example architecture of a plurality of simulation models, in accordance with some embodiments of the present disclosure;

FIG. 5A illustrates a flowchart of a process for determining correction coefficients for a process parameter, according to some embodiments of the present disclosure;

FIG. 5B illustrates another flow chart of a process for determining correction coefficients for a process parameter according to some embodiments of the present disclosure;

FIG. 5C illustrates yet another flow chart of a process for determining correction coefficients for a process parameter in accordance with some embodiments of the present disclosure;

FIG. 6 illustrates another flow chart for emulating a chip processing procedure in accordance with some embodiments of the present disclosure, and

Fig. 7 illustrates a block diagram of a server or electronic device in which one or more embodiments of the disclosure may be implemented.

Detailed Description

Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While certain embodiments of the present disclosure have been shown in the accompanying drawings, it is to be understood that the present disclosure may be embodied in various forms and should not be construed as limited to the embodiments set forth herein, but are provided to provide a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are for illustration purposes only and are not intended to limit the scope of the present disclosure.

In describing embodiments of the present disclosure, the term "comprising" and its like should be taken to be open-ended, i.e., including, but not limited to. The term "based on" should be understood as "based at least in part on". The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment". The terms "first," "second," and the like, may refer to different or the same object. Other explicit and implicit definitions are also possible below.

FIG. 1 illustrates a schematic diagram of an example environment 100 in which embodiments of the present disclosure can be implemented. The example environment 100 may generally include an electronic device 110. The electronic device 110 may be used to simulate a wafer processing process. For example, the electronic device 110 may be used to generate the wafer processing model 120 or update the wafer processing model 120. In this context, the wafer processing process may be an electrochemical deposition process. The wafer processing model 120 may be used to simulate or simulate an electrochemical deposition process. The wafer processing model 120 may be initialized in any manner. For example, the wafer processing model 120 may simulate an electrochemical deposition process for a target wafer 130 to be processed to obtain a (simulated) processed target wafer 132. In some embodiments, a wafer may include a plurality of dies, and processing a wafer using the wafer processing model 120 may include processing a die on the wafer using the wafer processing model 120.

In some embodiments, the electronic device 110 may generate or update the wafer processing model 120 based on a set of metrology parameter information (e.g., metrology parameter information 102-1, 102-2.) and a set of simulation parameter information (e.g., simulation parameter information 104-1, 104-2.). Generating or updating the wafer processing model 120 refers to determining or updating various parameters of the wafer processing model 120. The set of metrology parameter information may be channel height and non-channel height obtained by performing an actual process on the target wafer, such as an electrochemical deposition process followed by a measurement of the topography of the processed target wafer. The set of simulation parameter information may be parameter information of a simulated processed wafer obtained by simulating processing of a target wafer using the wafer processing model 120.

In some embodiments, the electronic device 110 may be communicatively connected to a wafer processing platform, such as an electrochemical deposition platform. The electronic device 110 may also be communicatively connected to one or more sensors at various locations on or adjacent to the wafer processing platform. The wafer processing platform may physically process the wafer and transmit a set of metrology parameter information to the electronic device 110.

In some embodiments, the electronic device 110 may also be communicatively connected to and control the electrochemical deposition platform to process (e.g., package) the wafer. The electronics control the electrochemical deposition stage to perform a polishing operation on the surface of the target wafer 130 to effect wafer processing. The electrochemical deposition operation may include more than one deposition phase. By way of example, the plurality of deposition phases may include a trench fill phase, a trench overcharging phase, and a horizontal fill phase.

The electronics 110 can determine process parameter values for a final wafer processing platform, such as an electrochemical deposition platform, based on the obtained or updated process parameter values for the wafer processing model 120. These process parameter values may include values of various process parameters for multiple stages of electrochemical deposition.

In the example environment 100, the electronic device 110 may be any type of device having computing capabilities, including a terminal device or a server device. The terminal device may be any type of mobile terminal, fixed terminal, or portable terminal, including a mobile handset, desktop computer, laptop computer, notebook computer, netbook computer, tablet computer, media computer, multimedia tablet, personal Communication System (PCS) device, personal navigation device, personal Digital Assistant (PDA), audio/video player, digital camera/camcorder, positioning device, television receiver, radio broadcast receiver, electronic book device, game device, or any combination of the preceding, including accessories and peripherals for these devices, or any combination thereof. The server devices may include, for example, computing systems/servers, such as mainframes, edge computing nodes, computing devices in a cloud environment, and so forth.

It should be understood that the structure and function of environment 100 are described for illustrative purposes only and are not meant to suggest any limitation as to the scope of the disclosure. Example embodiments according to the present disclosure will be described in detail below with reference to the accompanying drawings.

As mentioned briefly above, electrochemical deposition technology is a core technology in the semiconductor manufacturing and microelectronics industries, where the accuracy of process parameters directly determines the performance and reliability of the chip. In the electrochemical deposition process, the high aspect ratio of the channel region at the chip is easy to cause problems such as void filling, uneven electric field distribution, uneven additive (e.g., inhibitor or accelerator) distribution, and the like, thereby influencing the quality of the chip after the electrochemical deposition treatment. In order to further improve the quality of the chip, simulation and defect detection of the electrochemical deposition process are required.

The current simulation mode for the electrochemical deposition simulation mainly comprises numerical simulation, level set function simulation and semi-empirical physical formula simulation. The numerical simulation and the level set function simulation have lower simulation efficiency, and are difficult to complete in effective time in the face of full-chip scale and complex structure simulation. The semi-empirical physical formula simulation has the prediction capability of the full-chip chemical deposition surface morphology, but has lower calculation accuracy. Therefore, how to simulate the chip processing process more accurately is a problem that needs to be solved by those skilled in the art.

To this end, embodiments of the present disclosure provide a method of layout processing to solve or at least partially solve the above-described problems and/or other potential problems in conventional approaches. According to embodiments of the present disclosure, for a time instant of a plurality of time instants in an electrochemical deposition process of a chip, a target processing stage for the time instant to be performed on the chip is determined from a plurality of processing stages of the electrochemical deposition process based on a deposition state of the chip. Based on the feature information of the chip and the process parameters related to the electrochemical deposition process, the target processing stage is simulated to determine a simulation result for the electrochemical deposition rate corresponding to the instant. A target parameter value for the process parameter is determined based on a plurality of simulation results determined for each of the plurality of time instants.

In this way, the stage of processing to be performed on the chip at each instant is determined based on the deposition state of the chip. The corresponding processing stages are then simulated based on the feature information and process parameters of the chip. Thereby, the accuracy of the simulation of the respective processing stage is improved. In addition, a target parameter value of the process parameter is determined based on each simulation result, and the accuracy of the determined process parameter is improved. And carrying out electrochemical deposition on the chip by utilizing the determined target parameter value of the process parameter. In this way, the quality of the chip can be improved in view of the determined process parameters being more accurate.

Example embodiments of the present disclosure are described in detail below with continued reference to the drawings.

In some embodiments, during electrochemical deposition for a chip, the electronic device 110 may simulate the deposition process for the chip using the chip handling model 120 to obtain simulation results for the topography of the chip. For example, for each of a plurality of moments in the electrochemical deposition process of the chip, the electronic device 110 may determine a simulation result for the electrochemical deposition rate at each moment, and thus the topography of the chip, through the chip processing model.

In some embodiments, the process of electrochemical deposition for a chip may be divided into multiple stages based on the effect of the electrochemical deposition. For example, the electrochemical deposition process may include at least one of a trench fill phase, a trench overcharging phase, or a horizontal fill phase. In the trench filling stage, the trench region on the chip is filled by using an electrochemical deposition technology, so that the trench is completely filled with metal. During the channel overcharging phase, an additional layer of technology is deposited over the channel using electrochemical deposition techniques to facilitate protection of the filled structure within the channel during subsequent processing (e.g., chemical mechanical polishing processes). In the horizontal filling stage, an electrochemical deposition technology is utilized to deposit on the non-channel region and the filled channel region so as to form a uniform horizontal layer on the surface of the chip, and the flatness and the electrical performance of the device are further improved.

In some embodiments, at the end of each deposition phase, the electronic device 110 may determine the phase that needs to be performed subsequently based on the deposition effect and process requirements for that deposition phase. Illustratively, at the end of the channel fill phase, if the presence of voids in the channel region is detected, the channel overcharging phase is entered. Otherwise, the horizontal filling phase is entered.

FIG. 2 illustrates a flow chart for a simulated chip process 200 according to some embodiments of the present disclosure. As shown in fig. 2, process 200 may be implemented or included at electronic device 110. It should be understood that process 200 may also include additional blocks not shown and/or may omit certain block(s) shown, the scope of the present disclosure not being limited in this respect.

In some embodiments, the process parameters corresponding to the different filling stages are not the same. In order to more accurately simulate the deposition state of the chip, different filling stages can be simulated by using different simulation models. In some embodiments, the target processing stage includes a trench fill stage and a trench overcharging stage, and simulating the target processing stage includes determining, for a target region of the plurality of regions of the chip, a time evolution factor for the process parameter based on feature information corresponding to the target region at the time, the time evolution factor indicating an effect of a time instant preceding the time instant on the time instant. The parameter value of the process parameter at the time instant is determined based on the time evolution factor, the correction factor for the process parameter and the parameter value of the process parameter at the previous time instant. Based on the parameter value of the process parameter at the moment, the target processing stage is simulated to obtain a region simulation result of the electrochemical deposition rate for the target region. Based on the plurality of region simulation results determined for the plurality of regions, respectively, a simulation result corresponding to the time is determined.

As shown in fig. 2, at block 210, during electrochemical deposition for a wafer, electronic device 110 may first obtain a deposition state of target die 130 to be processed. The deposition state indicates the deposition effect of the channel region on the chip. Fig. 3 illustrates a schematic diagram of an electrochemical deposition surface topography 300, according to some embodiments of the present disclosure. As shown in fig. 3, the chip includes a channel region 311 and a non-channel region 312. During the deposition process, metal ions are deposited at the bottom 314 of the channel region 311, the sidewalls 313 of the channel region 311, and the non-channel region 312. By way of example, the deposition state may include a channel region bottom deposition thickness, a channel region sidewall deposition thickness, a non-channel region fill thickness, and the like. During the deposition process, the processing stage corresponding to the current time may be determined based on the deposition state of the chip. For example, if the channel region sidewall deposition thickness is below the first deposition thickness threshold, then this indicates that the current stage is in the channel fill stage. If the channel region sidewall deposition thickness exceeds the first deposition thickness threshold and the non-channel region deposition thickness is below the second deposition thickness threshold, then the current stage is indicated to be in a channel overcharging stage.

In some embodiments, the electronic device 110 may simulate the target processing stage based on the feature information of the chip and the process parameters related to the electrochemical deposition process to determine a simulation result for the electrochemical deposition rate corresponding to the instant. The feature information of a chip may refer to any suitable information representing or describing the feature of the chip. The feature structure of a chip may refer to a structure of a target type or a structure of a type of interest in the chip. Features may include, but are not limited to, communication in a chip. For example, the feature information of the chip may include the on-chip channel density (i.e., the area fraction of the channel region), the perimeter of the channel region, the number of channels, the channel width, and the channel sidewall deposition thickness, among others. The process parameters may include parameters related to process conditions or tool settings such as deposition time, deposition rate, accelerator initial coverage, inhibitor initial coverage, and the like.

In some embodiments, to more accurately simulate the electrochemical deposition process of the chip, different simulation models may be used to simulate different stages of the electrochemical deposition process. FIG. 4 illustrates a schematic diagram of an example architecture 400 of multiple simulation models, according to some embodiments of the present disclosure. As shown in FIG. 4, a first simulation model 440-1 for simulating the channel fill phase 410, a second simulation model 440-2 for simulating the channel overcharging phase 420, and a third simulation model 440-3 for simulating the horizontal fill phase 430, which may be referred to individually or collectively as simulation models 440, may be included in the architecture 400. In some embodiments, the simulation model 440 may be a semi-empirical physical model that characterizes the relationship between the process parameters for electrochemical deposition of the chip and the feature information of the chip to describe different wire distributions resulting in different morphologies on the chip after electrochemical deposition.

If it is determined that the current processing stage performed on the channel is a channel filling stage, the electronic device 110 may simulate the channel overcharging state based on the feature structure information to obtain a plurality of first simulation results in block 220. For example, the electronic device 110 may simulate the target processing stage based on the feature information of the chip and the process parameters related to the electrochemical deposition process using the first simulation model 440-1. In some embodiments, electronic device 110 may grid the chip based on layout information of the chip to determine a plurality of regions related to the chip.

For a target region in a plurality of regions of the chip, determining a time evolution factor for the process parameter based on feature structure information corresponding to the target region at the moment, wherein the time evolution factor indicates the influence of the moment before the moment on the moment. At time t, the channel perimeter corresponding to the target region may be determined by:

(1)

Wherein, the For the channel perimeter of the target region at the initial instant,For the perimeter of the target area at time t,And N is the number of grooves of the target region for the thickness of the side wall of the target region at the time t.

The channel density corresponding to the target region may be determined by:

(2)

Wherein the method comprises the steps of For the channel density of the target region at time t,For the channel density of the target region at the initial instant,Is the area of the target area.

In some embodiments, the promoter coverage and the inhibitor coverage at the current time may be determined based on the promoter initial coverage, the inhibitor initial coverage, and the feature information, thereby determining the metal ion deposition rate at the current time.

In the trench fill phase and the trench overcharging phase, the accelerator coverage and the inhibitor coverage may be determined by:

(3)

(4)

Wherein the method comprises the steps of 、Indicating the coverage of the accelerator and retarder next time at the channel bottom, channel sidewall and non-trench regions,、Indicating the coverage of the accelerator and retarder at the bottom of the channel, the channel sidewall and the non-trench region at the present moment,The parameters (i.e., correction factors) may be optimized for dimensionless,Coverage at the initial time for the accelerator.To optimize the coefficients (i.e., correction coefficients),As a time evolution factor, it can be determined by:

(5)

Wherein the deposition rate at time t is ,For the initial deposition rate,For the initial coverage of the inhibitor,K is a coefficient for the accelerator initial coverage.

In the method for calculating the coverage rate of the accelerator shown in the formula (3), the time evolution factor may be a coverage rate coefficient. As shown in equation (5), the electronic device 110 may determine an initial value of the time evolution factor based on the initial feature structure of the target region. For example, the initial feature may include an initial channel density, an initial perimeter of the channel region, an initial number of channels, an initial channel width, and the like. Subsequently, the electronic device 110 may determine a value of the time evolution factor at the time instant based on the initial value and at least one region simulation result corresponding to at least one previous time instant of the time instant, respectively. In some embodiments, the region simulation results may include simulation results of deposition thickness (or deposition rate) for the channel region (e.g., deposition thickness of the channel sidewall, deposition thickness of the channel bottom) and also may include simulation results of deposition thickness for the non-channel region. As shown in the above equations (1) and (2), in the channel filling stage, the time evolution factor may be determined based on the difference between the initial value and the at least one region simulation result. Exemplary, for a certain point in the deposition process, the simulation results corresponding to that point include at least the channel sidewall deposition thickness. From the above equation (5), it is known that the channel circumference is based on this timeChannel densityAnd the channel perimeter channel density at the previous instant may determine the time evolution factor corresponding to that instant. The channel perimeter at this time is shown in equation (1)May be determined based on the sum of the initial channel perimeter and the area simulation results (e.g., channel sidewall deposition thickness) at that time. The channel density at this time is shown in the formula (2)Can be determined based on the sum of the initial channel density and the area simulation results (e.g., channel sidewall deposition thickness) at that time.

At block 230, the electronic device 110 determines whether the channel is filled. If the filling is complete, block 240 is entered where the channel overcharging state is simulated based on the feature information to obtain a plurality of second simulation results. In the channel overcharging stage, the thickness of metal ions in the channel is larger than that of a non-channel region, and the deposition state of the metal ions is changed. The time evolution factor may be determined by:

(6)

(7)

as shown in equation (6) and equation (7), the time evolution factor may be determined based on the sum of the initial value and the at least one region simulation result. The channel perimeter at this time is shown in equation (6) May be determined based on the sum of the initial channel perimeter and the area simulation results (e.g., channel sidewall deposition thickness) at that time. The channel density at this time is shown in the formula (7)Can be determined based on the sum of the initial channel density and the area simulation results (e.g., channel sidewall deposition thickness) at that time.

In some embodiments, the time evolution factors corresponding to the channel sidewalls and the channel bottom are not the same. For example, the time evolution factor may include a first time evolution factor corresponding to a channel sidewall of the target region or a second time evolution factor corresponding to a channel bottom of the target region. In some embodiments, the first time evolution factor may be 1 and the second time evolution factor may be as shown in equation (5). In this case, the accelerator coverage at the bottom of the channel can be determined by:

(8)

Wherein the method comprises the steps of The coverage rate of the accelerator at the bottom of the channel at the time t+1,The coverage rate of the accelerator at the bottom of the channel at time t.

In some embodiments, the electronic device 110 may determine the parameter value of the process parameter at the time instant (e.g., the parameter value of the accelerator coverage at the time instant or the parameter value of the inhibitor coverage at the time instant, etc.) based on the time evolution factor and the correction factor for the process parameter and the parameter value of the process parameter at the previous time instant. Then, based on the parameter values of the process parameters at that time, the target processing stage is simulated to obtain a region simulation result for the electrochemical deposition rate of the target region. In some embodiments, the region simulation result may be the deposition rate of the region at the current time, e.g., the electrochemical deposition rate at time t. The region simulation result may be the deposition thickness in the region at the current time. The deposition thickness of the target area may be determined by:

(9)

Wherein the method comprises the steps of For the thickness of the deposit at the previous moment,Is the deposition thickness at the current time.

In some embodiments, the electronic device 110 may determine a simulation result corresponding to the time based on a plurality of region simulation results determined for a plurality of regions, respectively. In some embodiments, the determined simulation result may be an average deposition rate for each region on the chip at the current time, or an average deposition thickness for each region on the chip at the current time.

In some embodiments, the target processing stage may include a horizontal fill stage. At block 250, the electronic device 110 determines whether the channel is overcharged. If the overcharging is complete, block 260 is entered. At block 260, the horizontal fill state is simulated based on the feature structure information to obtain a plurality of third simulation results. For a target region of the plurality of regions of the chip, the electronic device 110 may determine a region simulation result for the target region corresponding to a time when a previous stage of the horizontal filling stage ends, based on the region simulation result for the target region and the correction coefficient for the process parameter. Based on the plurality of region simulation results determined for the plurality of regions, respectively, a simulation result corresponding to the time is determined. The region simulation results for the target region may be determined by:

(10)

Wherein the method comprises the steps of Is the metal ion deposition rate corresponding to the end of the previous stage (e.g., channel overcharging stage) of the horizontal fill stage.For the end of the previous phase of the horizontal filling phase,Is a dimensionless correction coefficient.

In some embodiments, the electronic device 110 determines the target parameter value of the process parameter based on a plurality of simulation results determined for a plurality of time instants, respectively. The target parameter value is a process parameter value for the actual production of the chip. The electronic device 110 may determine a topography simulation result for the chip based on the plurality of simulation results. By way of example, the topography simulation results may include simulation results of deposition thickness for non-channel regions on the chip and simulation results of deposition thickness for channel regions on the chip. Subsequently, the electronics 110 can update the process parameters to determine target parameter values based on differences between the topography simulation results and the topography reference results, including the trench reference heights and the non-trench reference heights. The topography reference results may include channel design height and non-channel design height of the chip, or measured height for channel region and non-channel region of the chip, etc. In some embodiments, the target parameter values for the process parameters may be determined based on empirical models, or determined using other machine learning models, without limitation.

In the above embodiment, the simulation models 440 are used to simulate the electrochemical deposition process and update the process parameters of the chip based on the simulation result, so as to improve the quality of the chip in the production process. As described above, there are some correction coefficients in formulas (1) to (10), and in order to further improve the accuracy of the simulation model 440, the correction coefficients may be optimized.

Fig. 5A illustrates a flowchart of a process 500A for determining correction coefficients for a process parameter, according to some embodiments of the present disclosure. As shown in fig. 5A, at block 510, the electronic device 110 first obtains a plurality of training feature information associated with a chip. Each training feature information in the plurality of training feature information may be for a certain chip or a certain area to be processed in the chip.

In some embodiments, the electronic device 110 may define optimization objectives and constraints according to the simulation model 440 to be optimized. The optimal target is the deposition thickness of metal ions in the channel region and the non-channel region in the training characteristic structure information. The constraint condition is the value range of each correction coefficient to be optimized. Each parameter is adjusted in a predefined search space to bring the objective function to an optimal value.

At block 511, the electronic device 110 generates a first set of parameters based on the initial values of the correction coefficients. The parameter set in the first set of parameters includes respective coefficient values of a plurality of correction coefficients. For a certain area to be processed in the chip, a set of initial populations (i.e. a first set of parameters) is randomly generated, i.e. a combination of all correction coefficients to be optimized. The initial population acquisition mode includes, but is not limited to, a full-orthogonal method, a field-mouth experimental method, a response surface method, a random method and the like. The population number can be set according to parameters which are optimized according to specific needs, and the more parameters which are required to be optimized, the more the population number is. It should be noted that the initial value of each parameter is within the search space of the parameter.

At block 512, the electronic device 110 performs a combining operation and a mutation operation on the parameter sets in the first set of parameters using a genetic algorithm to generate a second set of parameter sets. Fig. 5B illustrates another flowchart of a process 500B for determining correction coefficients for process parameters, according to some embodiments of the present disclosure. As shown in fig. 5B, at block 520, electronic device 110 may simulate each parameter combination in the first set of parameter sets (i.e., each parameter set) to determine training simulation results corresponding to the respective parameter set. At block 521, for each parameter combination (i.e., each parameter set in the second set of parameters), the electronic device 110 may determine a fitness based on the difference between the training simulation result and the reference simulation result using an objective function. The value of the fitness is related to the true solution that the objective function needs to achieve, in this example specifically the deposited thickness of the metal ions in the channel region and the non-channel region after the electrochemical deposition process. For each parameter set, the electronic device 110 may determine a root mean square error of a measured value (i.e., a reference value of the electrochemical deposition profile of the chip) and a simulated value (i.e., a simulation result of the electrochemical deposition profile of the chip) corresponding to the parameter set to determine a fitness corresponding to the parameter set. The smaller the root mean square error, the greater the fitness of the parameter set.

At block 522, the electronic device 110 may determine an excellent individual based on the plurality of fitness determined for the plurality of training simulation results. In the process of optimizing the correction coefficient, an individual refers to one parameter set in a group of parameter sets, and an excellent individual is a parameter set in which the fitness of a plurality of parameter sets exceeds a fitness threshold. Methods of selecting superior individuals include, but are not limited to, roulette selections, tournament selections, and the like. The optimal individuals are obtained from the current population based on the above method in order to generate a new second set of parameter sets. In some embodiments, electronic device 110 may perform individual crossing based on the selected excellent individual to generate a new individual. The crossover operation is to take out part of the parameters from the two individuals and combine them, thereby generating a new solution. This process may explore new regions of solution space. Meanwhile, parameter random fluctuation (i.e., mutation operation) is performed for excellent individuals in order to increase the diversity of the solution space, and the mutation operation helps to avoid sinking into a locally optimal solution.

At block 523, electronic device 110 may determine whether the number of population iterations of the genetic algorithm exceeds a first threshold number. If the first threshold number is not exceeded, then execution continues with the steps shown above in blocks 520 through 523. At block 524, if the electronic device 110 determines that the number of iterations of the population exceeds the first threshold number, a globally superior individual is obtained.

At block 513, the electronic device 110 obtains a globally superior individual. At block 514, the electronic device 110 optimizes the correction factors using a Monte Carlo search tree algorithm. Fig. 5C illustrates yet another flow chart of a process 500C for determining correction coefficients for a process parameter according to some embodiments of the present disclosure. Illustratively, after several iterations of the genetic algorithm, at block 530, the electronic device 110 may select multiple sets of optima (or preferred parameter combinations) as starting nodes for the Monte Carlo search Tree algorithm. Subsequently, at block 531, the electronic device 110 may use the monte carlo search tree algorithm to expand the tree starting from the current solution. The Monte Carlo search tree algorithm evaluates the quality of the solution by modeling future possible parameter combination configurations. Each tree node represents a combination of parameters and the child nodes represent the possible next best solutions. At block 532, the electronic device 110 may perform a Monte Carlo simulation at each tree node. In the simulation process, the quality of the node is estimated according to the root mean square difference between the thickness and the measured value, which is estimated by the estimation target, and the expected value of each node is retrospectively updated according to the simulation result. At block 533, through continuous simulation and backtracking, the electronic device 110 may expand and select the optimal path through a Monte Carlo search tree algorithm. At block 534, the electronic device 110 may obtain a locally preferred individual based on the selected optimal path.

At block 515, the electronic device 110 may obtain locally preferred individuals to determine a third set of parameters.

At block 516, the electronic device 110 may determine whether the coefficient values in the second set of parameters are less than a root mean square difference threshold. If the root mean square difference threshold is less than the root mean square difference threshold, the coefficient value of the correction coefficient is updated, otherwise the process of updating the correction coefficient using the genetic algorithm and the Monte Carlo search tree algorithm described above (i.e., the steps shown in blocks 512 through 516) continues. In some embodiments, the alternating optimization of the genetic algorithm and the Monte Carlo search tree algorithm is performed by repeating. And obtaining a global optimal solution by utilizing the characteristics of global search by crossing and mutation of a genetic algorithm, and obtaining a local optimal solution by combining the characteristics of local refinement optimization of each candidate solution by a Monte Carlo search tree algorithm. And finally, the optimal parameter combination is found through multi-generation evolution. The optimization termination condition can stop optimization by setting the iteration times or the root mean square difference threshold value and the like, and a group of optimal solutions corresponding to the objective function are obtained.

At block 517, the electronic device 110 may update the coefficient values of the correction coefficients based on the coefficient values in the third set of parameters.

In some embodiments, the above-described manner of alternating optimization of the genetic algorithm and the Monte Carlo search tree algorithm may also be used to determine target parameter values for the process parameters based on a plurality of simulation results. For example, the electronic device 110 may determine an initial population for the genetic algorithm based on the initial values of the process parameters. Subsequently, the electronic device 110 obtains a plurality of candidate solutions by performing a crossover operation or a mutation operation on the individuals in the initial population. Subsequently, the electronic device 110 performs local refinement optimization on each candidate solution in combination with the monte carlo search tree algorithm, and obtains a local optimal solution. And finally, through multi-generation evolution, finding out the optimal target parameter value for determining the process parameter.

Fig. 6 illustrates another flow diagram for a simulated chip process 600 according to some embodiments of the present disclosure. As shown in fig. 6, process 600 may be implemented at electronic device 110. Process 600 is described below with reference to fig. 1.

As shown in fig. 6, at block 610, the electronic device 110 determines a target processing stage for the chip at a time instant in an electrochemical deposition process of the chip from a plurality of processing stages of the electrochemical deposition process based on a deposition state of the chip.

At block 620, the electronic device 110 simulates a target processing stage based on the feature information of the chip and process parameters related to the electrochemical deposition process to determine a simulation result for the electrochemical deposition rate corresponding to the time.

In some embodiments, the target processing stage includes a trench fill stage and a trench overcharging stage, and simulating the target processing stage includes determining, for a target region of a plurality of regions of the chip, a time evolution factor for a process parameter based on feature structure information corresponding to the target region at the time, the time evolution factor indicating an effect of a time immediately preceding the time on the time, determining a parameter value for the process parameter at the time based on the time evolution factor, a correction coefficient for the process parameter, and a parameter value for the process parameter at the time immediately preceding, simulating the target processing stage based on the parameter value for the process parameter at the time to obtain a region simulation result for an electrochemical deposition rate for the target region, and determining a simulation result corresponding to the time based on the plurality of region simulation results determined for the plurality of regions, respectively.

In some embodiments, determining the time evolution factor of the target region includes determining an initial value of the time evolution factor based on an initial feature of the target region and determining a value of the time evolution factor at the time based on the initial value and at least one region simulation result corresponding respectively to at least one previous time of the time.

In some embodiments, determining the parameter value of the time evolution factor at the instant is based on at least one of a sum of the initial value and the at least one region simulation result, or a difference between the initial value and the at least one region simulation result.

In some embodiments, the time evolution factor comprises at least one of a first time evolution factor corresponding to a channel sidewall of the target region or a second time evolution factor corresponding to a channel bottom of the target region.

In some embodiments, the target processing stage includes a horizontal fill stage and simulating the target processing stage includes determining, for a target region of a plurality of regions of the chip, a region simulation result for the target region corresponding to a time instant at which a previous stage of the horizontal fill stage ended based on the region simulation result for the target region and a correction coefficient for the process parameter, and determining a simulation result corresponding to the time instant based on the plurality of region simulation results determined for the plurality of regions, respectively.

At block 630, the electronic device 110 determines target parameter values for the process parameters based on the plurality of simulation results determined for each of the plurality of time instants.

In some embodiments, determining the target parameter value of the process parameter includes determining a topography simulation result for the chip based on the plurality of simulation results, the topography simulation result including a trench simulation height and a non-trench simulation height, and updating the process parameter to determine the target parameter value based on a difference between the topography simulation result and a topography reference result, the topography reference result including a trench reference height and a non-trench reference height.

In some embodiments, the correction coefficients for the process parameters used in the simulation are determined by generating a first set of parameter sets based on initial values of the correction coefficients, the parameter sets in the first set of parameter sets including coefficient values of the correction coefficients, generating a second set of parameter sets by a combination operation and a variation operation of the coefficient values of the correction coefficients in the first set of parameter sets, and updating the coefficient values of the correction coefficients based on the coefficient values in each of the second set of parameter sets until the number of updates exceeds a threshold number.

In some embodiments, updating the coefficient values of the correction coefficients includes determining a plurality of training simulation results based on the second set of parameters, the training simulation results of the plurality of training simulation results including simulation values of an electrochemical deposition profile of the chip, determining respective qualities of the parameter values in the second set of parameters based on differences between the plurality of training simulation results and respective reference simulation results, the reference simulation results including reference values of the electrochemical deposition profile of the chip, updating the coefficient values in the second set of parameters using a Monte Carlo search tree algorithm based on the qualities to determine a third set of parameter sets, and updating the coefficient values of the correction coefficients based on the coefficient values in the third set of parameter sets.

Fig. 7 illustrates a block diagram of a server or electronic device 700 in which one or more embodiments of the disclosure may be implemented. The electronic device 700 may be used, for example, to implement the electronic device 110 shown in fig. 1. It should be understood that the electronic device 700 illustrated in fig. 7 is merely exemplary and should not be construed as limiting the functionality and scope of the embodiments described herein.

As shown in fig. 7, the electronic device 700 is in the form of a general-purpose electronic device. Components of electronic device 700 may include, but are not limited to, one or more processors 710 or processing units, memory 720, storage 730, one or more communication units 740, one or more input devices 750, and one or more output devices 760. The processing unit may be an actual or virtual processor and is capable of performing various processes according to programs stored in the memory 720. In a multiprocessor system, multiple processing units execute computer-executable instructions in parallel to improve the parallel processing capabilities of electronic device 700.

Electronic device 700 typically includes a number of computer storage media. Such a medium may be any available medium that is accessible by electronic device 700, including, but not limited to, volatile and non-volatile media, removable and non-removable media. The memory 720 may be volatile memory (e.g., registers, cache, random Access Memory (RAM)), non-volatile memory (e.g., read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory), or some combination thereof. Storage device 730 may be a removable or non-removable media and may include machine-readable media such as flash drives, magnetic disks, or any other media that may be capable of storing information and/or data (e.g., training data for training) and may be accessed within electronic device 700.

The electronic device 700 may further include additional removable/non-removable, volatile/nonvolatile storage media. Although not shown in fig. 7, a magnetic disk drive for reading from or writing to a removable, nonvolatile magnetic disk (e.g., a "floppy disk") and an optical disk drive for reading from or writing to a removable, nonvolatile optical disk may be provided. In these cases, each drive may be connected to a bus (not shown) by one or more data medium interfaces. Memory 720 may include a computer program product 725 having one or more program modules configured to perform the various methods or acts of the various embodiments of the disclosure.

The communication unit 740 enables communication with other electronic devices through a communication medium. Additionally, the functionality of the components of the electronic device 700 may be implemented in a single computing cluster or in multiple computing machines capable of communicating over a communication connection. Thus, the electronic device 700 may operate in a networked environment using logical connections to one or more other servers, a network Personal Computer (PC), or another network node.

The input device 750 may be one or more input devices such as a mouse, keyboard, trackball, etc. The output device 760 may be one or more output devices such as a display, speakers, printer, etc. The electronic device 700 may also communicate with one or more external devices (not shown), such as storage devices, display devices, etc., through the communication unit 740, with one or more devices that enable a user to interact with the electronic device 700, or with any device (e.g., network card, modem, etc.) that enables the electronic device 700 to communicate with one or more other electronic devices, as desired. Such communication may be performed via an input/output (I/O) interface (not shown).

According to an exemplary implementation of the present disclosure, a computer-readable storage medium is provided, on which one or more computer instructions are stored, wherein the one or more computer instructions are executed by a processor to implement the method described above.

Various aspects of the present disclosure are described herein with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to the disclosure. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer-readable program instructions.

These computer readable program instructions may be provided to a processing unit of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processing unit of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks. These computer readable program instructions may also be stored in a computer readable storage medium that can direct a computer, programmable data processing apparatus, and/or other devices to function in a particular manner, such that the computer readable medium having the instructions stored therein includes an article of manufacture including instructions which implement the function/act specified in the flowchart and/or block diagram block or blocks.

The computer readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other devices to cause a series of operational steps to be performed on the computer, other programmable apparatus or other devices to produce a computer implemented process such that the instructions which execute on the computer, other programmable apparatus or other devices implement the functions/acts specified in the flowchart and/or block diagram block or blocks.

The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various implementations of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

The foregoing description of implementations of the present disclosure has been provided for illustrative purposes, is not exhaustive, and is not limited to the implementations disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the various implementations described. The terminology used herein was chosen in order to best explain the principles of each implementation, the practical application, or the improvement of technology in the marketplace, or to enable others of ordinary skill in the art to understand each implementation disclosed herein.

Claims (11)

1. A method for simulating a wafer processing process, comprising:

for the moment of the electrochemical deposition process of the chip,

Determining a target processing stage to be performed on the chip at the time from a plurality of processing stages of the electrochemical deposition process based on a deposition state of the chip, the plurality of processing stages being divided based on an effect of electrochemical deposition, the plurality of processing stages corresponding to different simulation models;

Simulating the target processing stage with a simulation model corresponding to the target processing stage based on the feature information of the chip and the process parameters related to the electrochemical deposition process to determine a simulation result for the electrochemical deposition rate corresponding to the instant in time, and

A target parameter value of the process parameter is determined based on a plurality of simulation results determined for a plurality of the time instants, respectively.

2. The method of claim 1, wherein the target processing stage comprises a trench fill stage and a trench overcharging stage, and simulating the target processing stage with a simulation model corresponding to the target processing stage comprises:

For a target area of a plurality of areas of the chip,

Determining a time evolution factor for the process parameter based on the feature structure information corresponding to the target area at the moment, wherein the time evolution factor indicates the influence of the moment before the moment on the moment;

determining a parameter value of the process parameter at the previous moment based on the time evolution factor, a correction coefficient for the process parameter and the parameter value of the process parameter at the previous moment;

Simulating the target processing stage based on the parameter value of the process parameter at the moment to obtain a region simulation result of the electrochemical deposition rate for the target region, and

And determining a simulation result corresponding to the moment based on the simulation results of the plurality of areas determined for the plurality of areas respectively.

3. The method of claim 2, wherein determining the temporal evolution factor of the target region comprises:

determining an initial value of the time evolution factor based on an initial feature structure of the target area;

And determining the value of the time evolution factor at the moment based on the initial value and at least one region simulation result respectively corresponding to at least one previous moment of the moment.

4. A method according to claim 3, characterized in that the determination of the parameter value of the time evolution factor at the instant is based on at least one of the following:

the sum of the initial value and the at least one region simulation result, or

A difference between the initial value and the at least one region simulation result.

5. The method of claim 2, wherein the time evolution factor comprises at least one of:

a first time evolution factor corresponding to the channel sidewall of the target region, or

And a second time evolution factor corresponding to the bottom of the channel of the target region.

6. The method of claim 1, wherein the target processing stage comprises a horizontal fill stage, and simulating the target processing stage with a simulation model corresponding to the target processing stage comprises:

determining, for a target region of a plurality of regions of the chip, a region simulation result corresponding to a time instant for which a previous stage of the horizontal filling stage ends, based on a region simulation result corresponding to the time instant for the target region and a correction coefficient for the process parameter, and

And determining a simulation result corresponding to the moment based on the simulation results of the plurality of areas determined for the plurality of areas respectively.

7. The method of claim 1, wherein determining a target parameter value for the process parameter comprises:

determining a topography simulation result for the chip based on the plurality of simulation results, the topography simulation result including a trench simulation height and a non-trench simulation height, and

The process parameters are updated to determine the target parameter values based on differences between the topography simulation results and topography reference results, including trench reference heights and non-trench reference heights.

8. The method according to claim 1, characterized in that the correction coefficients for the process parameters used in the simulation are determined by:

generating a first set of parameter sets based on the initial value of the correction coefficient, the parameter sets in the first set of parameter sets comprising coefficient values of the correction coefficient;

Generating a second set of parameters by combining and mutating coefficient values of the correction coefficients in the first set of parameters, and

Updating the coefficient values of the correction coefficients based on the coefficient values in each of the second set of parameters until the number of updates exceeds a threshold number.

9. The method of claim 8, wherein updating coefficient values of the correction coefficients comprises:

Determining a plurality of training simulation results based on the second set of parameter sets, wherein the training simulation results in the plurality of training simulation results comprise simulation values of electrochemical deposition morphology of the chip;

Determining respective qualities of parameter values in the second set of parameters based on differences between the plurality of training simulation results and respective reference simulation results, the reference simulation results comprising reference values of electrochemical deposition morphology of the chip;

Updating coefficient values in the second set of parameters using a Monte Carlo search tree algorithm based on the quality to determine a third set of parameters, and

Updating the coefficient values of the correction coefficients based on the coefficient values in the third set of parameters.

10. An electronic device, comprising:

at least one processing unit, and

At least one memory coupled to the at least one processing unit and storing instructions for execution by the at least one processing unit, which when executed by the at least one processing unit, cause the electronic device to perform the method of any one of claims 1 to 9.

11. A computer readable storage medium, having stored thereon a computer program, characterized in that the computer program is executable by a processor to implement the method according to any of claims 1 to 9.