CN120317210A - A wafer-level chip simulation method, device, equipment and storage medium - Google Patents
A wafer-level chip simulation method, device, equipment and storage mediumInfo
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Abstract
本发明实施例公开了一种晶圆级芯片仿真方法、装置、设备和存储介质，方法包括：基于多个目标进程解析预设仿真命令行，确定预设仿真命令行对应的晶圆级芯片仿真任务；基于目标进程中的主进程对晶圆级芯片仿真任务进行拆分，得到多个芯片仿真子任务；将多个芯片仿真子任务分发给多个目标进程，以使目标进程基于对应的多个线程并行处理芯片仿真子任务，得到预设仿真命令行对应的目标仿真结果。本发明实施例的技术方案解决了现有技术中无法针对晶圆级芯片进行仿真模拟的问题，可以基于多个目标进程并行处理晶圆级芯片仿真任务，在满足模拟仿真精度需求下提升模拟仿真速度，支持大规模晶圆级芯片模拟仿真，满足晶圆级芯片开发环境设计与验证的需求。
The embodiment of the present invention discloses a wafer-level chip simulation method, device, equipment and storage medium, the method comprising: parsing a preset simulation command line based on multiple target processes to determine the wafer-level chip simulation task corresponding to the preset simulation command line; splitting the wafer-level chip simulation task based on the main process in the target process to obtain multiple chip simulation subtasks; distributing the multiple chip simulation subtasks to multiple target processes, so that the target process processes the chip simulation subtasks in parallel based on the corresponding multiple threads to obtain the target simulation result corresponding to the preset simulation command line. The technical solution of the embodiment of the present invention solves the problem that wafer-level chips cannot be simulated in the prior art, and wafer-level chip simulation tasks can be processed in parallel based on multiple target processes, and the simulation speed can be improved while meeting the simulation accuracy requirements, supporting large-scale wafer-level chip simulation, and meeting the requirements of wafer-level chip development environment design and verification.
Description
Technical Field
The embodiment of the invention relates to the technical field of simulation, in particular to a wafer-level chip simulation method, a device, equipment and a storage medium.
Background
The wafer-level chip integrates heterogeneous resources with different functions and mixed granularity, and different tasks and different moments can show high dynamic characteristics of service. The system on the chip is integrated with various prefabricated members on the wafer, besides the traditional CPU, FPGA, DSP, GPU, NPU and other heterogeneous computing units can be integrated, and besides, network resources and interface resources on the wafer are more efficient and dynamically reconfigurable than traditional architectures. In order to realize efficient utilization of various heterogeneous resources, a wafer-level chip base software stack is required to carry out resource unified virtualization, information acquisition and resource management on hardware resources. Because the wafer-level chip integrates a plurality of heterogeneous computing resources, and adopts a software definable technology to interconnect the resources, the network structure can be dynamically recombined according to task changes, a larger optimization space is provided for the comprehensive optimization design of the wafer-level chip, but the wafer-level chip is limited by technology, power consumption, area and the like, and problems to be solved in the design process are numerous, and the problems are mutually interwoven and mutually influenced.
The simulation object of the existing tool and technology is a single chip under a specific process, not a wafer-level chip, and although the HeteroGarnet module of Gem5 can simulate the interconnection between simulation chips, the simulation object cannot accurately model the interconnection of the substrate, and cannot support the accurate simulation of a large-scale (more than or equal to 100 chips) wafer-level chip.
Disclosure of Invention
The technical scheme of the embodiment of the invention solves the problem that the effective simulation of the wafer-level chip cannot be performed in the prior art, can process the wafer-level chip simulation task in parallel based on a plurality of target processes, improves the simulation speed under the condition of meeting the simulation precision requirement, supports the large-scale wafer-level chip simulation, and meets the requirement of designing and verifying the wafer-level chip system-level development environment.
In a first aspect, an embodiment of the present invention provides a wafer level chip simulation method, where the method includes:
analyzing a preset simulation command line based on a plurality of target processes, determining a wafer-level chip simulation task corresponding to the preset simulation command line, splitting the wafer-level chip simulation task based on a main process in the target processes to obtain a plurality of chip simulation subtasks, and distributing the plurality of chip simulation subtasks to the plurality of target processes so that the target processes process the chip simulation subtasks in parallel based on a plurality of corresponding threads to obtain a target simulation result corresponding to the preset simulation command line.
In a second aspect, an embodiment of the present invention provides a wafer-level chip simulation apparatus, including:
The system comprises a command line analysis module, a simulation task splitting module and a simulation task execution module, wherein the command line analysis module is used for analyzing a preset simulation command line based on a plurality of target processes to determine a wafer-level chip simulation task corresponding to the preset simulation command line, the simulation task splitting module is used for splitting the wafer-level chip simulation task based on a main process in the target processes to obtain a plurality of chip simulation subtasks, and the simulation task execution module is used for distributing the plurality of chip simulation subtasks to a plurality of target processes so that the target processes can process the chip simulation subtasks in parallel based on a plurality of corresponding threads to obtain a target simulation result corresponding to the preset simulation command line.
In a third aspect, an embodiment of the present invention provides a computer apparatus, including:
one or more processors;
A memory for storing one or more programs;
The one or more programs, when executed by the one or more processors, cause the one or more processors to implement the wafer level chip emulation method of any of the embodiments.
In a fourth aspect, an embodiment of the present invention provides a computer readable storage medium having stored thereon a computer program, which when executed by a processor implements the wafer level chip emulation method of any embodiment.
According to the technical scheme provided by the embodiment of the invention, the wafer-level chip simulation task corresponding to the preset simulation command line is determined by analyzing the preset simulation command line based on a plurality of target processes, the wafer-level chip simulation task is split based on a main process in the target processes to obtain a plurality of chip simulation subtasks, and the plurality of chip simulation subtasks are distributed to the plurality of target processes so that the target processes can process the chip simulation subtasks in parallel based on the corresponding plurality of threads to obtain a target simulation result corresponding to the preset simulation command line. The technical scheme of the embodiment of the invention solves the problem that the effective simulation cannot be carried out on the wafer-level chip in the prior art, can process the wafer-level chip simulation task in parallel based on a plurality of target processes, improves the simulation speed under the condition of meeting the requirement of simulation precision, supports the large-scale wafer-level chip simulation and meets the requirement of designing and verifying the wafer-level chip system-level development environment.
Drawings
FIG. 1 is a flow chart of a wafer level chip simulation method provided by an embodiment of the invention;
FIG. 2 is a flowchart of another wafer level chip simulation method provided by an embodiment of the present invention;
FIG. 3 is a flowchart illustrating a wafer level chip simulation process according to an embodiment of the present invention;
FIG. 4 is a workflow diagram of a process executing a chip emulation task provided by an embodiment of the present invention;
FIG. 5 is a workflow diagram provided by an embodiment of the present invention for registering a new component with a configuration file;
FIG. 6 is a schematic diagram of a wafer level chip simulation apparatus according to an embodiment of the present invention;
Fig. 7 is a schematic structural diagram of a computer device according to an embodiment of the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Fig. 1 is a flowchart of a wafer level chip simulation method provided by an embodiment of the present invention, where the embodiment of the present invention is applicable to a scenario in which a wafer level chip is simulated, the method may be performed by a wafer level chip simulation apparatus, and the apparatus may be implemented by software and/or hardware.
As shown in fig. 1, the wafer-level chip simulation method includes the following steps:
S110, analyzing a preset simulation command line based on a plurality of target processes, and determining a wafer-level chip simulation task corresponding to the preset simulation command line.
The target process may be a process for performing wafer-level chip simulation tasks, among other things. The preset simulation command line may be a command line for recording the content of the chip simulation task. Specifically, the preset simulation command line may be set manually. The wafer-level chip simulation task may be a specific simulation task corresponding to a preset simulation command line. The wafer-level chip can be subjected to simulation test based on the wafer-level chip simulation task to obtain a corresponding simulation test result. Alternatively, the multiple target processes may all parse the preset simulation command line, so that the target processes are aware of the overall simulation task.
S120, splitting the wafer-level chip simulation task based on a main process in the target process to obtain a plurality of chip simulation subtasks.
The main process may be a process for performing simulation task allocation. Specifically, the main process may be one process of the target processes, and the main process may be set by a person. The chip simulation subtask may be a chip simulation task that the target process needs to execute. Specifically, the main process splits the wafer-level chip simulation task to obtain chip simulation subtasks corresponding to each target process. Alternatively, the number of chip simulation subtasks may be the same as the number of target processes, so that each target process obtains a corresponding chip simulation subtask.
And S130, distributing the chip simulation subtasks to a plurality of target processes, so that the target processes process the chip simulation subtasks in parallel based on a plurality of corresponding threads to obtain a target simulation result corresponding to the preset simulation command line.
The target simulation result may be a simulation test result corresponding to a wafer level chip simulation task. Specifically, the multiple chip simulation subtasks may be distributed to multiple target processes, so that the target processes process the chip simulation subtasks in parallel based on the corresponding multiple threads, and the simulation test results of all the target processes are summarized, so as to obtain a target simulation result.
According to the technical scheme provided by the embodiment of the invention, the wafer-level chip simulation task corresponding to the preset simulation command line is determined by analyzing the preset simulation command line based on a plurality of target processes, the wafer-level chip simulation task is split based on a main process in the target processes to obtain a plurality of chip simulation subtasks, and the plurality of chip simulation subtasks are distributed to the plurality of target processes so that the target processes can process the chip simulation subtasks in parallel based on the corresponding plurality of threads to obtain a target simulation result corresponding to the preset simulation command line. The technical scheme of the embodiment of the invention solves the problem that the effective simulation cannot be carried out on the wafer-level chip in the prior art, can process the wafer-level chip simulation task in parallel based on a plurality of target processes, improves the simulation speed under the condition of meeting the requirement of simulation precision, supports the large-scale wafer-level chip simulation and meets the requirement of designing and verifying the wafer-level chip system-level development environment.
Fig. 2 is a flowchart of another wafer level chip simulation method provided by the embodiment of the present invention, where the embodiment of the present invention is applicable to a scenario in which a wafer level chip is simulated, and based on the above embodiment, how to split the wafer level chip simulation task based on a main process in the target process to obtain multiple chip simulation subtasks, and how to enable the target process to process the chip simulation subtasks in parallel based on multiple corresponding threads to obtain a target simulation result corresponding to the preset simulation command line.
As shown in fig. 2, the wafer-level chip simulation method includes the following steps:
S210, analyzing a preset simulation command line based on a plurality of target processes, and determining a wafer-level chip simulation task corresponding to the preset simulation command line.
The target process may be a process for performing wafer-level chip simulation tasks, among other things. The preset simulation command line may be a command line for recording the content of the chip simulation task. Specifically, the preset simulation command line may be set manually. The wafer-level chip simulation task may be a specific simulation task corresponding to a preset simulation command line. The wafer-level chip can be subjected to simulation test based on the wafer-level chip simulation task to obtain a corresponding simulation test result. Alternatively, the multiple target processes may all parse the preset simulation command line, so that the target processes are aware of the overall simulation task.
S220, under the condition that the target configuration file corresponding to the preset simulation command line exists, the main process determines a target configuration diagram according to the target configuration file and the wafer-level chip simulation task.
The target configuration file may be a file related to configuration parameters and initial settings corresponding to the wafer level chip simulation task. The master process may be a process for performing simulation task allocation. Specifically, the main process may be one process of the target processes, and the main process may be set by a person. The target configuration diagram is used for representing link information between components to be used corresponding to the chip simulation subtask. Wherein, a process can comprise a plurality of threads, and the process and the threads can comprise a certain number of components, and the components can be used for executing simulation tasks. The components to be used may be components that need to be used in wafer-level chip simulation tasks. The link information may include a connection relationship between the components and a communication delay time for communication between the components.
Optionally, the main process determines the target configuration diagram according to the target configuration file and the wafer-level chip simulation task, and comprises the steps of obtaining a preset simulation configuration model, and determining the target configuration diagram according to the preset simulation configuration model, the target configuration file and the wafer-level chip simulation task.
The preset simulation configuration model is used for representing internal configuration information of a preset component and link information between the preset component and other preset components, and the preset component comprises at least one of a processor component, a memory component and a network component. The preset simulation configuration model may be understood as a template regarding connection relationships between preset components and other components. Specifically, each preset component may have its corresponding preset simulation configuration model. The preset simulation configuration model may be entered by human. For example, the preset simulation configuration model can be stored in the prefabricated member, a user can insert the corresponding prefabricated member into the system according to the requirement, flexible integration of various calculation cores can be supported, plug and play of various prefabricated members is realized, and reasonable compromise between simulation scale and simulation precision is realized. Furthermore, components to be used in the simulation test can be determined according to the target configuration file and the wafer-level chip simulation task, and then the components to be used are connected based on a preset simulation configuration model corresponding to the components to be used, so that a target configuration diagram is obtained.
Optionally, the main process may further determine a process communication path according to the target configuration diagram, and send the process communication path to the target process executing the chip emulation subtask. Wherein the process communication path is used to represent the communication path with the smallest communication delay between the target processes. Specifically, the main process may plan a path for communication between the target processes with the minimum communication delay time according to the communication delay time between the components to be used in the target configuration diagram, and take the path as a process communication path. By determining the process communication path, when the target process subsequently executes the chip simulation task, communication between the target processes can be performed based on the process communication path, and the communication rate is improved.
Optionally, under the condition that the component to be used corresponding to the preset simulation command line is found to be absent, determining a custom component according to the compiling interaction instruction, and registering the name of the custom component and the dynamic library path into the target configuration file.
Under the condition that the to-be-used component to be started in the preset command line does not exist, a user can compile the custom component by the interaction command, take the compiled custom component as the to-be-used component, register the name of the custom component and the dynamic library path into the target configuration file, and then run the related component in the database according to the component path and the component name in the target configuration file.
S230, splitting the target configuration diagram to obtain a plurality of partition diagrams, and determining the chip simulation subtask according to the partition diagrams.
Wherein the partition map may be a portion of an image in the target configuration map. Specifically, the target configuration diagram may be split according to the number of components in the target configuration diagram and the number of target processes, so as to obtain a plurality of partition diagrams. For example, the components in the target configuration graph may be split equally according to the number of target processes, so as to ensure that the number of components in each split partition graph is the same, and each target process corresponds to one partition graph.
The chip simulation subtask may be a chip simulation task that the target process needs to execute. Specifically, for each process, a chip simulation subtask required to be executed by each process can be determined according to the partition map. Further, each chip emulation subtask can be distributed to a corresponding target process. It should be noted here that the multiple target processes may not execute corresponding chip emulation subtasks in parallel. That is, when each target process executes the corresponding chip simulation subtask, there may be a corresponding sequence and execution delay time. The specific execution sequence and execution delay time can be determined according to a preset simulation command line.
S240, distributing the chip simulation subtasks to a plurality of target processes, and executing the chip simulation subtasks in parallel based on a plurality of threads corresponding to the target processes aiming at each target process to obtain a sub-simulation result corresponding to the target process.
The sub-simulation result may be a simulation test result of the target thread executing the chip simulation sub-task. Specifically, the target process may execute the chip simulation subtasks in parallel based on the corresponding multiple threads, and then determine the sub-simulation result corresponding to the target process according to the simulation test results of the multiple threads.
Optionally, executing the chip simulation subtask in parallel based on a plurality of threads corresponding to the target process to obtain a subtask corresponding to the target process, wherein the method comprises the steps of splitting the chip simulation subtask by the main thread in the target process to obtain a plurality of chip simulation subtasks, distributing the plurality of chip simulation subtasks to the plurality of target threads in the target process, enabling the plurality of target threads to execute the distributed chip simulation subtask in parallel, and determining the subtask corresponding to the target process according to the simulation results of the plurality of target threads.
The main thread may be a thread for performing simulation task allocation. Specifically, the main thread may be selected from threads belonging to the target process, and the specific main process may be set manually. The target thread may be a thread in the target process that needs to perform an emulation test task. The chip emulation subtask may be a chip emulation task that the target thread needs to execute. Specifically, the chip simulation subtasks can be split according to the number of components in the chip simulation subtasks and the number of target threads, so that a plurality of chip simulation subtasks are obtained. For example, the components in the chip simulation subtasks can be split equally according to the number of the target threads, so that the same number of the split components in each chip simulation subtask is ensured, and each target thread corresponds to one chip simulation subtask.
Further, the multiple chip simulation subtasks can be distributed to the corresponding target threads respectively, then the multiple target threads execute the distributed chip simulation subtasks in parallel, finally the simulation test results of the multiple target threads are combined, and further sub-simulation results corresponding to the target processes are obtained.
Optionally, the main thread may further determine a thread communication path according to the partition map in the chip emulation subtask, and send the thread communication path to a target thread executing the chip emulation subtask, where the thread communication path is used to represent a communication path with a minimum communication delay between the target threads. Specifically, the main thread may plan a path for communication between the target threads according to the communication delay time between the components in the partition map, and take the path as a thread communication path. By determining the thread communication path, the target threads can communicate with each other based on the thread communication path when the chip simulation task is executed, and the communication rate is improved.
S250, unifying formats of sub-simulation results of a plurality of target processes, and determining the target simulation results.
The target simulation result may be a simulation test result corresponding to a wafer level chip simulation task. Specifically, the sub-simulation results of the multiple target processes can be unified according to a preset format, all the sub-simulation results with the unified format are used as target simulation results, and the sub-simulation results with the unified format can be combined to obtain target simulation results.
For better understanding of the technical solution provided by the present invention, a description of a specific embodiment is provided below, and fig. 3 is a flowchart of a process for performing wafer-level chip simulation according to an embodiment of the present invention. As shown in fig. 3, the workflow for performing wafer-level chip simulation includes the steps of:
(1) All processes parse the command line.
(2) Check if a configuration file exists.
(3) A factory is created for loading definitions of external models.
(4) Creating a configuration diagram:
(a) The global memory space size for each thread is obtained. And acquiring the maximum memory usage in all parallel processes, and broadcasting the result back to all processes.
(B) A configuration map is created. Parsing and executing the python input configuration file to obtain component names, connection information, messaging size, etc.
(C) The thread number is set. And setting the thread number according to the parameters of the command line.
(D) A global output object is created. Creating and initializing a global output object, setting file names, process numbers, thread numbers, and setting standard output as the global output object.
(E) The total number of components is calculated. The total number of components used in the configuration file, processor, memory, network, etc., is calculated.
(5) And decomposing the parallel simulation tasks. Reasonable grouping is carried out on the components in the configuration file, total weight is calculated, link information is optimized, connection fields related to the components are updated, and a partition map is constructed.
(6) The smallest partition is calculated. The shortest delay path across rank communications is found in a parallel simulation by analyzing the components and link information in the simulation model.
(7) The graph information is broadcast to all processes. By splitting and distributing the different parts of the graph it is ensured that all ranks can efficiently perform their tasks. And a certain rank overload is avoided, and the uniform allocation of resources is ensured.
(8) An analog simulator is created.
FIG. 4 is a workflow diagram of a process executing a chip emulation task provided by an embodiment of the present invention. As shown in fig. 4, the workflow of the process for executing the chip emulation task includes the following steps:
(1) Local data is initialized.
(2) A thread setting signal other than 0 thread (main process).
(3) An analog simulation object is created.
(4) The graph information is processed. Information of all components and links is extracted from the current partition map, and the minimum communication delay path between different threads is determined.
(5) All simulated simulation components are created. According to the component structure configuration information, a computing core component, a memory component, a network component and the like are added into a dynamic library, global parameter verification is carried out on the components, connection operation between the components is carried out, and a communication pipeline is arranged.
(6) The analog simulator is initialized.
(7) Simulation setting is simulated. Traversing all registered component information mappings, invoking the setup () method of each component in turn, configuring and preparing the individual components to enter a simulated run state.
(8) Ready to run.
(9) And running simulation.
(10) And (5) ending the simulation.
FIG. 5 is a workflow diagram of registering a new component with a configuration file provided by an embodiment of the present invention. As shown in fig. 5, the workflow of registering components includes the steps of:
Under the condition that the to-be-used component to be started in the preset command line does not exist, a user can compile to obtain a custom component, register the name of the custom component and the dynamic library path to the target environment configuration file, and then run the database to find out related components according to the component path and the component name in the target configuration file.
The technical scheme provided by the embodiment of the invention comprises the steps of analyzing a preset simulation command line based on a plurality of target processes, determining a wafer-level chip simulation task corresponding to the preset simulation command line, determining a target configuration diagram by the main process according to the target configuration file and the wafer-level chip simulation task when the target configuration file corresponding to the preset simulation command line exists, splitting the target configuration diagram to obtain a plurality of partition diagrams, determining a chip simulation subtask according to the partition diagrams, distributing the plurality of chip simulation subtasks to a plurality of target processes, executing the chip simulation subtask in parallel based on a plurality of threads corresponding to the target processes for each target process to obtain a sub-simulation result corresponding to the target process, unifying formats of the sub-simulation results of the plurality of target processes, and determining the target simulation result. The technical scheme of the embodiment of the invention solves the problem that the effective simulation cannot be carried out on the wafer-level chip in the prior art, can process the wafer-level chip simulation task in parallel based on a plurality of target processes, improves the simulation speed under the condition of meeting the requirement of simulation precision, supports the large-scale wafer-level chip simulation and meets the requirement of designing and verifying the wafer-level chip system-level development environment.
Fig. 6 is a schematic structural diagram of a wafer level chip simulation device according to an embodiment of the present invention, where the embodiment of the present invention is applicable to a scenario in which a wafer level chip is simulated, and the device may be implemented in software and/or hardware, and integrated into a computer device having an application development function.
As shown in fig. 6, the wafer level chip simulation apparatus includes a command line parsing module 310, a simulation task splitting module 320, and a simulation task executing module 330.
The system comprises a command line analyzing module 310, a simulation task splitting module 320 and a simulation task executing module 330, wherein the command line analyzing module 310 is used for analyzing a preset simulation command line based on a plurality of target processes to determine a wafer-level chip simulation task corresponding to the preset simulation command line, the simulation task splitting module 320 is used for splitting the wafer-level chip simulation task based on a main process in the target processes to obtain a plurality of chip simulation subtasks, and the simulation task executing module 330 is used for distributing the plurality of chip simulation subtasks to a plurality of target processes so that the target processes can process the chip simulation subtasks in parallel based on a plurality of corresponding threads to obtain a target simulation result corresponding to the preset simulation command line.
According to the technical scheme provided by the embodiment of the invention, the wafer-level chip simulation task corresponding to the preset simulation command line is determined by analyzing the preset simulation command line based on a plurality of target processes, the wafer-level chip simulation task is split based on a main process in the target processes to obtain a plurality of chip simulation subtasks, and the plurality of chip simulation subtasks are distributed to the plurality of target processes so that the target processes can process the chip simulation subtasks in parallel based on the corresponding plurality of threads to obtain a target simulation result corresponding to the preset simulation command line. The technical scheme of the embodiment of the invention solves the problem that the effective simulation cannot be carried out on the wafer-level chip in the prior art, can process the wafer-level chip simulation task in parallel based on a plurality of target processes, improves the simulation speed under the condition of meeting the requirement of simulation precision, supports the large-scale wafer-level chip simulation and meets the requirement of designing and verifying the wafer-level chip system-level development environment.
In an optional implementation manner, the simulation task splitting module 320 is specifically configured to determine, by the main process, a target configuration diagram according to the target configuration file and the wafer level chip simulation task when the target configuration file corresponding to the preset simulation command line exists, where the target configuration diagram is used to represent link information between components to be used corresponding to the chip simulation subtask, split the target configuration diagram to obtain a plurality of partition diagrams, and determine the chip simulation subtask according to the partition diagrams.
In an alternative embodiment, the simulation task splitting module 320 includes a configuration diagram determining unit, configured to obtain a preset simulation configuration model, where the preset simulation configuration model is used to represent internal configuration information of a preset component and link information between the preset component and other preset components, the preset component includes at least one of a processor component, a memory component, and a network component, and determine the target configuration diagram according to the preset simulation configuration model, the target configuration file, and the wafer level chip simulation task.
In an alternative implementation manner, the simulation task splitting module 320 further includes a process communication path determining unit, configured to determine a process communication path by using the master process according to the target configuration diagram, and send the process communication path to a target process executing the chip simulation subtask, where the process communication path is used to represent a communication path with a minimum communication delay between the target processes.
In an alternative embodiment, the simulation task execution module 330 includes a simulation subtask processing unit, configured to execute, for each target process, the chip simulation subtask in parallel based on a plurality of threads corresponding to the target process to obtain a sub-simulation result corresponding to the target process, and unify formats of the sub-simulation results of the plurality of target processes to determine the target simulation result.
In an optional implementation manner, the simulation subtask processing unit comprises a subtotal simulation result determining subtotal, wherein the subtotal simulation result determining subtotal is used for splitting the chip simulation subtask by a main thread in the target process to obtain a plurality of chip simulation subtasks, and distributing the plurality of chip simulation subtasks to a plurality of target threads in the target process so that the plurality of target threads execute the distributed chip simulation subtasks in parallel, and determining a subtotal simulation result corresponding to the target process according to the simulation results of the plurality of target threads.
In an alternative implementation mode, the simulation subtask processing unit further comprises a thread communication path determining subunit, wherein the thread communication path determining subunit is used for determining a thread communication path according to the partition map in the chip simulation subtask by the main thread and sending the thread communication path to a target thread executing the chip simulation subtask, and the thread communication path is used for representing a communication path with minimum communication delay between the target threads.
In an alternative implementation mode, the wafer level chip simulation device further comprises a configuration file registration module, wherein the configuration file registration module is used for taking a preset configuration file as the target configuration file and registering component information in the preset configuration file into a preset database when the target configuration file corresponding to the preset simulation command line does not exist.
The wafer-level chip simulation device provided by the embodiment of the invention can execute the wafer-level chip simulation method provided by any embodiment of the invention, and has the corresponding functional modules and beneficial effects of the execution method.
Fig. 7 is a schematic structural diagram of a computer device according to an embodiment of the present invention. Fig. 7 illustrates a block diagram of an exemplary computer device 12 suitable for use in implementing embodiments of the present invention. The computer device 12 shown in fig. 7 is only an example and should not be construed as limiting the functionality and scope of use of embodiments of the invention. The computer device 12 may be any terminal device with computing power and may be configured in a wafer level chip emulation device.
As shown in fig. 7, the computer device 12 is in the form of a general purpose computing device. Components of computer device 12 may include, but are not limited to, one or more processors or processing units 16, a system memory 28, and a bus 18 that connects the various system components, including system memory 28 and processing units 16.
Bus 18 may be one or more of several types of bus structures including a memory bus or memory controller, a peripheral bus, an accelerated graphics port, a processor, or a local bus using any of a variety of bus architectures. By way of example, and not limitation, such architectures include Industry Standard Architecture (ISA) bus, micro channel architecture (MAC) bus, enhanced ISA bus, video Electronics Standards Association (VESA) local bus, and Peripheral Component Interconnect (PCI) bus.
Computer device 12 typically includes a variety of computer system readable media. Such media can be any available media that is accessible by computer device 12 and includes both volatile and nonvolatile media, removable and non-removable media.
The system memory 28 may include computer system readable media in the form of volatile memory, such as Random Access Memory (RAM) 30 and/or cache memory 32. The computer device 12 may further include other removable/non-removable, volatile/nonvolatile computer system storage media. By way of example only, storage system 34 may be used to read from or write to non-removable, nonvolatile magnetic media (not shown in FIG. 7, commonly referred to as a "hard disk drive"). Although not shown in fig. 7, a magnetic disk drive for reading from and writing to a removable non-volatile magnetic disk (e.g., a "floppy disk"), and an optical disk drive for reading from or writing to a removable non-volatile optical disk (e.g., a CD-ROM, DVD-ROM, or other optical media) may be provided. In such cases, each drive may be coupled to bus 18 through one or more data medium interfaces. The system memory 28 may include at least one program product having a set (e.g., at least one) of program modules configured to carry out the functions of the embodiments of the invention.
A program/utility 40 having a set (at least one) of program modules 42 may be stored in, for example, system memory 28, such program modules 42 including, but not limited to, an operating system, one or more application programs, other program modules, and program data, each or some combination of which may include an implementation of a network environment. Program modules 42 generally perform the functions and/or methods of the embodiments described herein.
The computer device 12 may also communicate with one or more external devices 14 (e.g., keyboard, pointing device, display 24, etc.), one or more devices that enable a user to interact with the computer device 12, and/or any devices (e.g., network card, modem, etc.) that enable the computer device 12 to communicate with one or more other computing devices. Such communication may occur through an input/output (I/O) interface 22. Moreover, computer device 12 may also communicate with one or more networks such as a Local Area Network (LAN), a Wide Area Network (WAN) and/or a public network, such as the Internet, through network adapter 20. As shown in fig. 7, the network adapter 20 communicates with other modules of the computer device 12 via the bus 18. It should be appreciated that although not shown in FIG. 7, other hardware and/or software modules may be used in connection with computer device 12, including, but not limited to, microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, data backup storage systems, and the like.
The processing unit 16 executes various functional applications and data processing by running programs stored in the system memory 28, for example, implementing a wafer-level chip simulation method provided by an embodiment of the present invention, the method includes:
analyzing a preset simulation command line based on a plurality of target processes, determining a wafer-level chip simulation task corresponding to the preset simulation command line, splitting the wafer-level chip simulation task based on a main process in the target processes to obtain a plurality of chip simulation subtasks, and distributing the plurality of chip simulation subtasks to the plurality of target processes so that the target processes process the chip simulation subtasks in parallel based on a plurality of corresponding threads to obtain a target simulation result corresponding to the preset simulation command line.
The present embodiment provides a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, implements a wafer level chip simulation method as provided in any embodiment of the present invention, comprising:
analyzing a preset simulation command line based on a plurality of target processes, determining a wafer-level chip simulation task corresponding to the preset simulation command line, splitting the wafer-level chip simulation task based on a main process in the target processes to obtain a plurality of chip simulation subtasks, and distributing the plurality of chip simulation subtasks to the plurality of target processes so that the target processes process the chip simulation subtasks in parallel based on a plurality of corresponding threads to obtain a target simulation result corresponding to the preset simulation command line.
The computer storage media of embodiments of the invention may take the form of any combination of one or more computer-readable media. The computer readable medium may be a computer readable signal medium or a computer readable storage medium. The computer readable storage medium can be, for example but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the foregoing. More specific examples (a non-exhaustive list) of the computer-readable storage medium include an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In this document, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.
The computer readable signal medium may include a propagated data signal with computer readable program code embodied therein, either in baseband or as part of a carrier wave. Such a propagated data signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination of the foregoing. A computer readable signal medium may also be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device.
Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.
Computer program code for carrying out operations of the present invention may be written in one or more programming languages, including an object oriented programming language such as Java, smalltalk, C ++ and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any kind of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or may be connected to an external computer (for example, through the Internet using an Internet service provider).
It will be appreciated by those of ordinary skill in the art that the modules or steps of the invention described above may be implemented in a general purpose computing device, they may be centralized on a single computing device, or distributed over a network of computing devices, or they may alternatively be implemented in program code executable by a computer device, such that they are stored in a memory device and executed by the computing device, or they may be separately fabricated as individual integrated circuit modules, or multiple modules or steps within them may be fabricated as a single integrated circuit module. Thus, the present invention is not limited to any specific combination of hardware and software.
Note that the above is only a preferred embodiment of the present invention and the technical principle applied. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, while the invention has been described in connection with the above embodiments, the invention is not limited to the embodiments, but may be embodied in many other equivalent forms without departing from the spirit or scope of the invention, which is set forth in the following claims.
Claims (10)
1. A wafer level chip simulation method, comprising:
analyzing a preset simulation command line based on a plurality of target processes, and determining a wafer-level chip simulation task corresponding to the preset simulation command line;
splitting the wafer-level chip simulation task based on a main process in the target process to obtain a plurality of chip simulation subtasks;
And distributing the chip simulation subtasks to a plurality of target processes, so that the target processes parallelly process the chip simulation subtasks based on a plurality of corresponding threads to obtain a target simulation result corresponding to the preset simulation command line.
2. The method of claim 1, wherein splitting the wafer-level chip simulation task based on a master process of the target processes results in a plurality of chip simulation subtasks, comprising:
Determining a target configuration diagram by the main process according to the target configuration file and the wafer-level chip simulation task under the condition that the target configuration file corresponding to the preset simulation command line exists, wherein the target configuration diagram is used for representing link information between components to be used corresponding to the chip simulation subtask;
and splitting the target configuration diagram to obtain a plurality of partition diagrams, and determining the chip simulation subtask according to the partition diagrams.
3. The method of claim 2, wherein the host process determining the target configuration map from the target configuration file and the wafer-level chip simulation task comprises:
the method comprises the steps of obtaining a preset simulation configuration model, wherein the preset simulation configuration model is used for representing internal configuration information of a preset component and link information between the preset component and other preset components, and the preset component comprises at least one of a processor component, a memory component and a network component;
and determining the target configuration diagram according to the preset simulation configuration model, the target configuration file and the wafer-level chip simulation task.
4. A method according to claim 3, characterized in that the method further comprises:
The main process determines a process communication path according to the target configuration diagram and sends the process communication path to a target process executing the chip simulation subtask;
the process communication path is used for representing a communication path with minimum communication delay between the target processes.
5. The method of claim 1, wherein the causing the target process to process the chip emulation subtasks in parallel based on the corresponding plurality of threads to obtain the target emulation result corresponding to the preset emulation command line comprises:
aiming at each target process, executing the chip simulation subtasks in parallel based on a plurality of threads corresponding to the target process to obtain a sub-simulation result corresponding to the target process;
And unifying formats of sub-simulation results of the plurality of target processes, and determining the target simulation results.
6. The method of claim 5, wherein the executing the chip simulation subtask in parallel based on the plurality of threads corresponding to the target process to obtain the sub-simulation result corresponding to the target process comprises:
splitting the chip simulation subtasks by a main thread in the target process to obtain a plurality of chip simulation subtasks;
Distributing the multiple chip simulation sub-tasks to multiple target threads in the target process, so that the multiple target threads execute the distributed chip simulation sub-tasks in parallel, and determining sub-simulation results corresponding to the target process according to the simulation results of the multiple target threads.
7. The method of claim 6, wherein the method further comprises:
The main thread determines a thread communication path according to the partition map in the chip simulation subtask, and sends the thread communication path to a target thread executing the chip simulation subtask;
The thread communication path is used for representing a communication path with minimum communication delay between the target threads.
8. The method according to claim 2, wherein the method further comprises:
And under the condition that the component to be used corresponding to the preset simulation command line does not exist, determining a custom component according to the compiling interaction instruction, and registering the name and the dynamic library path of the custom component into the target configuration file.
9. A wafer level chip emulation device, said device comprising:
the command line analysis module is used for analyzing a preset simulation command line based on a plurality of target processes and determining a wafer-level chip simulation task corresponding to the preset simulation command line;
the simulation task splitting module is used for splitting the wafer-level chip simulation task based on a main process in the target process to obtain a plurality of chip simulation subtasks;
And the simulation task execution module is used for distributing the chip simulation subtasks to a plurality of target processes so that the target processes can process the chip simulation subtasks in parallel based on a plurality of corresponding threads to obtain a target simulation result corresponding to the preset simulation command line.
10. A computer device, the computer device comprising:
one or more processors;
A memory for storing one or more programs;
The one or more programs, when executed by the one or more processors, cause the one or more processors to implement the wafer level chip emulation method of any one of claims 1-7.
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