CN120341103A - Deposition equipment, semiconductor deposition process and semiconductor structure - Google Patents

Abstract

The present application provides a deposition device, a semiconductor deposition process and a semiconductor structure, wherein the deposition device comprises: a reaction chamber; a carrier platform, arranged in the reaction chamber, for carrying a wafer having the fin structure; a plasma dispersion structure, arranged at the top of the reaction chamber, located above the carrier platform; a plasma generator, connected to the plasma dispersion structure through a plasma pipeline, the plasma generator is used to convert a second reactant into a plasma form; an air intake pipeline, connected to the plasma pipeline, for introducing a first reactant in a gaseous form. The present application provides a deposition device, a semiconductor deposition process and a semiconductor structure, which can prevent the fins in the FinFET structure from tilting or even merging, thereby affecting the deposition quality of the dielectric layer between the fins, thereby improving the reliability of the device.

Description

Deposition equipment, semiconductor deposition process and semiconductor structure

Technical Field

The present application relates to the field of semiconductor technology, and in particular, to a deposition apparatus, a semiconductor deposition process, and a semiconductor structure.

Background

Isolation oxide of FinFET structures is typically formed by FCVD (Flowable CVD) process. However, as FinFET structures shrink further, the filling of FCVD has shown to be inadequate. The advantages of ALD (Atomic Layer Deposition ) are more pronounced from the trench filling capability alone. However, ALD has a fatal disadvantage that the formed film has a large stress (generally more than 300 MPa), and the generated ion bombardment directly acts on the fin, which may cause the fin to tilt or even merge, which is not acceptable.

Therefore, it is necessary to provide a more efficient and reliable solution to avoid tilting or even merging of fins in FinFET structures and to affect the deposition quality of the dielectric layer between the fins.

Disclosure of Invention

The application provides a deposition device, a semiconductor deposition process and a semiconductor structure, which can prevent fins in a FinFET structure from tilting or even merging to influence the deposition quality of a medium layer between the fins, thereby improving the reliability of a device.

One aspect of the application provides deposition equipment for depositing a film layer on the surface of a fin structure, which comprises a reaction cavity, a bearing table, a plasma dispersing structure, a plasma generator and an air inlet pipeline, wherein the bearing table is arranged in the reaction cavity and is used for bearing a wafer with the fin structure, the plasma dispersing structure is arranged at the top of the reaction cavity and is positioned above the bearing table, the plasma generator is communicated with the plasma dispersing structure through a plasma pipeline and is used for converting a second reactant into a plasma form, and the air inlet pipeline is communicated with the plasma pipeline and is used for introducing a first reactant in a gas form.

In some embodiments of the application, the deposition apparatus further comprises a controller configured to control the supply of the first reactant in the inlet line.

In some embodiments of the application, the supply of the first reactant in the inlet line comprises a number of supply cycles, each supply cycle comprising a supply phase and a pause phase.

In some embodiments of the application, the time of each supply cycle is 1 second to 4 minutes, wherein the supply phase in each supply cycle is 0.4 seconds to 1 minute and the pause phase in each supply cycle is 0.6 seconds to 3 minutes.

In some embodiments of the application, the plasma dispersing structure is a showerhead structure.

The application also provides a semiconductor deposition process, which adopts the deposition equipment, and comprises the steps of arranging a wafer with the fin structure on the bearing table, supplying a second reactant in a plasma form to the plasma dispersing structure through a plasma pipeline after converting the second reactant into the plasma form through the plasma generator, uniformly dispersing the second reactant by the plasma dispersing structure, and then transmitting the second reactant into a reaction cavity under the action of gravity, introducing a first reactant in a gas form into the reaction cavity through the gas inlet pipeline, and depositing a product of the reaction of the first reactant and the second reactant in the reaction cavity onto the surface of the fin structure under the action of gravity.

In some embodiments of the application, the reaction conditions in the reaction chamber include a reaction temperature of 40 to 400 degrees celsius, a reaction pressure of 0.7 to 5 torr, and a reaction time of 2 to 15 minutes.

In some embodiments of the application, the first reactant comprises trisilylmethylamine and the second reactant comprises ammonia and/or oxygen.

In some embodiments of the application, the flow rate of the first reactant is 50 to 500sccm and the flow rate of the second reactant is 50 to 600sccm.

The application also provides a semiconductor structure formed by the semiconductor deposition process, which comprises a semiconductor substrate, an insulating medium layer and a dielectric layer, wherein the semiconductor substrate comprises a fin part formed by a first fin and a second fin, the insulating medium layer is positioned on the surfaces of the first fin and the second fin and the surface of the semiconductor substrate, the insulating medium layer fills gaps between the first fin and the second fin, and the thicknesses of the insulating medium layer on the surfaces of the semiconductor substrate and the first fin and the second fin are uniform.

The application provides a deposition device, a semiconductor deposition process and a semiconductor structure, which can prevent fins in a FinFET structure from tilting or even merging to influence the deposition quality of a medium layer between the fins, thereby improving the reliability of a device.

Drawings

The following drawings describe in detail exemplary embodiments disclosed in the present application. Wherein like reference numerals refer to like structure throughout the several views of the drawings. Those of ordinary skill in the art will understand that these embodiments are non-limiting, exemplary embodiments, and that the drawings are for illustration and description only and are not intended to limit the scope of the application, as other embodiments may equally well accomplish the inventive intent in this disclosure. It should be understood that the drawings are not to scale.

Wherein:

FIG. 1 is a schematic view of a deposition apparatus according to an embodiment of the present application;

FIG. 2 is a flow chart of a semiconductor deposition process according to an embodiment of the present application;

fig. 3 is a schematic structural diagram of a semiconductor structure according to an embodiment of the application.

Detailed Description

The following description provides specific applications and requirements of the application to enable any person skilled in the art to make and use the application. Various modifications to the disclosed embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the application. Thus, the present application is not limited to the embodiments shown, but is to be accorded the widest scope consistent with the claims.

The technical scheme of the invention is described in detail below with reference to the examples and the accompanying drawings.

Fig. 1 is a schematic structural view of a deposition apparatus according to an embodiment of the present application.

The embodiment of the application provides a deposition device 100 for depositing a film layer on the surface of a fin structure, which comprises a reaction cavity 110, a bearing table 120, a plasma dispersing structure 130, a plasma generator 150 and an air inlet pipeline 140, wherein the bearing table 120 is arranged in the reaction cavity 110 and is used for bearing a wafer with the fin structure, the plasma dispersing structure 130 is arranged at the top of the reaction cavity 110 and is positioned above the bearing table 120, the plasma generator 150 is communicated with the plasma dispersing structure 130 through a plasma pipeline 160, the plasma generator 150 is used for converting a second reactant into a plasma form, and the air inlet pipeline 140 is communicated with the plasma pipeline 160 and is used for introducing a first reactant in a gas form.

In the conventional deposition apparatus, instead of generating plasma by the external plasma generator 150, the susceptor 120 and the plasma dispersing structure 130 are made of conductive materials and then are connected to a power supply, so that the susceptor 120 and the plasma dispersing structure 130 perform the functions of an upper electrode plate and a lower electrode plate in addition to their own functions, a strong electric field is formed between the susceptor 120 and the plasma dispersing structure 130, and the reactants in the reaction chamber are changed into plasma by using the electric field. However, in use of such a deposition apparatus, the stronger electric field applies a downward electric field force to the plasma, causing the plasma to accelerate downward deposition onto the wafer on the platen 120. On the one hand, the deposition speed is increased, the conformal growth of the film layer is not facilitated, on the other hand, plasma can generate a certain impact force on the wafer, and particularly when the surface of the wafer is provided with the fin structures, and the size of each fin structure is thinner, the fin structures are easy to incline under the impact force of the plasma, even the adjacent fin structures are combined with each other, and the film layer which needs to be filled cannot be filled between the adjacent fin structures.

In the technical solution of the present application, as shown in fig. 1, the carrier 120 and the plasma dispersing structure 130 only take on their original functions, and are not connected to the power supply to take on the function of generating an electric field by the electrode plates. The plasma required for the deposition process is formed by an external plasma generator 150 and then introduced into the reaction chamber 110. Thus, the plasma is no longer acted upon by the electric field after entering the reaction chamber 110, but is naturally deposited onto the wafer on the susceptor 120 by gravity. On the one hand, the deposition speed can be reduced, so that the film layer can be grown in a better shape, on the other hand, plasma can not generate impact force on the wafer, the fin structures are not damaged or inclined or even the adjacent fin structures are combined with each other, and the film layer which needs to be filled can be filled between the adjacent fin structures.

With continued reference to fig. 1, in some embodiments of the application, the stage 120 is further configured to heat a wafer placed on the stage 120. In some embodiments of the present application, the carrier 120 need not be made of a conductive material, since it is not necessary to perform the function of an electrode plate, and the carrier 120 may be made of other materials that are more suitable for performing both the heating and carrying functions, such as ceramic.

With continued reference to FIG. 1, in some embodiments of the application, the plasma dispersing structure 130 is a showerhead structure. The plasma dispersing structure 130 is used for dispersing the plasma entering the plasma dispersing structure 130, so as to avoid the concentration of the plasma at the inlet of the plasma pipe 160. In order to better perform the dispersing function of the plasma dispersing structure 130, preferably, the plasma dispersing structure 130 is a shower head structure, and has a plurality of dispersed fine pipelines therein, and the plasma enters the plasma dispersing structure 130 and then is dispersed into the plurality of fine pipelines, and then is dispersed into the whole plasma dispersing structure 130, and finally can flow out from the outlet of the whole plasma dispersing structure 130.

In some embodiments of the present application, as with the carrier 120, the plasma dispersing structure 130 need not be made of a conductive material, since it is not necessary to take on the role of an electrode plate, and the plasma dispersing structure 130 may be made of other materials that are more suitable for functioning, such as ceramic.

With continued reference to FIG. 1, in some embodiments of the application, the deposition apparatus 100 further includes a controller 150 configured to control the supply of the first reactant in the inlet line 140.

In some embodiments of the present application, the supply of the first reactant in the inlet line 140 comprises a number of supply cycles, each supply cycle comprising a supply phase and a pause phase. The supply phase is connected to the pause phase. The first reactant is introduced during the supply phase and the first reactant is suspended during the suspension phase. That is, the supply is by circulating the first reactant for a period of time and then suspending the supply of the first reactant for a period of time.

In some embodiments of the application, the time of each supply cycle is 1 second to 4 minutes, wherein the supply phase in each supply cycle is 0.4 seconds to 1 minute and the pause phase in each supply cycle is 0.6 seconds to 3 minutes. The deposition rate of the reactants was 1 to 2 angstrom per cycle.

In conventional deposition apparatus, the supply of the gas inlet 140 is continuous, so that the reaction is continuously performed in the reaction chamber 110, and the reaction products are continuously generated and deposited on the wafer. In this case, the deposition rate is high, the deposition amount is large, and the deposition cannot grow in a conformal manner.

In the solution of the present application, the air inlet pipe 140 is provided by intermittent circulation. The deposition is not carried out continuously by generating a large amount of reactant, but is carried out intermittently by a little, so that the deposition speed is low, and the growth can be well conformal.

The application provides a deposition device, which can avoid the influence of tilting or even merging of fins in a FinFET structure on the device failure, thereby improving the reliability of the device.

Fig. 2 is a flow chart of a semiconductor deposition process according to an embodiment of the application.

Embodiments of the present application also provide a semiconductor deposition process employing the deposition apparatus 100 as described above, the semiconductor deposition process comprising:

Step S1, arranging a wafer with the fin structure on the bearing table;

Step S2, converting a second reactant into a plasma form through the plasma generator, and then supplying the second reactant in the plasma form to the plasma dispersing structure through a plasma pipeline, wherein the second reactant is uniformly dispersed by the plasma dispersing structure and then is transmitted into the reaction cavity under the action of gravity;

and S3, introducing a first reactant in a gas form into the reaction cavity through the gas inlet pipeline, and depositing a product of the first reactant and the second reactant after reaction in the reaction cavity onto the surface of the fin structure under the action of gravity.

In the technical scheme of the application, the deposition equipment 100 is adopted to carry out the semiconductor deposition process, reactants deposit and fall on the surface of a wafer under the action of gravity in the deposition process, and no plasma bombards the surface of the wafer in the reaction process, so that the fin structures in the formed semiconductor structure are not damaged, are not inclined or even combined, and well fill the sediments among the fin structures.

In some embodiments of the present application, the semiconductor deposition process of the present application is specifically to deposit an oxide film layer on a surface of a fin structure, and the wafer having the fin structure is, for example, a FinFET device structure. The first reactant thus comprises Trisilylmethylamine (TSA) and the second reactant comprises ammonia and/or oxygen, and the product is SiONH (which subsequently becomes silica by annealing).

In some embodiments of the present application, the order of the steps of introducing the first reactant and introducing the second reactant in the step S2 and the step S3 is not limited herein. That is, the first reactant may be introduced first and then the second reactant may be introduced first and then the first reactant may be introduced, or the first reactant and the second reactant may be introduced simultaneously.

In some embodiments of the application, the reaction conditions in the reaction chamber include a reaction temperature of 40 to 400 degrees celsius, a reaction pressure of 0.7 to 5 torr, and a reaction time of 2 to 15 minutes.

In some embodiments of the application, the flow rate of the first reactant is 50 to 500sccm and the flow rate of the second reactant is 50 to 600sccm. The deposition rate of the product was 0.5 to 5 angstrom per cycle.

In some embodiments of the present application, the stress of the film layer formed by the semiconductor deposition process of the present application is less than 100MPa.

The application provides a semiconductor deposition process, which can avoid the device failure caused by tilting or even merging of fins in a FinFET structure, thereby improving the device reliability.

Fig. 3 is a schematic structural diagram of a semiconductor structure according to an embodiment of the application.

The embodiment of the application also provides the semiconductor structure 200 formed by adopting the semiconductor deposition process, which comprises a semiconductor substrate 210, an insulating dielectric layer 230 and an insulating dielectric layer 230, wherein the surface of the semiconductor substrate 210 comprises a fin part 220 formed by a first fin 221 and a second fin 222, the insulating dielectric layer 230 is positioned on the surfaces of the first fin 221 and the second fin 222 and the surface of the semiconductor substrate 210, the insulating dielectric layer 230 fills the gap between the first fin 221 and the second fin 222, and the thicknesses of the insulating dielectric layer 230 on the surfaces of the semiconductor substrate 210 and the surfaces of the first fin 221 and the second fin 222 are uniform.

In some embodiments of the present application, the semiconductor structure of the present application is, for example, a FinFET device.

In some embodiments of the present application, the material of the semiconductor substrate 210 comprises (i) an elemental semiconductor, such as silicon or germanium, or the like, (ii) a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide, or indium phosphide, or the like, (iii) an alloy semiconductor, such as silicon germanium carbide, silicon germanium, gallium arsenide phosphide, or indium gallium phosphide, or the like, or (iv) a combination thereof.

In some embodiments of the present application, the surface of the semiconductor substrate 210 may be formed with a plurality of fins 220, and the present application is illustrated by only one fin.

In some embodiments of the present application, the material of the insulating dielectric layer 230 comprises silicon oxide.

In some embodiments of the present application, the stress of the insulating dielectric layer 230 is less than 100MPa.

In the semiconductor structure formed by conventional deposition equipment and deposition process, the first fin 221 and the second fin 222 may be inclined to each other or even directly combined due to the bombardment of plasma, which directly affects the functions of the fins. In addition, since the fins are close together and the deposition speed is high, the degree of conformality is low, and the formed insulating dielectric layer 230 cannot fill the gap between the first fin 221 and the second fin 222, so that a void exists in the insulating dielectric layer 230, and the quality of the insulating dielectric layer 230 is reduced. And the deposited insulating dielectric layer 230 is not uniform in thickness and cannot be conformal.

In the technical scheme of the application, the deposition equipment 100 is adopted to execute the semiconductor deposition process of the application, reactants are deposited and fall onto the surface of the semiconductor substrate 210 under the action of gravity in the deposition process, and no plasma bombards the surface of the semiconductor substrate 210 (including the first fin 221 and the second fin 222) in the reaction process, so that the first fin 221 and the second fin 222 in the formed semiconductor structure are not damaged, cannot incline or even merge, and the insulating medium layer 230 is well filled between the first fin 221 and the second fin 222.

The application provides a deposition device, a semiconductor deposition process and a semiconductor structure, which can avoid the failure of a device caused by tilting or even merging of fins in a FinFET structure, thereby improving the reliability of the device.

In view of the foregoing, it will be evident to those skilled in the art after reading this disclosure that the foregoing application may be presented by way of example only and may not be limiting. Although not explicitly described herein, those skilled in the art will appreciate that the present application is intended to embrace a variety of reasonable alterations, improvements and modifications to the embodiments. Such alterations, improvements, and modifications are intended to be within the spirit and scope of the exemplary embodiments of the application.

It should be understood that the term "and/or" as used in this embodiment includes any or all combinations of one or more of the associated listed items. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may also be present.

Similarly, it will be understood that when an element such as a layer, region or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. In contrast, the term "directly" means without intermediate elements. It will be further understood that the terms "comprises," "comprising," "includes" or "including," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

It will be further understood that, although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Thus, a first element in some embodiments could be termed a second element in other embodiments without departing from the teachings of the present application. Like reference numerals or like reference numerals designate like elements throughout the specification.

Furthermore, the present description describes example embodiments with reference to idealized example cross-sectional and/or plan and/or perspective views. Thus, differences from the illustrated shapes, due to, for example, manufacturing techniques and/or tolerances, are to be expected. Thus, the exemplary embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region shown as a rectangle will typically have rounded or curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the exemplary embodiments.

Claims (10)

1. A deposition device for depositing a film layer on a surface of a fin structure, comprising: Reaction chamber; A carrying platform, disposed in the reaction chamber, for carrying the wafer having the fin structure; A plasma dispersion structure is arranged at the top of the reaction chamber and above the supporting platform; a plasma generator, connected to the plasma dispersion structure through a plasma pipeline, the plasma generator being used to convert the second reactant into a plasma form; The air inlet pipeline is connected to the plasma pipeline and is used for introducing the first reactant in gas form. 2. The deposition device as described in claim 1 is characterized in that it also includes: a controller configured to control the supply method of the first reactant in the air intake pipeline. 3. The deposition device as described in claim 2 is characterized in that the supply method of the first reactant in the air inlet pipeline includes several supply cycles, and each supply cycle includes a supply stage and a pause stage. 4. The deposition device as described in claim 3 is characterized in that the time of each supply cycle is 1 second to 4 minutes, wherein the supply phase in each supply cycle is 0.4 seconds to 1 minute, and the pause phase in each supply cycle is 0.6 seconds to 3 minutes. 5 . The deposition device according to claim 1 , wherein the plasma dispersion structure is a shower head structure. 6. A semiconductor deposition process, characterized in that the deposition device according to any one of claims 1 to 5 is used, and the semiconductor deposition process comprises: Placing the wafer having the fin structure on the carrier; After the second reactant is converted into a plasma form by the plasma generator, the second reactant in the plasma form is supplied to the plasma dispersion structure through the plasma pipeline, and the plasma dispersion structure disperses the second reactant uniformly and then transmits it to the reaction chamber under the action of gravity; A first reactant in gaseous form is introduced into the reaction chamber through the air inlet pipeline, and a product of the reaction between the first reactant and the second reactant in the reaction chamber is deposited on the surface of the fin structure under the action of gravity. 7. The semiconductor deposition process as described in claim 6 is characterized in that the reaction conditions in the reaction chamber include: a reaction temperature of 40 to 400 degrees Celsius; a reaction pressure of 0.7 to 5 Torr; and a reaction time of 2 to 15 minutes. 8. The semiconductor deposition process according to claim 6, wherein the first reactant comprises trisilylamine, and the second reactant comprises ammonia and/or oxygen. 9. The semiconductor deposition process according to claim 6, wherein the flow rate of the first reactant is 50 to 500 sccm, and the flow rate of the second reactant is 50 to 600 sccm. 10. A semiconductor structure formed by the semiconductor deposition process according to any one of claims 6 to 9, characterized in that it comprises: A semiconductor substrate, wherein a surface of the semiconductor substrate includes a fin portion consisting of a first fin and a second fin; The insulating dielectric layer is located on the surfaces of the first fin and the second fin and the surface of the semiconductor substrate. The insulating dielectric layer fills the gap between the first fin and the second fin. The thickness of the insulating dielectric layer on the surface of the semiconductor substrate and the surfaces of the first fin and the second fin is uniform.