CN120378390B - Network card connects circuit and server - Google Patents
Network card connects circuit and serverInfo
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- CN120378390B CN120378390B CN202510864972.3A CN202510864972A CN120378390B CN 120378390 B CN120378390 B CN 120378390B CN 202510864972 A CN202510864972 A CN 202510864972A CN 120378390 B CN120378390 B CN 120378390B
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Abstract
The application discloses a network card connecting circuit and a server, which relate to the technical field of network card connection, wherein the network card connecting circuit comprises a first transfer card and a second transfer card, the first transfer card is used for receiving a first output signal sent by a first processor and separating a communication signal and a power supply voltage in the first output signal to obtain the first communication signal and the first power supply voltage, the second transfer card is arranged on a second processor and used for receiving and integrating the first communication signal and the first power supply voltage to obtain a second output signal and/or receiving a third output signal sent by the second processor and sending the second output signal or the third output signal through a target network card, so that when the resources of the first processor are insufficient, the target network card corresponding to the second processor can be multiplexed through the first transfer card and the second transfer card, the technical problem of communication transmission delay of an OCP network card when the CPU resources are insufficient can be solved, and the technical effect of target cross-CPU resource allocation is achieved.
Description
Technical Field
The application relates to the technical field of network card connection, in particular to a network card connection circuit and a server.
Background
With the promotion and organization of OCP (open compute project, a technology association for servers) association, more and more enterprises and organizations are increasingly demanding OCP NIC (Network INTERFACE CARD) Network cards in cloud computing server systems, which requires perfect adaptation of compatibility of the OCP NIC cards by server scheme providers and complete machine manufacturers.
In the related art, the OCP network cards and the CPUs (Central Processing Unit, central processing units) are arranged in a one-to-one correspondence manner, that is, each OCP network card is connected to a corresponding CPU through a corresponding link and a switching card, and each CPU performs information transmission through the connected OCP network card. However, when the CPU resource is overloaded, the communication transmission delay of the OCP network card is easily caused, and the user experience is reduced.
Disclosure of Invention
The application provides a network card connecting circuit and a server, which at least solve the problem of communication transmission delay of an OCP network card when CPU resources are insufficient in the related technology.
The application provides a network card connecting circuit which comprises a first transfer card, a second transfer card and a second transfer card, wherein the input end of the first transfer card is connected with a network card interface of a first processor and is used for receiving a first output signal sent by the first processor, separating a communication signal and a power supply voltage in the first output signal to obtain the first communication signal and the first power supply voltage, the second transfer card is arranged on a second processor, the first input end of the second transfer card is connected with the output end of the first transfer card, the second input end of the second transfer card is connected with a data interface of the second processor, the output end of the second transfer card is connected with a target network card and is used for receiving and integrating the first communication signal and the first power supply voltage to obtain a second output signal and/or receiving a third output signal sent by the second processor and sending the second output signal or the third output signal through the target network card.
The application also provides a server which comprises a plurality of processors, wherein the processors comprise a second processor and a first processor, and the network card connecting circuit.
According to the application, the network card interface of the first processor can be connected with the target network card corresponding to the second processor through the first transfer card and the second transfer card, so that the network card interface can be used for communication transmission of the second processor through the target network card, and can also be used for communication transmission requirements of the first processor.
Drawings
For a clearer description of embodiments of the present application, the drawings that are required to be used in the embodiments will be briefly described, it being apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to the drawings without inventive effort for those skilled in the art.
Fig. 1 is a schematic diagram of a network card connection circuit according to an embodiment of the present application;
fig. 2 is a schematic diagram of a network card connection circuit according to an embodiment of the present application;
FIG. 3 is a schematic diagram of a network card connection circuit according to another embodiment of the present application;
fig. 4 is a connection schematic diagram of a server according to an embodiment of the present application.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. Based on the embodiments of the present application, all other embodiments obtained by a person of ordinary skill in the art without making any inventive effort are within the scope of the present application.
It should be noted that in the description of the present application, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. The terms "first," "second," and the like in this specification are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order.
The present application will be further described in detail below with reference to the drawings and detailed description for the purpose of enabling those skilled in the art to better understand the aspects of the present application.
Under the promotion and organization of the OCP society, more and more enterprises and institutions have increasingly strong demands for OCP NIC network cards in cloud computing server systems, which requires perfect adaptation of compatibility of server scheme providers and complete machine manufacturers with OCP NIC network cards.
In the related art, a connection scheme of a server and an OCP network card or a connection scheme of binding a CPU and the OCP network card one by one is adopted. The method comprises the following steps:
In the connection scheme adopting the server and the OCP network card, an adaptive design of the OCP NIC network card with fixed upstream PCIe (PERIPHERAL COMPONENT INTERCONNECT EXPRESS, high-speed serial computer expansion bus standard) link and bandwidth is adopted on a main board of the server, and the fixed PCIe link and bandwidth are provided for the OCP NIC network card by placing a 4C+/4C (Connector) Connector of the fixed OCP NIC network card on the main board, and an upstream PCIe signal of the Connector is connected to a fixed CPU or bridge chip. However, the standard design of providing the fixed PCIe link to the OCP NIC card based on the motherboard is effective, but only can be compatible with the OCP NIC card with limited types of adaptation, and the compatible requirements of the various OCP NIC cards cannot be met due to limited types of compatible OCP NIC cards. Taking the use of the OCP NIC network card of the server as an example, if the operation and maintenance personnel are not completely familiar with the design of the interior of the server in the machine room and the type of the peripheral OCP NIC network card, when an A-type OCP NIC network card is inserted into the server only supporting the B-type OCP NIC network card, the server has the problem of incompatibility adaptation and external insertion of the OCP NIC network card, so that the server is in downtime and the OCP NIC network card cannot work normally, and the user experience is not facilitated.
In the connection scheme adopting one-to-one binding of the CPU and the OCP network card, the OCP network card is connected to a single CPU (such as CPU 1) through a single link and a transfer card, and when the server only configures the single CPU or the CPU1 to be overloaded, delay is increased, and user experience is reduced.
In order to solve at least one technical problem, the application provides a network card connecting circuit, wherein a network card interface of a first processor (such as a CPU 1) can be connected with a target network card corresponding to a second processor (such as a CPU 0) through a first switching circuit and a second switching circuit, so that the network card can be used for communication transmission of the CPU0 through the target network card and can also be used for communication transmission requirements of the CPU1, and at the moment, when the CPU1 is insufficient in resources, the target network card at the CPU0 can be multiplexed through the first switching card and the second switching card, so that communication transmission is carried out based on the target network card, thereby solving the technical problem of communication transmission delay of an OCP network card when the CPU resource is insufficient, achieving the technical effects of dynamically distributing the target network card across the CPU resource, improving the load balance and solving the problem of exclusive hardware-level resources.
The network card connection circuit according to the embodiment of the present application will be described in detail below by taking the target network card as an OCP network card as an example.
Fig. 1 is a schematic diagram of a network card connection circuit according to an embodiment of the present application.
As shown in fig. 1, the network card connection circuit 100 according to the embodiment of the application includes a first adapter card 10 and a second adapter card 20 disposed on a second processor.
The input end of the first adapter card 10 is connected to the network card interface of the first processor, and is configured to receive the first output signal sent by the first processor, and separate the communication signal and the power supply voltage in the first output signal, so as to obtain a first communication signal and a first power supply voltage. The first input end of the second adapter card 20 is connected with the output end of the first adapter card 10 respectively, the second input end of the second adapter card 20 is connected with the data interface of the second processor, the output end of the second adapter card 20 is connected with the target network card and is used for receiving the first communication signal and the first power supply voltage, integrating the first communication signal and the first power supply voltage to obtain a second output signal, and/or receiving a third output signal sent by the second processor so as to send the second output signal or the third output signal through the target network card.
Specifically, the first adapter card 10 is disposed in an area where the corresponding first processor is located, receives a first output signal sent by the first processor through an OCP interface connected to the first processor (i.e., a network card interface of the first processor), separates a PCIe signal (i.e., a communication signal) and a 12V supply voltage from the first output signal, processes the PCIe signal, for example, performs signal amplification, filtering, etc., to obtain a processed PCIe signal (i.e., a first communication signal), and processes, for example, filters, etc., the 12V supply voltage to obtain a processed 12V power supply (i.e., a second supply voltage). The first adapter card 10 can avoid power noise coupling by separating the PCIe signal of the first output signal and the 12V power supply into independent lines and transmitting the independent lines to the second adapter card 20 respectively.
The second processor can be selected according to the processor load in the server, and the processor with smaller load is selected as the second processor, and can be specifically selected according to actual conditions. The second adapter card 20 is arranged in the area where the second processor is located and is connected with the main board through the Slimline x interface, on one hand, a second output signal can be obtained by integrating the first communication signal and the first power supply voltage and is output through the target network card, that is to say, the data transmission task of the first processor is completed through the target network card arranged at the second processor, and on the other hand, a third output signal which is a data transmission task issued by the second processor can be received based on the Slimline x interface and is output through the target network card. It should be noted that the second output signal needs to meet the PCIe signal requirement of the second processor, for example, the second power supply voltage is converted into 3.3V/5V to adapt to the PCIe power requirement of the second processor, so that the second output signal is sent out based on the OCP interface of the second processor, that is, the output end of the second adapter card 20.
In addition, the second output signal may be sent through the target network card by controlling the on/off of the line inside the second adapter card 20, or the third output signal may be sent through the control of the motherboard, which is not limited in particular.
According to the embodiment, through the circuit connection of the first transfer card 10 and the second transfer card 20, communication transmission of the first processor can be completed based on the target network card arranged on the second processor, meanwhile, based on a transmission strategy of communication and power supply separation, interference is reduced, transmission effect is guaranteed, the second transfer card 20 can realize signal transmission of an OCP interface to the first processor and the second processor based on communication switching, seamless switching of a PCIe channel from the first processor to the second processor is realized through transfer card hardware, software intervention is not needed, dynamic allocation of the OCP network card based on double transfer cards across processor resources is realized, the problem of load balancing when processor resources are insufficient in the related technology is solved, and application flexibility of the target network card is improved. The circuit can also be suitable for dynamic resource allocation of PCIe peripheral devices such as GPU (Graphics Processing Unit, graphic processing unit), NVMe (Non-Volatile Memory Express, nonvolatile memory express channel) devices and the like.
Further, the network card connection circuit 100 may include a plurality of first switch cards 10, where each first switch card 10 corresponds to a first processor, and is configured to communicate and separate power supply from a first output signal of a corresponding first processor, and output ends of the first switch cards are respectively connected to corresponding ports of a first input end of the second switch card 20, and the ports of the first input end of the second switch card 20 identify inputs of different processors, so as to perform signal integration and output, thereby implementing dynamic resource allocation among the plurality of processors.
In some embodiments of the application, as shown in connection with fig. 2, the first switch card 10 comprises a signal relay module 11, an input of the signal relay module 11 being connected to a communication port of the input of the first switch card 10, an output of the signal relay module 11 being adapted to be connected to a communication port of the first input of the second switch card 20 for receiving a communication signal of the first output signal via the communication port of the input of the first switch card and generating the first communication signal based on the communication signal of the first output signal, and a power separation module 12, an input of the power separation module 12 being connected to a power supply port of the input of the first switch card 10, an output of the power separation module 12 being adapted to be connected to a power supply port of the first input of the second switch card 20 for receiving a power supply voltage of the first output signal via the power supply port of the input of the first switch card 10 and generating the first power supply voltage based on the power supply voltage of the first output signal.
Specifically, the signal relay module 11 is a signal relay node from the first processor to the target network card, and is configured to receive, amplify and forward signals, so as to achieve the functions of expanding signal coverage, enhancing transmission reliability and compensating signal attenuation, so as to solve the problem of signal attenuation in long-distance transmission, and ensure stability and reliability of long-distance communication. The signal relay module 11 processes the communication signal separated from the first output signal to obtain a first communication signal for long-distance transmission, and transmits the second output signal to the communication port of the first input end of the second riser card 20 through the communication line. The power supply separation module 12 processes the power supply voltage separated from the first output signal to obtain a first power supply voltage for transmission, and transmits the first power supply voltage to the power supply port of the first input end of the second adapter card 20 through the power line. Thus, by separating the 12V power supply and PCIe signals into separate lines, power supply noise coupling is avoided.
In some embodiments of the present application, the signal relay module 11 includes a differential signal amplifying unit, where an input terminal of the differential signal amplifying unit is connected to a communication port of an input terminal of the first adapter card 10, and is configured to amplify a communication signal in the first output signal to generate a first communication signal.
Specifically, the differential signal is a signal transmission mode, and signals are transmitted through two signal lines, wherein one signal is a positive signal, the other signal is a negative signal, and the phases of the two signals are opposite. The signal transmission mode has the advantages of strong anti-interference capability, good signal integrity and the like, and is suitable for high-speed signal transmission. The differential signal amplification unit includes at least one differential signal amplifier for signal amplifying the received communication signal to generate a first communication signal, thereby enhancing signal quality to enable more stable and reliable transmission over longer distances.
For example, the gain value of the differential signal amplifying unit may be set to 8db@5ghz, that is, the gain of the signal is 8db at a frequency of 5 GHz. The gain is an index for measuring the amplification degree of the signal, and the higher gain can enable the signal to be amplified more effectively in the transmission process, so that the strength and the quality of the signal are enhanced. The gain of 8dB is a relatively reasonable value in high-speed signal transmission, so that the transmission performance of the signal can be effectively improved without introducing excessive noise and distortion, and the gain can be specifically set according to actual conditions. The gain can be realized through the resistance adjustment of the external resistor, the amplification degree of the signal can be accurately controlled, so that the optimal signal transmission effect is realized, a user can flexibly adjust the gain according to the actual application requirements and the system characteristics, greater flexibility and adaptability are provided for the system design, and the signal transmission requirements under different scenes can be better met.
The embodiment optimizes the signal transmission performance by utilizing the differential signal amplifying unit, ensures the accurate and rapid transmission of data, and improves the communication transmission efficiency and reliability.
In addition, the signal relay module 11 may further include an adaptive equalization compensation unit to support adaptive equalization compensation functions, including CTLE (continuous TIME LINEAR Equalizer) and DFE (Decision Feedback Equalizer ). The CTLE can compensate the high-frequency attenuation of the signal caused by the characteristic of the transmission line in the transmission process to recover the high-frequency component of the signal, and the DFE can adjust the current signal according to the history information of the received signal to further optimize the signal quality. The self-adaptive equalization compensation function can automatically adjust equalization parameters according to the actual condition of signal transmission, so that the self-adaptive equalization compensation function is better suitable for different transmission environments, and the reliability and stability of signal transmission are improved.
In some embodiments of the present application, the signal relay module 11 further includes an electrostatic protection unit, wherein one end of the electrostatic protection unit is connected to the communication port of the input end of the first adapter card and the input end of the differential signal amplifying unit, and the other end of the electrostatic protection unit is grounded.
Specifically, the electrostatic discharge refers to an instantaneous high-voltage discharge phenomenon due to accumulation of static electricity. Such discharges may cause damage to the electronic device, especially at the input, because the input is directly connected to an external signal source or a user operation interface, and is more susceptible to interference and impact from external static electricity. To prevent damage to internal circuits by electrostatic discharge, stable operation and reliability of the circuits are ensured. The embodiment is provided with the electrostatic protection unit, and particularly, a bidirectional TVS (TRANSIENT VOLTAGE SUPPRESSOR ) electrode two-tube array is deployed at the input end of the signal relay module 11, and the protection level of +/-15 kV is achieved, so that electrostatic protection capability is provided for electronic equipment, the risk of damage to a circuit caused by static is effectively reduced, and the normal operation and reliability of the circuit are ensured.
In some embodiments of the present application, the signal relay module 11 further includes an impedance matching unit, one end of the impedance matching unit is connected to the output terminal of the differential signal amplifying unit, and the other end of the impedance matching unit is used as the output terminal of the signal relay module.
Specifically, when a signal propagates on a communication line, if the characteristic impedance of the communication line is not matched with the impedances of a signal source and a load, reflection of the signal is caused, thereby causing distortion and transmission loss of the signal. Therefore, the embodiment adds an impedance matching unit in the signal relay module 11, and ensures that the first communication signal can be efficiently and completely transmitted to the second riser card 20 through the arrangement of the impedance matching network, so that the reflection and interference of the first communication signal are reduced, and the quality and reliability of signal transmission are improved.
For example, the impedance matching unit strictly maintains 100 Ω differential impedance (4 mil linewidth, 8mil pitch) by disposing 100 Ω differential resistance (±1% precision) at the output of the signal relay module 11, and PCB (Printed Circuit Board ) routing. The arrangement of the 100deg.C differential resistor at the output end of the signal relay module 11 is to realize impedance matching of differential signals, so that the differential signals (i.e. the first communication signals) are well matched at the end of the communication line, signal reflection is reduced, and signal integrity is ensured, and the precision of the differential resistor is required to be +/-1%, which means that the actual value of the differential resistor should be 99 Ω to 101 Ω, and the high-precision resistor can more accurately realize impedance matching, thereby improving the quality and stability of signal transmission. In addition, differential impedance refers to the impedance characteristics of a differential signal transmission line to a signal, which is related to the geometry of the transmission line, dielectric material, and the like. Therefore, in the PCB design, a specific differential impedance value is realized through an accurate routing design, and the 100 Ω differential impedance corresponding to this embodiment needs to consider factors such as line width, pitch, and dielectric thickness of the transmission line. The line width of the PCB wiring is 4mil, the interval is 8mil, and the line width can be determined according to a calculation formula of differential impedance and the dielectric material characteristics of the PCB, so that the differential impedance of 100 omega can be realized under a given PCB structure, the impedance consistency of differential signals in the transmission process can be ensured, and the reflection and distortion in the signal transmission process can be reduced.
In some embodiments of the present application, the output of the signal relay module 11 is adapted to be connected to the communication port of the first input of the second riser card 20 by a shielded cable.
That is, the first riser card 10 and the second riser card 20 are interconnected by a custom cable, the signal relay module 11 transmits PCIe differential signals through a shielded cable, and interference is reduced by an additional shielding layer of the shielded cable.
In some embodiments of the present application, the power separation module 12 includes a filtering unit and a noise isolation unit for filtering and noise isolating the power supply voltage in the first output signal to generate a first power supply voltage.
Specifically, the connection sequence of the filtering unit and the noise isolation unit is not limited, the power supply voltage obtained by separation can be filtered through the filtering unit, noise isolation processing is performed on the power supply voltage obtained by separation through the noise isolation unit, so that the first power supply voltage is obtained, or the power supply voltage obtained by separation can be subjected to noise isolation processing through the noise isolation unit, and then the power supply voltage obtained by noise isolation processing is filtered through the filtering unit, so that the first power supply voltage is obtained. The filtering is used for filtering high-frequency noise, and the noise isolation processing can comprise high-frequency noise suppression, transient overvoltage suppression protection and the like.
For example, the filter unit may employ a pi filter including a 10 μF ceramic capacitor, a 10 Ω@100MHz magnetic bead, and a 10 μF tantalum capacitor with an insertion loss of-40 dB@100MHz. The 10 mu F ceramic capacitor is a temperature compensation ceramic capacitor, has good temperature stability and high-frequency characteristics, is mainly used for filtering high-frequency noise, and can provide lower impedance at a high frequency band, so that high-frequency noise signals can be effectively bypassed. The 10 mu F tantalum capacitor has higher capacitance density and good stability, is suitable for low-frequency filtering, can further filter low-frequency noise in a power supply, and can realize a filtering effect in a wider frequency range by being matched with a ceramic capacitor. The magnetic beads are high-frequency inductance elements, and the impedance of the magnetic beads increases with the increase of frequency. When the magnetic bead with the impedance of 10 omega is 100MHz, the magnetic bead with the impedance of 10 omega can effectively inhibit the passing of high-frequency noise, and in the pi-type filter, the magnetic bead provides higher impedance at a high frequency band to prevent the high-frequency noise from entering a subsequent circuit. Insertion loss refers to the degree of attenuation of a signal after it has passed through a filter. The insertion loss of 40dB@100MHz means that the filter can attenuate noise signals to 1/10000 of the original noise signals at the frequency of 100MHz, so that the pi-type filter has strong noise suppression capability at the frequency of 100MHz, high-frequency noise in a power supply can be effectively reduced, and the purity of the power supply is improved.
The noise isolation unit may include a high impedance bead and a transient voltage suppressor. The high-resistance anti-magnetic beads can provide higher impedance at a high frequency band, so that the propagation of high-frequency noise is effectively restrained, the coupling and propagation of noise are reduced, the noise on a power line can be further isolated through the high-resistance anti-magnetic beads, the noise is prevented from being propagated from one circuit part to another circuit part, and the anti-interference capability of the whole system is improved. The transient voltage suppressor is used for suppressing transient overvoltage (such as lightning stroke, electric arc and the like), can be rapidly conducted when the overvoltage occurs, clamps the overvoltage at a safe level, and therefore protects a subsequent circuit from damage, clamps the overvoltage within a safe range in a short time, and accordingly protects the circuit from damage caused by the overvoltage.
The filtering unit and the noise isolation unit can effectively reduce power supply noise and improve the quality and stability of a power supply, so that reliable guarantee is provided for normal operation of electronic equipment. The first power supply voltage output by the power supply separation module 12 is transmitted through the power line, so that the OCP power supply of the first processor and the signal transmission of the second processor are separated, and the conflict with the main board power supply is avoided.
Further, the power ground of the power supply separation module 12 is connected with the signal ground of the signal relay module 11 through a single point of 0 omega resistor, so that effective isolation between the power ground and the signal ground is realized, interference of power supply noise on a signal line is reduced, and signal integrity and reliability are improved. In this embodiment, the 0Ω resistor is essentially a conductor that serves to connect the power ground and the signal ground in the circuit, ensuring that the two are electrically connected. In addition, although the resistance value of the 0Ω resistor is close to zero, it still has a certain parasitic inductance and parasitic capacitance under the high-frequency signal, and these parasitic parameters can isolate the high-frequency noise to a certain extent, and prevent the high-frequency noise from propagating between the power supply ground and the signal ground through the ground path. In some occasions needing hot plug, the 0 omega resistor can limit the impact of instantaneous current and protect the circuit from damage. The 0Ω resistor can be conveniently removed or replaced during the circuit design and debug phase to facilitate testing and optimizing the circuit's ground strategy.
In some embodiments of the present application, the power separation module 12 further includes a power protection unit for cutting off the input of the power supply voltage in response to the network card migration request.
In particular, network card migration refers to the fact that in some multiprocessor or distributed systems, a network card may migrate from one processor to another, which migration may be due to load balancing, failover, or other system management policies. When a network card migration request is detected, it means that the network card is about to switch from one processor to another, which may result in a sudden change in power demand.
The power supply separation module 12 of the first adapter card 10 can adopt an electronic fuse to realize intelligent power distribution management, and judges whether a network card migration request is received by monitoring the current of an OCP interface (network card interface) of the first processor, when the network card migration request is detected, 12V main power supply is cut off within 10ms, 3.3V standby power supply is reserved, and meanwhile, a back-to-back MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) is integrated to prevent the power supply of the second processor side from flowing backwards to the first processor. By cutting off the input of the power supply voltage, the overload or damage of the power supply can be prevented in the migration process of the network card, and the stable operation of the system can be ensured. Meanwhile, a standby power supply of 3.3V is maintained, and the system can be prevented from being completely powered off, so that the operation can be quickly recovered after the main power supply is recovered, and the time and complexity of restarting the system are reduced. In addition, the back-to-back MOSFET is a circuit structure formed by two MOSFETs, and can prevent the second processor side power supply from flowing backwards to the first processor in the power supply switching process, and the flowing backwards can cause power supply short circuit or other faults, so that the isolation of the power supply is realized through the back-to-back MOSFET.
In some embodiments of the present application, the second riser card 20 includes a signal reforming module 21, an input end of the signal reforming module 21 is connected to a communication port of a first input end of the second riser card 20, an output end of the signal reforming module 21 is adapted to be connected to a communication port of an output end of the second riser card 20, for receiving the first communication signal and performing signal loss compensation on the first communication signal to generate a second communication signal, a voltage converting module 22, an input end of the voltage converting module 22 is connected to a power supply port of a first input end of the second riser card 20, and an output end of the voltage converting module 22 is adapted to be connected to a power supply port of an output end of the second riser card 20, for receiving the first power supply voltage and performing voltage conversion on the first power supply voltage to generate a second power supply voltage, wherein the second communication signal and the second power supply voltage are integrated at the output end of the second riser card 20 to obtain the second output signal.
Specifically, the signal reforming module 21 is configured to compensate for signal attenuation of the first communication signal due to long-distance transmission, so as to obtain a second communication signal, for example, the signal attenuation compensation can be performed on the received first communication signal by using the signal relay chip, so as to output the second communication signal. The voltage conversion module 22 is configured to convert the first power supply voltage to a target voltage adapted to a target network card, so as to adapt to a PCIe power supply requirement of the second processor, thereby integrating a network card interface of the second adapter card 20 (i.e. an output end of the second adapter card 20) with the second communication signal to generate a second output signal, and outputting the signal through the target network card.
In this embodiment, the communication signal and the power supply in the first output signal of the first processor are separately transmitted in an isolated manner, and the second adapter card 20 performs signal and voltage processing respectively and then performs integrated output, so that the signal quality of the first processor is ensured, and meanwhile, the first adapter card is adapted to the target network card, thereby meeting the requirement of dynamic matching application.
In some embodiments of the present application, the signal reforming module 21 includes a signal redrive unit for performing high frequency gain compensation on the first communication signal based on the initial gain to generate the second communication signal.
Specifically, the received first communication signal is subjected to high-frequency gain compensation by the signal redrive unit to offset attenuation of high-frequency components during cable transmission, for example, the initial gain is set to 6dB for compensating high-frequency attenuation of the first 8-inch cable. The initial gain may be set according to the actual situation.
The embodiment can redrive and condition the received first communication signal through the signal redrive unit to enhance signal quality so that it can be transmitted more stably and reliably.
In some embodiments of the present application, the signal redrive unit is further configured to adjust the initial gain based on the signal transmission error rate test result, so as to perform high frequency gain compensation on the first communication signal based on the adjusted initial gain.
Specifically, bit Error Rate (BER) test is a method for evaluating the performance of a digital communication system, which quantifies signal quality by measuring the ratio of the number of erroneous bits occurring during transmission to the total number of transmission bits. The signal transmission error rate can be calculated by generating a known test signal and detecting an error in the signal at the receiving end. For example, the signal redrive unit sets the initial gain to 6dB to compensate for the high frequency attenuation of the first 8 inch cable, and sets the 5-step tap to cancel the inter-symbol interference (Inter Symbol Interference, ISI). Based on the BER test results, the gain (-3.5 dB to-6 dB) is dynamically adjusted to further optimize the signal quality.
The embodiment dynamically adjusts the compensation gain based on the signal transmission error rate test result so as to further improve the transmission quality and reliability of the signal.
In some embodiments of the present application, the voltage conversion module 22 includes a step-down unit for reducing the first supply voltage to a target voltage to generate the second supply voltage.
That is, in the case that the power supply separation module 12 outputs the first power supply voltage through filtering and noise isolation, the voltage reduction unit in the voltage conversion module 22 reduces the first power supply voltage (12V) to 3.3V/5V required by the target network card, so as to obtain the second power supply voltage for signal integration.
Referring to fig. 3, in some embodiments of the present application, the second adapter card 20 further includes a hot plug key for triggering a hot plug request, and sending the hot plug request to the second processor, so that the second processor triggers a hot plug control procedure based on the hot plug request.
That is, the second adapter card 20 supports the hot plug function, and hot plug means that the hardware component can be safely plugged in or plugged out when the device is running, without affecting the normal operation of the system. For the network card adapter card, the hot plug function allows a user to safely plug in or plug out the network card under the condition of not closing the power supply of the system, so that the availability and the efficiency maintenance of the system are improved.
The second adapter card 20 is provided with a communication interface connected to the communication interface of the second processor, and can communicate with the second processor through an EDID (Extended Display Identification Data ) protocol.
The hot plug key may be a physical button disposed on the front panel or the side of the second adapter card 20, and the user may trigger the hot plug operation by pressing the button. Specifically, after the user presses the hot plug key, a hot plug request is sent to the second processor based on communication, and after the second processor receives the hot plug request, the following hot plug control flow operation is executed to ensure that the second adapter card realizes a hot plug function, and the specific hot plug control flow is as follows:
Cutting off the power supply of the network card, ensuring that electric arc is not generated or a circuit is not damaged when the network card is inserted or pulled out;
Disabling signal channel, namely disabling signal channel of network card to prevent signal interference or damage;
updating the system state, namely updating the internal state of the system and recording the inserting or extracting operation of the network card;
The indicator lights indicate that the system feeds back the state of the hot plug operation to the user through the indicator lights. For example, when the indicator light turns green, it means that the network card can be safely inserted or extracted;
Inserting or extracting the network card, namely, the user inserts or extracts the network card safely according to the prompt of the indicator lamp;
And (3) recovering the system, namely, after the network card is inserted, the system can supply power again and enable the signal channel, and recovering the normal work of the network card.
The embodiment realizes the hot plug function based on the hot plug key, and allows a user to safely plug in or plug out the network card without turning off the power supply of the system. This feature ensures that the system or network card is not damaged during hot plug through a series of security mechanisms such as power management, signal isolation, and software support. The hot plug function has important significance in the scenes of frequent maintenance and network card replacement of a data center, a server, an industrial control system and the like, and can improve the availability and maintenance efficiency of the system.
Further, the second riser card 20 also supports PCIe 4.0/5.0 protocols for interfacing with other interfaces of the second processor.
As an embodiment of the present application, as shown in connection with fig. 1-3, the hardware of the network card connection circuit 100 is configured to insert the first adapter card 10 into the OCP 3.0 interface of the first processor and fix it to the server back window. The output end of the adapter card 1 is connected with the input end of the second adapter card 20 through a custom cable. The second riser card 20 is inserted into the Slimline interface reserved on the motherboard, i.e. the data interface of the second processor.
The signal processing flow of the network card connection circuit 100 is that PCIe signals of the first processor are transmitted to the second adapter card 20 through the shielding differential line after being relayed by the first adapter card 10. The Re-driver chip of the second adapter card 20 shapes the signal and sends it to the network card interface of the second processor.
The power supply management flow of the network card connection circuit 100 is that the first adapter card 10 obtains the 12V power supply from the OCP interface and transmits the 12V power supply to the second adapter card 20 through the independent power supply line. The second adapter card 20 is built with a DC-DC (Direct Current-Direct Current) module to convert 12V into 3.3V/5V required by the target network card.
In addition, the power supply separation module 12 of the first adapter card 10 adopts eFuses (electronic fuses) to realize intelligent power distribution management, monitors OCP interface current of the first processor, cuts off 12V main power supply within 10ms when a network card migration request is detected, reserves 3.3V standby power supply, integrates back-to-back MOSFET, and prevents the second processor side power supply from flowing backwards to the first processor.
The second patch card 20 carries a Re-driver chip and performs adaptive equalization. The receiving end CTLE (Continuous TIME LINEAR Equalization) has initial gain=6dB to compensate the high-frequency attenuation of the cable of 8 inches, 5 taps to eliminate inter-code interference (ISI) and dynamic adjustment (-3.5 dB to-6 dB) according to BER test.
Thus, in this embodiment, the first switch card 10 connected to the first processor is used for separating PCIe signals and power, the second switch card 20 connected to the second processor is used for integrating signal reforming and voltage conversion functions, and signals and power are independently transmitted through a shielding cable connected to the two switch cards.
The network card connection circuit 100 is based on the OCP network card cross-CPU resource dynamic allocation of the double adapter cards, and at least the following beneficial effects can be achieved:
And load balancing, namely flexibly distributing the OCP network card to the idle CPU, and improving the resource utilization rate. The optimal matching of the OCP network card equipment and the target CPU (namely the second processor) can be realized by combining NUMA (Non-Uniform Memory Access, non-uniform memory access structure) topological structure characteristics according to the PCIe channel utilization rate, the memory bandwidth occupancy rate and the calculation load index of each CPU. Under the typical service scene of a two-way server, the cross-CPU resource allocation can improve the utilization rate of the whole resource and reduce the network delay fluctuation at the same time;
The hardware level can be compatible with the standard specification of the OCP NIC 3.0, the specially designed mechanical structure keeps the original server case layout, the definition of the adapter card golden finger is completely compatible with the standard OCP slot, the main stream server architecture is supported, and the main board design is not required to be modified;
The cost advantage is that the complex high-speed exchange chip and the matched clock buffer circuit are omitted through the signal-power supply separation architecture, and the hardware cost is reduced.
In summary, the network card connection circuit of the embodiment of the application receives the first output signal sent by the corresponding first processor through the first adapter card, separates the communication signal and the power supply voltage in the first output signal to obtain the first communication signal and the first power supply voltage, and sends the first communication signal and the first power supply voltage to the first input end of the second processor through the communication line and the power supply line respectively, the second adapter card integrates the received first communication signal and the first power supply voltage to obtain the second output signal, sends the second output signal based on the target network card, and is also used for receiving the third output signal sent by the second processor to send the third output signal through the target network card for communication transmission of the second processor. That is, the network card interface of the first processor may be connected to the target network card corresponding to the second processor through the first switching circuit and the second switching circuit, so that the network card interface may be used for communication transmission of the second processor through the target network card, and may also be used for communication transmission requirement of the first processor, where when the resources of the first processor are insufficient, the target network card corresponding to the second processor can be multiplexed through the first transfer card and the second transfer card, so that communication transmission is carried out based on the target network card, and therefore, the technical problem of communication transmission delay of the OCP network card when the CPU resource is insufficient can be solved, the technical effect of dynamically distributing the target network card across the CPU resource and improving the load balance is achieved.
The application also provides a server corresponding to the embodiment.
As shown in fig. 4, the server 1000 according to the embodiment of the present application includes a plurality of processors, where the plurality of processors includes the second processor 200 and the first processor 300, and the network card connection circuit 100 described above.
In the server 1000, a plurality of network card connection circuits 100 may be set according to requirements, and each network card connection circuit 100 may correspond to one second processor 200 and one first processor 300 respectively, or may correspond to one second processor 200 and one first processor 300, which is not limited in particular.
In some embodiments of the application, the second processor 200 is determined based on the utilization of each of the plurality of processors.
Specifically, the utilization rate of each processor may be determined through a physical link connection condition, for example, when there are more devices such as a hard disk network card connected to the processor, the CPU utilization rate is considered to be higher, or the operating system checks in real time through a command, so that the utilization rate value of each CPU can be seen, and a processor with a lower utilization rate is selected as the second processor 200.
Therefore, the server 1000 can realize load balancing, flexibly distribute the OCP network card to the idle CPU, and improve the resource utilization rate. Specifically, the matching effect of the target network card and the second processor can be realized by combining NUMA (Non-Uniform Memory Access, non-uniform memory access structure) topological structure characteristics according to the PCIe channel utilization rate, the memory bandwidth occupancy rate and the calculation load index of each CPU.
In summary, the server of the embodiment of the application realizes the network card sharing between the first processor and the second processor through the network card connecting circuit, namely, the network card interface of the first processor is connected with the target network card at the second processor through the network card connecting circuit, so that the network card interface can be used for communication transmission of the second processor through the target network card, can also be used for communication transmission requirement of the first processor, and can be used for communication transmission based on the target network card when the resource of the first processor is insufficient, thereby solving the technical problem of communication transmission delay of the OCP network card when the CPU resource is insufficient, and achieving the technical effects of dynamically distributing the target network card across the CPU resource and improving the load balance.
From the description of the above embodiments, it will be clear to a person skilled in the art that the method according to the above embodiments may be implemented by means of software plus the necessary general hardware platform, but of course also by means of hardware, but in many cases the former is a preferred embodiment.
Those of skill would further appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative elements and steps are described above generally in terms of functionality in order to clearly illustrate the interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
The network card connecting circuit and the server provided by the application are described in detail. The principles and embodiments of the present application have been described herein with reference to specific examples, the description of which is intended only to facilitate an understanding of the method of the present application and its core ideas. It should be noted that it will be apparent to those skilled in the art that various modifications and adaptations of the application can be made without departing from the principles of the application and these modifications and adaptations are intended to be within the scope of the application as defined in the following claims.
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| CN206312134U (en) * | 2016-12-29 | 2017-07-07 | 郑州云海信息技术有限公司 | A kind of switching device suitable for multipath server |
| US10110551B1 (en) * | 2017-08-14 | 2018-10-23 | Reza Toghraee | Computer-implemented system and methods for providing IPoE network access using software defined networking |
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| CN114490475A (en) * | 2021-12-30 | 2022-05-13 | 苏州浪潮智能科技有限公司 | A PCI-E transfer card, network card access method, device, equipment and medium |
| CN118263712A (en) * | 2022-12-26 | 2024-06-28 | 超聚变数字技术有限公司 | Male connector, female connector, connector assembly and computing device |
| CN116069709A (en) * | 2023-01-06 | 2023-05-05 | 超聚变数字技术有限公司 | Server system and network card integrated device |
| CN118897816B (en) * | 2024-09-24 | 2025-01-21 | 苏州元脑智能科技有限公司 | Server control method, server, device, medium and product based on network card |
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