CN120379244A - Memory array, preparation method thereof, memory and electronic equipment - Google Patents

Abstract

The present application provides a storage array and a preparation method thereof, a storage device, and an electronic device, which relates to the field of semiconductor technology and aims to improve the arrangement density of the storage array. The storage array includes a plurality of storage cells arranged in an array, and each storage cell includes a capacitor and a transistor. Among them, the capacitor includes a first electrode, a dielectric layer, and a second electrode, the first electrode is arranged around the second electrode, and the dielectric layer is located between the first electrode and the second electrode. The transistor is arranged on the capacitor, and the transistor includes a channel layer, a gate dielectric layer, and a gate layer, the gate layer surrounds the side of the channel layer, and the gate dielectric layer is located between the channel layer and the gate layer. The channel layer contacts the second electrode, the channel layer includes a first surface in contact with the second electrode, the second electrode includes a second surface in contact with the channel layer, and the boundary of the first surface coincides with the boundary of the second surface. The storage array can be applied to a memory to realize reading and writing of data.

Description

Memory array, preparation method thereof, memory and electronic equipment

Technical Field

The present application relates to the field of semiconductor technologies, and in particular, to a memory array, a method for manufacturing the memory array, a memory, and an electronic device.

Background

The dynamic random access memory (Dynamic Random Access Memory, DRAM) is one of the mainstream memories by virtue of its high speed, high density, low latency, etc.

At present, the size shrinkage of the DRAM achieves the bottleneck, and how to improve the arrangement density of the storage array in the memory to achieve the size shrinkage of the device becomes a problem to be solved in the field.

Disclosure of Invention

The embodiment of the application provides a memory array, a preparation method thereof, a memory and electronic equipment, and aims to improve the arrangement density of the memory array.

In order to achieve the above purpose, the embodiment of the present application adopts the following technical scheme:

In a first aspect, a memory array is provided that includes a plurality of memory cells arranged in an array, each memory cell including a capacitor and a transistor. The capacitor comprises a first electrode, a dielectric layer and a second electrode, wherein the first electrode is arranged around the second electrode, and the dielectric layer is positioned between the first electrode and the second electrode. The transistor is arranged on the capacitor and comprises a channel layer, a gate dielectric layer and a gate layer, wherein the gate layer surrounds the side face of the channel layer, and the gate dielectric layer is arranged between the channel layer and the gate layer. The channel layer is in contact with the second electrode, the channel layer includes a first surface in contact with the second electrode, the second electrode includes a second surface in contact with the channel layer, and a boundary of the first surface coincides with a boundary of the second surface.

The memory array provided by the embodiment of the application comprises a plurality of memory cells arranged in an array manner, wherein in the capacitor of each memory cell, the first electrode is arranged around the second electrode, and the dielectric layer is arranged between the first electrode and the second electrode, so that the capacitor has a columnar capacitance structure. The transistor is arranged on the capacitor and comprises a channel layer, a gate dielectric layer and a gate layer, wherein the gate layer surrounds the side face of the channel layer, so that the control capability of the gate layer on the channel layer is improved, and the window of the operating voltage of the transistor is increased. The gate dielectric layer is located between the channel layer and the gate layer, and the transistor has a vertical transistor structure.

The columnar capacitor structure is smaller than the plane capacitor structure in plane size, and the vertical transistor structure is smaller than the plane transistor structure in plane size, so that the plane size of the memory cells is reduced, the number of memory cells in unit area is increased, and the arrangement density of the memory array is improved.

The channel layer of the transistor is contacted with the second electrode of the capacitor, the channel layer comprises a first surface contacted with the second electrode, the second electrode comprises a second surface contacted with the channel layer, the boundary of the first surface is coincident with the boundary of the second surface, namely, the positions and the sizes of the end parts contacted with the channel layer and the second electrode are the same, the channel layer and the second electrode are aligned, the alignment precision is higher, the stable connection of the transistor and the capacitor is ensured, and the arrangement density of the memory array is improved.

In some embodiments, the memory array further includes a plurality of word lines, the plurality of memory cells arranged in an array include a plurality of rows and a plurality of columns, gate layers of the plurality of transistors in one row of memory cells are connected to form one word line, the word lines include conductive connection layers between gate layers of two adjacent transistors, and surfaces of the conductive connection layers far away from the capacitor are recessed toward a direction close to the capacitor, so that a cross-sectional area of the conductive connection layers is smaller, and materials used for preparing the word lines can be saved.

Or the conductive connecting layer fills the gap area between the grid electrode layers of the two adjacent transistors, so that the cross-sectional area of the word line is larger, the resistance of the word line is reduced, and the voltage drop of the voltage signal transmitted on the word line is reduced.

In some embodiments, the memory array further includes a plurality of bit lines, each bit line being disposed on a side of the transistor away from the capacitor, each bit line being electrically connected to channel layers of the plurality of transistors in a column of memory cells, an end of the channel layer connected to the bit line being a source of the transistor.

In some embodiments, the memory array further includes a plate line disposed on a side of the capacitor remote from the transistor, the first electrodes of the plurality of capacitors in the plurality of memory cells being electrically connected to the plate line.

In some embodiments, the memory cell includes a plurality of capacitors and a transistor, first electrodes of the plurality of capacitors are stacked and spaced apart along a direction in which the capacitors are directed toward the transistor, and second electrodes of the plurality of capacitors are connected to form a pillar electrode. The channel layer of the transistor is connected to one end of the columnar electrode.

In some embodiments, along the direction of the capacitor pointing to the transistor, the memory array includes a plurality of memory structures stacked, each of the memory structures includes a plurality of memory cells arranged in an array, and the three-dimensional stacking of the plurality of memory structures is beneficial to improving the arrangement density of the memory array.

In some embodiments, the material of the dielectric layer comprises a ferroelectric material, in which case the capacitor formed by the first electrode, the dielectric layer and the second electrode is a ferroelectric capacitor.

In a second aspect, a method for fabricating a memory array is provided, the method comprising forming an insulating layer having a plurality of vias on a substrate, the plurality of vias being arranged in an array. And forming a first electrode, a dielectric layer and a second electrode in the via hole, wherein the first electrode is positioned on the surface of the via hole, the dielectric layer is positioned on the inner side of the first electrode, the second electrode is positioned on the inner side of the dielectric layer, and the surface of the second electrode, which is far away from the substrate, is lower than the surface of the insulating layer, which is far away from the substrate. A barrier layer is formed in the via hole, the barrier layer being located inside the dielectric layer and on a side of the second electrode remote from the substrate. And removing the insulating layer, the first electrode and the dielectric layer to expose the barrier layer. And forming a gate dielectric layer and a gate layer on the side surface of the barrier layer.

According to the preparation method provided by the embodiment of the application, the insulating layer with the plurality of through holes is formed on the substrate, the first electrode, the dielectric layer and the second electrode are formed in the through holes, the first electrode is positioned on the surface of the through holes, the dielectric layer and the second electrode are sequentially positioned on the inner side of the first electrode, and the first electrode, the dielectric layer and the second electrode form a columnar capacitor structure. And the top surface of the second electrode is lower than the top surface of the insulating layer, namely, in the process of preparing the columnar capacitor structure, cavities are synchronously formed in the through holes.

A barrier layer is then formed in the cavity within the via, the barrier layer also being located inside the dielectric layer and the barrier layer being located over the second electrode. Finally, removing the insulating layer, the first electrode and the dielectric layer to expose the barrier layer and forming a gate dielectric layer and a gate electrode layer on the side surface of the barrier layer. The blocking layer may be used as a channel layer, a blocking layer, a gate dielectric layer, and a gate layer of a transistor, or the blocking layer may be used as a sacrificial layer, and the blocking layer may be replaced with a channel layer, the gate dielectric layer, and the gate layer forming a transistor.

It can be seen that both the barrier layer and the second electrode are located inside the dielectric layer, and the barrier layer is located above the second electrode, so that in the direction parallel to the substrate, the positions and dimensions of the barrier layer and the second electrode are defined by the same dielectric layer, i.e. the positions and dimensions of the channel layer and the second electrode are defined by the same dielectric layer, so that the positions and dimensions of the channel layer and the second electrode are the same, and the "self-alignment" of the channel layer and the second electrode is realized.

Compared with the method of adopting an exposure development process to etch the channel hole on the gate layer to form the channel layer, the method of the application needs to align the channel hole with the second electrode, and the process of automatic alignment of the channel layer and the second electrode does not need to adopt the exposure development process, so that the preparation process is relatively simple and controllable, and is beneficial to reducing the process difficulty and the cost.

In some embodiments, forming the first electrode, the dielectric layer, and the second electrode within the via includes forming the first electrode at a surface of the via. A dielectric layer is formed on the inner side of the first electrode. A conductive material is deposited and a fill layer is formed on the inside of the dielectric layer. And removing the part of the filling layer, which is far away from the substrate, and forming a first cavity in the via hole, wherein the reserved part of the filling layer forms a second electrode, so that the first cavity is synchronously formed in the via hole in the process of preparing the columnar capacitor structure.

Forming a barrier layer in the via includes forming a barrier layer in the first chamber, the barrier layer in contact with the second electrode, the barrier layer being in the same location as the second electrode, and the ends of the barrier layer in contact with the second electrode being the same size.

In some embodiments, forming the gate dielectric layer and the gate layer on sides of the barrier layer includes forming a gate dielectric film and a gate film on an outer side of the barrier layer, the gate dielectric film including at least a first portion on a side of the barrier layer away from the substrate, and a second portion on a side of the barrier layer, the gate film including at least a third portion on a side of the barrier layer away from the substrate, and a fourth portion on a side of the barrier layer. And removing the third part of the gate film, removing the first part of the gate dielectric film, taking the reserved second part as the gate dielectric layer, taking the fourth part as the gate layer, and exposing the surface of the barrier layer far away from one side of the substrate so as to facilitate the formation of bit lines on the surface of the barrier layer or replacing the barrier layer with a channel layer.

In some embodiments, the plurality of vias includes a plurality of rows and a plurality of columns, the plurality of barrier layers within the plurality of vias includes a plurality of rows and a plurality of columns, and after forming the gate dielectric layer and the gate layer on sides of the barrier layers, a first mask layer is formed, the first mask layer having a plurality of first openings, each first opening exposing the gate layer on sides of a row of the barrier layers. And depositing a conductive material, forming a conductive connection layer between the barrier layers in the same row through the first opening, and connecting the conductive connection layer with the grid layers on the side surfaces of the barrier layers to form a word line.

In some embodiments, the gate film further includes a fifth portion on a surface of the insulating layer, the fifth portion being connected to the gate layer on a side of the plurality of barrier layers, and a second mask layer is formed after forming the gate dielectric layer and the gate layer on the side of the barrier layers, the second mask layer having a plurality of second openings, each second opening exposing a region between two adjacent rows of barrier layers. And removing a part of the fifth part of the gate film through the second opening, wherein the part reserved by the fifth part and the gate layer on the side surface of the barrier layer in the same row form a word line together.

In some embodiments, the blocking layer is directly used as a channel layer of a transistor, the transistor comprises the blocking layer, the gate dielectric layer and the gate layer, and a bit line can be directly formed on the surface of the blocking layer, so that the process steps for preparing the channel layer are simplified.

In some embodiments, the barrier layer is used as a sacrificial layer, and after forming the gate dielectric layer and the gate layer on the side of the barrier layer, the barrier layer is removed to form the second chamber. And forming a channel layer of the transistor in the second chamber, wherein the transistor comprises the channel layer, the gate dielectric layer and the gate layer, so that the blocking layer is replaced by the channel layer, the channel layer can be prevented from being formed in advance, and the channel layer is damaged by etching in the process of forming the gate dielectric layer and the gate layer, thereby being beneficial to improving the film quality of the channel layer and the electrical property of the transistor.

In a third aspect, a memory is provided that includes a memory array in any of the embodiments described above, and a controller electrically connected to the memory array.

In a fourth aspect, an electronic device is provided, such as a consumer electronic product, a home electronic product, a vehicle-mounted electronic product, a financial terminal product, a communication electronic product. The electronic device comprises a circuit board and the memory in the above embodiment, which is electrically connected to the circuit board.

It can be appreciated that the memory and the electronic device provided by the embodiments of the present application may refer to the advantages of the memory array described above, and will not be described herein.

Drawings

In order to more clearly illustrate the technical solutions of the present application, the drawings that are required to be used in some embodiments of the present application will be briefly described below, and it is apparent that the drawings in the following description are only drawings of some embodiments of the present application, and other drawings may be obtained according to these drawings to those of ordinary skill in the art. Furthermore, the drawings in the following description may be regarded as schematic illustrations, and are not limiting of the actual size of the product, the actual flow of the method, etc. according to the embodiments of the present application.

Fig. 1 is a schematic diagram of an electronic device according to an embodiment of the present application;

fig. 2 is an exploded view of an electronic device according to an embodiment of the present application;

FIG. 3 is a schematic diagram of a memory according to an embodiment of the present application;

FIG. 4 is a circuit diagram of a memory array according to an embodiment of the present application;

FIGS. 5A and 5B are flowcharts illustrating the preparation of a memory array according to embodiments of the present application;

Fig. 6A to fig. 6S are block diagrams corresponding to each step of a method for manufacturing a memory array according to an embodiment of the present application;

Fig. 7A to fig. 7D are block diagrams corresponding to steps of another method for manufacturing a memory array according to an embodiment of the present application;

fig. 8A to 8F are block diagrams corresponding to steps of another method for manufacturing a memory array according to an embodiment of the present application;

FIG. 9 is a cross-sectional view along plane X-Z of a memory array according to an embodiment of the present application;

FIG. 10 is a cross-sectional view along plane Y-Z of a memory array according to an embodiment of the present application;

fig. 11 is a block diagram of another memory array according to an embodiment of the present application.

Detailed Description

The following description of the embodiments of the present application will be made more apparent and fully hereinafter with reference to the accompanying drawings, in which some, but not all embodiments of the application are shown. All other embodiments obtained by a person skilled in the art based on the embodiments provided by the present application fall within the scope of protection of the present application.

Some embodiments of the present application provide an electronic device, which may be, for example, a mobile phone, a tablet computer, a Personal digital assistant (Personal DIGITAL ASSISTANT, PDA), a television, a smart wearable product (e.g., a smart watch, a smart bracelet), a Virtual Reality (VR) terminal device, an augmented Reality (Augmented Reality, AR) terminal device, a rechargeable household small-sized appliance (e.g., a soymilk machine, a sweeping robot), an unmanned aerial vehicle, a radar, an aerospace device, a vehicle-mounted device, and other different types of user devices or terminal devices, and may also be a network device such as a base station. The embodiment of the present application is not particularly limited to the specific form of the electronic device.

Fig. 1 is a schematic diagram of an electronic device according to an embodiment of the present application.

Referring to fig. 1, the electronic device 1 includes a storage 11, a processor 12, an input device 13, an output device 14, and the like. Those skilled in the art will appreciate that the architecture of the electronic device 1 shown in fig. 1 does not constitute a limitation of the electronic device 1, and the electronic device 1 may include more or fewer components than those shown in fig. 1, or may combine some of the components shown in fig. 1, or may be arranged differently than the components shown in fig. 1.

The storage device 11 is used for storing software programs and modules. The storage means 11 mainly includes a storage program area that can store and back up an operating system, application programs required for at least one function (such as a sound playing function, an image playing function, etc.), etc., and a storage data area that can store data created according to the use of the electronic device 1 (such as audio data, image data, a phonebook, etc.), etc. Further, the storage device 11 includes an external memory 111 and an internal memory 112. The data stored in the external memory 111 and the internal memory 112 can be transferred to each other.

The external memory 111 may include, for example, a hard disk, a usb disk, a floppy disk, and the like. The internal memory 112 may include, for example, dynamic random access memory (Dynamic Random Access Memory, DRAM), static random access memory (Static Random Access Memory, SRAM), resistance change memory (RESISTANCE RANDOM ACCESS MEMORY, RRAM), phase change memory (PHASE CHANGE Random Access Memory, PCRAM), ferroelectric random access memory (Ferroelectric Random Access Memory, feRAM), ferroelectric field Effect Transistor (FeFET) memory, ferroelectric tunnel junction (Ferroelectric Tunnel Junction, FTJ) memory, NAND flash memory (NAND FLASH), and the like.

The processor 12 is a control center of the electronic device 1, connects respective parts of the entire electronic device 1 using various interfaces and lines, and performs various functions of the electronic device 1 and processes data by running or executing software programs and/or modules stored in the storage device 11, and calling data stored in the storage device 11. Alternatively, the processor 12 may include one or more processing units. For example, processor 12 may include an application processor (Application Processor, AP), a modem processor, a graphics processor (Graphics Processing Unit, GPU), and the like. Wherein the different processing units may be separate devices or may be integrated in one or more processors. For example, processor 12 may integrate an application processor that primarily handles operating systems, user interfaces, applications, etc., with a modem processor that primarily handles wireless communications. It will be appreciated that the modem processor described above may not be integrated into the processor 12. The application processor may be, for example, a central processing unit (Central Processing Unit, CPU). In fig. 1, the processor 12 is taken as an example of a CPU, and the CPU may include an operator 121 and a controller 122. The arithmetic unit 121 acquires data stored in the internal memory 112, processes the data stored in the internal memory 112, and normally returns the processed result to the internal memory 112. The controller 122 may control the arithmetic unit 121 to process data, and the controller 122 may also control the external memory device 111 and the internal memory 112 to read or write data.

The input device 13 is used to receive input numeric or character information and to generate key signal inputs related to user settings and function control of the electronic device. By way of example, the input device 13 may include a touch screen, as well as other input devices. Touch screens, also known as touch panels, collect touch operations by a user on or near the touch screen (e.g., operations by a user on or near the touch screen using any suitable object or accessory such as a finger, stylus, etc.), and actuate the corresponding connection device according to a predetermined program. The controller 122 in the processor 12 may also control the input device 13 to receive an input signal or not. Further, the entered number or character information received by the input device 13, as well as key signal inputs generated in connection with user settings and function controls of the electronic device, may be stored in the internal memory 112.

The output device 14 is for outputting an input of the input device 13 and storing a signal corresponding to the data in the internal memory 112. For example, the output device 14 outputs a sound signal or a video signal. The controller 122 in the processor 12 may also control the output device 14 to output signals or not.

The thick arrow in fig. 1 is used to indicate the transmission of data, and the direction of the thick arrow indicates the direction of data transmission. For example, a single arrow between the input device 13 and the internal memory 112 indicates that data received by the input device 13 is transferred to the internal memory 112. For another example, double-headed arrows between the operator 121 and the internal memory 112 indicate that data stored in the internal memory 112 may be transferred to the operator 121, and data processed by the operator 121 may be transferred to the internal memory 112. Thin arrows in fig. 1 represent components that can be controlled by the controller 122. Illustratively, the controller 122 may control the external memory device 111, the internal memory 112, the operator 121, the input device 13, the output device 14, and the like.

Fig. 2 is an exploded view of an electronic device according to an embodiment of the present application.

Referring to fig. 2, taking the electronic device 1 as an example of a mobile phone, the electronic device 1 includes a middle frame 15, a rear shell 16, and a display screen 17, the rear shell 16 and the display screen 17 are respectively located on two opposite sides of the middle frame 15, the middle frame 15 includes a carrying board 150, and a frame 151 surrounding the carrying board 150 for a week, where the carrying board 150 is used to carry the display screen 17.

With continued reference to fig. 2, the electronic device 1 may further include a circuit board 18, the circuit board 18 being disposed on a side of the carrier board 150 proximate to the rear case 16, and the internal memory 112 in the electronic device 1 may be disposed on the circuit board 18, the internal memory 112 being electrically connected to the circuit board 18.

At present, DRAM is one of the mainstream memories, which can be used as the internal memory 112, and fig. 3 is a schematic diagram of a memory according to an embodiment of the present application.

Referring to fig. 3, the internal memory 112 includes a memory array 21, a row decoding circuit 22, a column decoding circuit 23, a timing control circuit 24, a read-write control circuit 25, and a sense amplifier 26.

The memory array 21 includes a plurality of memory cells 210 arranged in an array, where the plurality of memory cells 210 includes a plurality of rows arranged along a first direction X and a plurality of columns arranged along a second direction Y. The first direction X intersects the second direction Y, e.g. perpendicular to each other.

The timing control circuit 24 is electrically connected to the row decoding circuit 22, the column decoding circuit 23, the memory array 21, the read-write control circuit 25, and the sense amplifier 26, respectively, and the timing control circuit 24 is configured to perform timing control of the respective circuits.

The row decode circuit 22 is electrically connected to the memory array 21, and the row decode circuit 22 is configured to gate the memory cells 210 of the corresponding row according to the row address to address the memory cells 210 of the corresponding row.

The column decoding circuit 23 is electrically connected to the memory array 21, and after the memory cells 210 of the corresponding row are strobed, the column decoding circuit 23 is configured to address the memory cells 210 of the corresponding column according to the column address, thereby selecting the memory cells 210 that need to perform a read operation or a write operation.

The read/write control circuit 25 is electrically connected to the memory array 21, and the read/write control circuit 25 is configured to control the selected memory cell 210 to perform a read operation or a write operation.

The sense amplifier 26 is electrically connected to the memory array 21, and the sense amplifier 26 is configured to read, amplify and output data information stored in the selected memory cell 210 to implement a data read operation, or input a data signal to the selected memory cell 210 to implement a data write operation.

Fig. 4 is a circuit diagram of a memory array according to an embodiment of the present application.

Referring to fig. 4, the memory array 21 further includes a plurality of Word Lines (WL) extending in the direction X, a plurality of Bit lines (Bit lines, BL) extending in the direction Y, and a plurality of plate lines (PLATE LINE, PL) extending in the direction Y, each row of memory cells 210 is electrically connected to one of the Word lines WL, and each column of memory cells 210 is electrically connected to one of the Bit lines BL and one of the plate lines PL.

With continued reference to fig. 4, the memory cell 210 may have a 1T1C (1-Transistor-1-Capacitor) structure, that is, the memory cell 210 includes a Transistor T having a gate electrically connected to the word line WL, a source electrically connected to the bit line BL, a drain electrically connected to one electrode of the Capacitor C, and the other electrode of the Capacitor C electrically connected to the plate line PL, and the circuit architecture of the memory cell 210 in the embodiment of the present application is not limited thereto.

The embodiment of the application provides a preparation method of a memory array, fig. 5A and 5B are flowcharts of the preparation of the memory array, and fig. 6A-6S are structure diagrams corresponding to steps of the preparation method of the memory array.

Referring to fig. 5A, the method for preparing the memory array includes the following steps S1 to S5:

in fig. 6A, (B) is a sectional view taken along the sectional line A-A ', and in fig. 6B, (B) is a sectional view taken along the sectional line B-B'.

Referring to fig. 6A and 6B, a first insulating layer 31 having a plurality of vias H arranged in an array is formed on a substrate 30, for example, the plurality of vias H include a plurality of rows and a plurality of columns, each row of vias H being aligned in a direction X and each column of vias H being aligned in a direction Y.

Illustratively, referring to fig. 6A, a plate line PL is first formed on a substrate 30, and an insulating layer 31 is formed over the plate line PL. Then, referring to fig. 6B, the first insulating layer 31 is etched using a photolithography process to form a plurality of vias H on the first insulating layer 31, the bottoms of the vias H exposing the plate line PL.

Illustratively, the plurality of vias H arranged in an array includes a plurality of rows and a plurality of columns, each row of vias H being aligned along the direction X and each column of vias H being aligned along the direction Y.

S2 referring to fig. 6C and 6D, a first electrode 32, a dielectric layer 33 and a second electrode 34 are formed in the via hole H, the first electrode 32 is located on the surface of the via hole H, the dielectric layer 33 is located inside the first electrode 32, the second electrode 34 is located inside the dielectric layer 33, the first electrode 32, the dielectric layer 33 and the second electrode 34 form a capacitor C, the second electrode 34 is surrounded by the first electrode 32, the first electrode 32 may be referred to as a "bottom electrode", the second electrode 34 may be referred to as a "top electrode", and the capacitor C has a "columnar capacitance structure".

The surface P1 of the second electrode 34 on the side away from the substrate 30 is lower than the surface P2 of the first insulating layer 31 on the side away from the substrate 30 with respect to the substrate 30, i.e., the surface P1 of the second electrode 34 is smaller in height than the surface P2 of the first insulating layer 31 with respect to the substrate 30 to form the first chamber C1 in the via hole H.

In some examples, referring to fig. 5B, S2 may include S21 to S24 as follows:

S21 referring to fig. 6C, a first electrode 32 is formed on the surface of the via hole H, and the first electrode 32 is connected to the plate line PL at the bottom of the via hole H.

Illustratively, the electrode material may be deposited over the entire surface to form the first electrode 32, and the first electrode 32 may cover the surface of the via H, and may also cover the surface P2 of the first insulating layer 31 on the side away from the substrate 30.

S22 referring to fig. 6C, a dielectric layer 33 is formed inside the first electrode 32.

Illustratively, a dielectric material may be deposited over the entire surface to form a dielectric layer 33, the dielectric layer 33 covering the first electrode 32, and the dielectric layer 33 being located inside the first electrode 32 within the via H.

Illustratively, the material of the dielectric layer 33 may include a dielectric material.

Illustratively, the material of the dielectric layer 33 may comprise a ferroelectric material, in which case the capacitor C formed by the first electrode 32, the dielectric layer 33 and the second electrode 34 is a ferroelectric capacitor.

Continuing with fig. 6C, a conductive material is deposited to form a fill layer 340 on the inside of dielectric layer 33 to fill via H.

S24 referring to fig. 6C and 6D, a portion of the filling layer 340 away from the substrate 30 is removed to form a first chamber C1 in the via H, and a remaining portion of the filling layer 340 forms the second electrode 34, so that the first chamber C1 is simultaneously formed in the via H during the process of manufacturing the capacitor C.

Illustratively, a back etch (etch) process may be used to etch down the fill layer 340 to form a first chamber C1, the first chamber C1 subsequently being used to form a barrier layer (channel layer of transistor T), the first chamber C1 defining the dimensions of the channel layer, or alternatively, the etch depth of the fill layer 340 being dependent on the height of the channel layer.

S3 referring to fig. 6E and 6F, a barrier layer 35 is formed in the via H, the barrier layer 35 being located inside the dielectric layer 33, and the barrier layer 35 being located on a side of the second electrode 34 remote from the substrate 30.

It will be appreciated that the plurality of vias H includes a plurality of rows and a plurality of columns such that the plurality of barrier layers 35 within the plurality of vias H includes a plurality of rows and a plurality of columns, each row of barrier layers 35 being aligned along the direction X and each column of barrier layers 35 being aligned along the direction Y.

Illustratively, referring to fig. 6E and 6F, a sacrificial material or channel material may be deposited over the entire surface, forming a barrier film 350 within the first chamber C1. Then, the upper surface of the barrier film 350 is polished by a Chemical Mechanical Polishing (CMP) process until the surface P2 of the first insulating layer 31, the first electrode 32, and the dielectric layer 33 are exposed, and the remaining portion of the barrier film 350 forms the barrier layer 35.

With continued reference to fig. 6F, the barrier layer 35 is in contact with the second electrode 34, the barrier layer 35 includes a first surface M1 in contact with the second electrode 34, the second electrode 34 includes a second surface M2 in contact with the barrier layer 35, and the boundary of the first surface M1 coincides with the boundary of the second surface M2, i.e., the size of the end portion of the barrier layer 35 in contact with the second electrode 34 is the same.

It will be appreciated that within the same via H, the barrier layer 35 is located inside the dielectric layer 33, the second electrode 34 is also located inside the dielectric layer 33, and the barrier layer 35 is located above the second electrode 34. On plane X-Y, the position and dimensions of the barrier layer 35 and the second electrode 34 are defined by the dielectric layer 33 within the same via H, such that the barrier layer 35 is the same as the second electrode 34 in position and dimension, achieving "self-alignment" of the barrier layer 35 and the second electrode 34.

S4 referring to fig. 6F and 6G, a portion of the first insulating layer 31 located outside the barrier layer 35 is removed, a portion of the first electrode 32 located outside the barrier layer 35 is removed, and a portion of the dielectric layer 33 located outside the barrier layer 35 is removed, exposing the barrier layer 35.

Illustratively, first insulating layer 31 is etched first to remove the portion of first insulating layer 31 outside barrier layer 35 to expose the portion of first electrode 32 outside barrier layer 35. Then, the first electrode 32 is etched to remove a portion of the first electrode 32 located outside the barrier layer 35 to expose a portion of the dielectric layer 33 located outside the barrier layer 35. Finally, dielectric layer 33 is etched, removing the portion of dielectric layer 33 outside barrier layer 35 to expose the sides of barrier layer 35.

It is understood that the material of the barrier layer 35 has a larger etching selectivity ratio with the material of the first insulating layer 31, the first electrode 32 and the dielectric layer 33, so that the barrier layer 35 is not damaged by etching during the process of etching the first insulating layer 31, the first electrode 32 and the dielectric layer 33, so as to retain the barrier layer 35.

S5 referring to FIG. 6H to FIG. 6L, a gate dielectric layer 36 and a gate layer 37 are formed on the side surfaces of the barrier layer 35.

Illustratively, referring to fig. 6H, a gate dielectric material is deposited over the gate dielectric material using an atomic layer deposition (Atomic Layer Deposition) process, forming a gate dielectric film 360 on the outside of the barrier layer 35.

Referring to fig. 6I, a conductive material is deposited over the entire surface of the gate dielectric film 360 to form a gate film 370, wherein the gate dielectric film 360 includes a first portion a1 on a side of the barrier layer 35 remote from the substrate 30, and a second portion a2 on a side of the barrier layer 35. The gate thin film 370 includes a third portion a3 located at a side of the barrier layer 35 remote from the substrate 30, and a fourth portion a4 located at a side of the barrier layer 35.

Referring to fig. 6I and 6J, the third portion a3 of the gate film 370 is removed, the fourth portion a4 of the gate film 370 forms the gate layer 37, the gate layer 37 surrounds the side surface of the barrier layer 35, and after the channel layer of the transistor T is formed subsequently, the control capability of the gate layer 37 on the channel layer is improved, so that the window of the operating voltage of the transistor T is increased.

For example, the gate film 370 may be etched downward using a dry etching process, and in removing the third portion a3 of the gate film 370, a portion of the gate film 370 located on the surface of the first insulating layer 31 may be also removed, so that the gate layers 37 located on the sides of the plurality of barrier layers 35 are disconnected.

Referring to fig. 6K, a dielectric material is deposited over the entire surface, forming a second insulating layer 38 on the outside of the barrier layer 35, the second insulating layer 38 acting as a fill to facilitate subsequent grinding.

Referring to fig. 6K and 6L, the upper surface of the second insulating layer 38 and the first portion a1 of the gate dielectric film 360 are polished by a chemical mechanical polishing process, and the first portion a1 of the gate dielectric film 360 is removed to expose the surface of the barrier layer 35 on the side away from the substrate 30, and the second portion a2 of the gate dielectric film 360 serves as the gate dielectric layer 36. And, the remaining portion of the second insulating layer 38 covers the gate layer 37.

In fig. 6M, (b) is a sectional view taken along the sectional line C-C'.

After S5, referring to fig. 6M, a first mask layer 39 is formed on the second insulating layer 38, for example, the first mask layer 39 may be photoresist, the first mask layer 39 may be exposed and developed, a plurality of first openings K1 are formed on the first mask layer 39, each first opening K1 extends in the direction X, each first opening K1 exposes one line of barrier layers 35 in the direction X, and portions of the second insulating layer 38 between the plurality of barrier layers 35 in the same line are exposed.

In fig. 6N, (b) is a sectional view taken along the sectional line D-D'.

Referring to fig. 6M and 6N, portions of the second insulating layer 38 between the plurality of barrier layers 35 of the same row are etched through the first openings K1 of the first mask layer 39, and portions of the second insulating layer 38 between the plurality of barrier layers 35 of the same row are removed such that each first opening K1 exposes the gate layer 37 of the side of one row of barrier layers 35.

In fig. 6O, (b) is a sectional view taken along the sectional line E-E'.

Referring to fig. 6O, a conductive material is deposited over the entire surface, and fills the gap regions G between the barrier layers 35 of the same row through the first openings K1 of the first mask layer 39, forming conductive connection layers 40, and the conductive connection layers 40 are connected to the gate layers 37 of the sides of the barrier layers 35.

In fig. 6P, (b) is a sectional view taken along the sectional line F-F' of (a).

Referring to fig. 6P, the conductive connection layer 40 is etched down by an etching back process, and a portion of the conductive connection layer 40 filled between two adjacent barrier layers 35 is reserved, the conductive connection layer 40 is connected in series with the gate layers 37 on the sides of the barrier layers 35 in the same row, so that a word line WL extending in the direction X is formed, the width W of the word line WL depends on the width of the first opening K1, and in the direction Y, the width of the first opening K1 may be greater than the size of the barrier layer 35, may be equal to the size of the barrier layer 35, or may be smaller than the size of the barrier layer 35, so that the width W of the word line WL may be greater than, equal to, or smaller than the size of the barrier layer 35.

Since the conductive connection layer 40 fills the gap region G between the plurality of barrier layers 35, the surface P3 of the word line WL away from the capacitor C is flush, and the cross-sectional area of the word line WL in the Y direction is large, which is beneficial to reducing the resistance of the word line WL, thereby reducing the voltage drop of the voltage signal transmitted on the word line WL.

In fig. 6Q, (b) is a sectional view taken along the sectional line G-G ', and (c) is a sectional view taken along the sectional line H-H'.

Referring to fig. 6Q, a dielectric material is deposited over the entire surface, forming a third insulating layer 41, the third insulating layer 41 covering the plurality of word lines WL.

In FIG. 6R, (b) is a sectional view taken along section line I-I 'and (c) is a sectional view taken along section line J-J'.

Referring to fig. 6Q and 6R, the upper surface of the third insulating layer 41 is polished using a chemical mechanical polishing process until the upper surface of the barrier layer 35 is exposed.

In FIG. 6S, (b) is a sectional view taken along section line K-K 'and (c) is a sectional view taken along section line L-L'.

Referring to fig. 6S, a plurality of bit lines BL are formed, each of the bit lines BL extends in the direction Y, and each of the bit lines BL is connected to the same column barrier layer 35.

Illustratively, a dielectric material is deposited over the entire surface to form the fourth insulating layer 42. The fourth insulating layer 42 is then etched using an exposure development process to form a via, which exposes the barrier layer 35. Finally, a bit line BL is formed in the via hole of the fourth insulating layer 42.

It will be appreciated that the material of the barrier layer 35 is selected from a suitable channel material, so that the barrier layer 35 can be directly used as the channel layer of the transistor T, and the process steps for preparing the channel layer can be simplified.

The transistor T includes a barrier layer 35, a gate dielectric layer 36 and a gate layer 37, the barrier layer 35 is a vertical channel structure extending along a direction Z, the gate layer 37 is located on a side of the barrier layer 35, the gate dielectric layer 36 is located between the barrier layer 35 and the gate layer 37, and the transistor T has a "vertical transistor structure".

The gate layer 37 serves as the gate of the transistor T, which gate layer 37 is part of the word line WL, i.e. the gate of the transistor T is electrically connected to the word line WL. The end of the blocking layer 35 connected to the bit line BL is the source of the transistor T. The blocking layer 35 is connected to the second electrode 34, and the end of the blocking layer 35 connected to the second electrode 34 is the drain of the transistor T, which is connected to the capacitor C to form a memory cell 210.

According to the foregoing, the positions and the dimensions of the barrier layer 35 and the second electrode 34 are the same, and the barrier layer 35 and the second electrode 34 are "self-aligned", and since the barrier layer 35 can be directly used as the channel layer of the transistor T, the positions and the dimensions of the channel layer and the second electrode 34 are the same, so that the "self-alignment" of the channel layer and the second electrode 34 is realized, and the alignment accuracy of the channel layer and the second electrode 34 is higher, thereby ensuring the stable connection of the transistor T and the capacitor C.

Compared with the method of forming the channel layer by etching the channel hole on the gate layer by using the exposure developing process, the method of manufacturing the capacitor C of the present application requires aligning the channel hole with the second electrode, the capacitor C has a columnar capacitor structure, the columnar capacitor structure has a smaller occupied area on the plane X-Y than the plane capacitor structure, the transistor T has a vertical transistor structure, the vertical transistor structure has a smaller occupied area on the plane X-Y than the plane transistor structure, which is favorable for reducing the occupied area of the memory cell 210 on the plane X-Y, and the precision of the channel layer of the transistor T and the second electrode 34 is higher, which is favorable for increasing the number of the memory cells 210 arranged on the plane X-Y per unit area, increasing the arrangement density of the memory array 21, and making the memory array 21 reach the cell Size of 4F2, wherein "F" is the minimum Feature Size (Feature Size) of the chip manufacturing process, and "4F 2" refers to twice the square of the minimum Feature Size (4f2=2f2f).

In addition, the process of automatically aligning the channel layer with the second electrode 34 does not need to adopt an exposure and development process, and only adopts two exposure and development processes in the process of preparing the word line WL and the bit line BL, so that the preparation process is relatively simple and controllable, and the process difficulty and cost are reduced.

The embodiment of the application also provides another preparation method of the memory array, and fig. 7A to 7D are block diagrams corresponding to each step of the another preparation method of the memory array.

In fig. 7A, (B) is a sectional view taken along a sectional line A-A ', and (C) is a sectional view taken along a sectional line B-B', and in fig. 7B, (B) is a sectional view taken along a sectional line C-C ', and (C) is a sectional view taken along a sectional line D-D'.

Referring to fig. 7A, the structure of fig. 7A may be formed by using the preparation steps of fig. 6A to 6R in the aforementioned preparation method, and the upper surface of the barrier layer 35 is exposed.

Unlike the preparation method shown in fig. 6A to 6S, the material of the barrier layer 35 in the preparation method in this embodiment may not be used as the material of the channel layer, but may be a sacrificial material, for example, the material of the barrier layer 35 may include silicon nitride. Therefore, referring to fig. 7A and 7B, the barrier layer 35 is removed with the barrier layer 35 as a sacrificial layer, forming a second chamber C2, the second chamber C2 exposing the second electrode 34 thereunder.

It will be appreciated that the material of the barrier layer 35 has a larger etching selectivity than the material of the second insulating layer 38 and the third insulating layer 41, and therefore, the second insulating layer 38 and the third insulating layer 41 are not damaged by etching during the process of etching the barrier layer 35.

In fig. 7C, (b) is a sectional view taken along the sectional line E-E ', and (C) is a sectional view taken along the sectional line F-F'.

Referring to fig. 7C, a channel layer 43 of the transistor T is formed in the second chamber C2, the channel layer 43 is connected to the second electrode 34, and the channel layer 43, the gate dielectric layer 36, and the gate layer 37 form the transistor T.

In fig. 7D, (b) is a sectional view taken along the sectional line G-G ', and (c) is a sectional view taken along the sectional line H-H'.

Referring to fig. 7D, a plurality of bit lines BL are formed, each of the bit lines BL extends in the direction Y, and each of the bit lines BL is connected to the same column of channel layers 43.

It will be appreciated that the quality of the film of the channel layer 43 will affect the electrical performance of the transistor T, the better the quality of the film of the channel layer 43, the better the electrical performance of the transistor T.

By using the barrier layer 35 as the sacrificial layer, after the gate dielectric layer 36 and the gate layer 37 are formed on the side surface of the barrier layer 35, the barrier layer 35 is removed to form the second cavity C2, and the channel layer 43 is formed in the second cavity C2, so that the replacement of the barrier layer 35 into the channel layer 43 is realized, the channel layer 43 can be prevented from being formed in advance, and etching damage is caused to the channel layer 43 in the process of forming the gate dielectric layer 36 and the gate layer 37, thereby being beneficial to improving the film quality of the channel layer 43 and improving the electrical property of the transistor T.

The embodiment of the application also provides another preparation method of the memory array, and fig. 8A to 8F are block diagrams corresponding to steps of the preparation method of the memory array according to the embodiment of the application, different from the preparation method shown in fig. 6A to 6S, the embodiment provides another preparation method of the word line WL.

Referring to fig. 8A, the structure of fig. 8A may be formed by using the preparation steps of fig. 6A to 6I in the preparation method described above, and forming a gate dielectric film 360 and a gate film 370 on the outer side of the barrier layer 35, where the gate dielectric film 360 includes a first portion a1 on the side of the barrier layer 35 away from the substrate 30, and a second portion a2 on the side of the barrier layer 35. The gate thin film 370 includes a third portion a3 located at a side of the barrier layer 35 away from the substrate 30, a fourth portion a4 located at a side of the barrier layer 35, and a fifth portion a5 located at a surface of the first insulating layer 31, the fifth portion a5 being connected to the fourth portion a 4.

Referring to fig. 8B, a dielectric material is deposited over the entire surface to form a fifth insulating layer 44 overlying the gate film 370, the fifth insulating layer 44 acting as a fill to facilitate subsequent grinding.

Referring to fig. 8B and 8C, the upper surface of the fifth insulating layer 44, the third portion a3 of the gate thin film 370, and the first portion a1 of the gate dielectric thin film 360 are polished using a chemical mechanical polishing process, and the third portion a3 of the gate thin film 370 and the first portion a1 of the gate dielectric thin film 360 are removed to expose the upper surface of the barrier layer 35. The fourth portion a4 of the gate film 370 serves as the gate layer 37 and the second portion a2 of the gate dielectric film 360 serves as the gate dielectric layer 36.

In fig. 8D, (b) is a sectional view taken along the sectional line A-A'.

Referring to fig. 8D, the second mask layer 45 is formed, for example, the second mask layer 45 may be photoresist, the second mask layer 45 may be exposed and developed, a plurality of second openings K2 are formed on the second mask layer 45, each of the second openings K2 extends along the direction X, and each of the second openings K2 exposes a region (fifth insulating layer 44) between two adjacent rows of barrier layers 35.

In fig. 8E, (B) is a sectional view taken along the sectional line B-B ', and (C) is a sectional view taken along the sectional line C-C'.

Referring to fig. 8D and 8E, the fifth insulating layer 44 is etched through the second opening K2 of the second mask layer 45 to expose the fourth and fifth portions a4 and a5 of the gate thin film 370. Then, the fifth portion a5 of the gate film 370 is etched through the second opening K2 of the second mask layer 45, and a portion of the fifth portion a5 of the gate film 370 is removed, so that the gate film 370 is disconnected in the direction Y, the portion remaining in the fifth portion a5 is used as a conductive connection layer to form a plurality of word lines WL extending in the direction X together with the fourth portion a4 (the gate layer 37 on the side of the same row of barrier layers 35), and the surface P3 of the fifth portion a5 away from the capacitor C is recessed in the direction V near the capacitor C, so that the cross-sectional area of the word lines WL in the direction Y is smaller, and materials for preparing the word lines can be saved.

In fig. 8F, (b) is a sectional view taken along the sectional line D-D ', and (c) is a sectional view taken along the sectional line E-E'.

Referring to fig. 8F, a dielectric material is deposited over the entire surface to form a sixth insulating layer 46 covering barrier layer 35 and gate layer 37. Then, a plurality of vias 47 are formed on the sixth insulating layer 46, the vias 47 exposing the upper surface of the barrier layer 35. Finally, a plurality of bit lines BL are formed, each of the bit lines BL extending in the direction Y, and each of the bit lines BL is connected to the same column of barrier layers 35.

According to the preparation method provided by the embodiment of the application, the chemical mechanical polishing process is adopted to grind the gate film 370 to form the gate layer 37, and the gate layer 37 is disconnected in the direction Y by etching to form a plurality of word lines WL, so that the preparation process of the word lines WL is simplified, and the process cost is reduced.

The embodiment of the application also provides a storage array, fig. 9 is a cross-sectional view along a plane X-Z of the storage array provided by the embodiment of the application, and fig. 10 is a cross-sectional view along a plane Y-Z of the storage array provided by the embodiment of the application.

Referring to fig. 9 and 10, along direction Z, the memory array 21 includes a plurality of memory structures 211 stacked, any one or more of the plurality of memory structures 211 being fabricated using the fabrication methods described above.

The memory array 21 is a three-dimensional memory array, and each memory structure 211 includes a plurality of memory cells 210 arranged in an array, so that the number of the memory cells 210 arranged in a unit area on the plane X-Y is increased, and the arrangement density of the memory array 21 is increased through three-dimensional stacking.

Illustratively, referring to FIG. 9, the memory array 21 further includes a word line connection structure 48, the word line connection structure 48 extending through the plurality of memory structures 211 disposed in a stack. In the direction Z, a plurality of word lines WL in the plurality of memory structures 211 correspond, and the corresponding plurality of word lines WL are connected by the word line connection structure 48.

Similarly, referring to fig. 10, the memory array 21 further includes a bit line connection structure 49, and the bit line connection structure 49 extends through the plurality of memory structures 211 stacked. In the direction Z, a plurality of bit lines BL in the plurality of memory structures 211 correspond, and the corresponding plurality of bit lines BL are connected by the bit line connection structure 49.

The embodiment of the application also provides a storage array, and fig. 11 is a structural diagram of another storage array provided by the embodiment of the application.

Referring to fig. 11, the memory array 21 includes a plurality of memory cells 210 arranged in an array, and the memory cells 210 may have a 1TnC (1-transmitter-n-Capacitor) structure, n being an integer greater than 1, i.e., the memory cells 210 include a Transistor T and a plurality of capacitors C.

The first electrodes 32 of the plurality of capacitors C are stacked and spaced apart in the direction Z, the second electrode 34 of each capacitor C extends through the first electrode 32 thereof, and the second electrodes 34 of the plurality of capacitors C are connected. For example, the second electrodes 34 of the plurality of capacitors C are integrally provided to form the columnar electrode 50. The channel layer 43 of the transistor T is connected to the second electrodes 34 (tips of the columnar electrodes 50) of the plurality of capacitors C.

It will be appreciated that the memory array 21 may also be fabricated by the fabrication method described above, and that the positions and dimensions of the channel layer 43 and the columnar electrode 50 are defined by the same dielectric layer 33 on the plane X-Y, so that the positions and dimensions of the channel layer 43 and the columnar electrode 50 are the same, and the "self-alignment" of the channel layer 43 and the columnar electrode 50 is achieved.

The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any changes or substitutions easily contemplated by those skilled in the art within the scope of the present invention should be included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims (16)

1. A memory array, comprising a plurality of memory cells arranged in an array, the memory cells comprising capacitors and transistors;

The capacitor includes a first electrode, a dielectric layer, and a second electrode, the first electrode disposed around the second electrode, the dielectric layer is located between the first electrode and the second electrode;

the transistor is arranged on the capacitor and comprises a channel layer, a gate dielectric layer and a gate layer, wherein the gate layer surrounds the side face of the channel layer, and the gate dielectric layer is positioned between the channel layer and the gate layer;

wherein the channel layer is in contact with the second electrode, the channel layer includes a first surface in contact with the second electrode, the second electrode includes a second surface in contact with the channel layer, and a boundary of the first surface coincides with a boundary of the second surface.

2. The memory array of claim 1, further comprising a plurality of word lines;

the array-type arranged memory cells comprise a plurality of rows and a plurality of columns, and gate layers of a plurality of transistors in one row of memory cells are connected to form one word line;

The word line comprises a conductive connection layer positioned between gate layers of two adjacent transistors, wherein the surface of the conductive connection layer, which is far away from the capacitor, is recessed towards the direction close to the capacitor, or the conductive connection layer fills a gap region between the gate layers of two adjacent transistors.

3. The memory array of claim 1 or 2, further comprising a plurality of bit lines disposed on a side of the transistor remote from the capacitor;

The plurality of memory cells arranged in an array comprises a plurality of rows and a plurality of columns, and each bit line is electrically connected with channel layers of a plurality of transistors in one column of memory cells.

4. A memory array according to any one of claims 1 to 3, further comprising a plate line disposed on a side of the capacitor remote from the transistor;

First electrodes of a plurality of capacitors in the plurality of memory cells are electrically connected to the plate line.

5. The memory array of any one of claims 1-4, wherein the memory cell comprises a plurality of the capacitors and one of the transistors;

Along the direction that the capacitor points to the transistor, the first electrodes of the capacitors are stacked and arranged at intervals, and the second electrodes of the capacitors are connected to form columnar electrodes;

the channel layer of the transistor is connected with one end of the columnar electrode.

6. The memory array according to any one of claims 1 to 5, wherein the memory array includes a plurality of memory structures arranged in a stack along a direction in which the capacitor is directed toward the transistor, each of the memory structures including a plurality of the memory cells arranged in an array.

7. The memory array of any one of claims 1-6, wherein the material of the dielectric layer comprises a ferroelectric material.

8. A method of manufacturing a memory array, comprising:

Forming an insulating layer with a plurality of through holes on a substrate, wherein the plurality of through holes are arranged in an array manner;

Forming a first electrode, a dielectric layer and a second electrode in the via hole, wherein the first electrode is positioned on the surface of the via hole, the dielectric layer is positioned on the inner side of the first electrode, and the second electrode is positioned on the inner side of the dielectric layer;

Forming a barrier layer in the via hole, wherein the barrier layer is positioned on the inner side of the dielectric layer and on one side of the second electrode away from the substrate;

Removing the part of the insulating layer, which is positioned outside the barrier layer, removing the part of the first electrode, which is positioned outside the barrier layer, and removing the part of the dielectric layer, which is positioned outside the barrier layer, to expose the barrier layer;

and forming a gate dielectric layer and a gate layer on the side surface of the barrier layer.

9. The method of manufacturing of claim 8, wherein forming a first electrode, a dielectric layer, and a second electrode within the via comprises:

forming the first electrode on the surface of the via hole;

forming the dielectric layer inside the first electrode;

depositing a conductive material, and forming a filling layer on the inner side of the dielectric layer;

removing a part of the filling layer, which is far away from the substrate, forming a first cavity in the via hole, and forming the second electrode by the reserved part of the filling layer;

Forming a barrier layer within the via, comprising:

the barrier layer is formed within the first chamber.

10. The method of claim 8 or 9, wherein forming a gate dielectric layer and a gate layer on sides of the barrier layer comprises:

forming a gate dielectric film and a gate film on the outer side of the barrier layer, wherein the gate dielectric film at least comprises a first part positioned on one side of the barrier layer away from the substrate and a second part positioned on the side surface of the barrier layer;

removing the third part of the gate film, removing the first part of the gate dielectric film, and exposing the surface of the barrier layer, which is far away from the substrate;

the second portion is used as the gate dielectric layer, and the fourth portion is used as the gate layer.

11. The method of manufacturing of claim 10, wherein the plurality of vias comprises a plurality of rows and a plurality of columns, and the plurality of barrier layers within the plurality of vias comprises a plurality of rows and a plurality of columns;

after forming the gate dielectric layer and the gate layer on the side surface of the barrier layer, the preparation method further comprises the following steps:

forming a first mask layer, wherein the first mask layer is provided with a plurality of first openings, and each first opening exposes a grid layer on the side surface of one row of barrier layers;

And depositing a conductive material, and forming a conductive connection layer between a plurality of barrier layers in the same row through the first opening, wherein the conductive connection layer is connected with gate layers on the side surfaces of the barrier layers to form word lines.

12. The method of manufacturing of claim 10, wherein the plurality of vias comprises a plurality of rows and a plurality of columns, and the plurality of barrier layers within the plurality of vias comprises a plurality of rows and a plurality of columns;

the gate film further comprises a fifth part positioned on the surface of the insulating layer, and the fifth part is connected with the gate layers on the side surfaces of the plurality of barrier layers;

after forming the gate dielectric layer and the gate layer on the side surface of the barrier layer, the preparation method further comprises the following steps:

Forming a second mask layer, wherein the second mask layer is provided with a plurality of second openings, and each second opening exposes a region between two adjacent rows of barrier layers;

And removing a part of a fifth part of the gate film through the second opening, wherein the part reserved by the fifth part and the gate layer on the side surface of the barrier layer in the same row form a word line together.

13. The method according to any one of claims 8 to 12, wherein the barrier layer is used as a channel layer of a transistor, and the transistor includes the barrier layer, the gate dielectric layer, and the gate layer.

14. The method according to any one of claims 8 to 12, wherein the barrier layer is used as a sacrificial layer, and after forming a gate dielectric layer and a gate layer on a side surface of the barrier layer, the method further comprises:

removing the barrier layer to form a second chamber;

and forming a channel layer of a transistor in the second chamber, wherein the transistor comprises the channel layer, the gate dielectric layer and the gate layer.

15. A memory, comprising:

The memory array of any one of claims 1-7;

And the storage array is electrically connected with the controller.

16. An electronic device, comprising:

The memory of claim 15;

And the memory is electrically connected with the circuit board.