CN120371622B

CN120371622B - Soft error injection method and FPGA chip

Info

Publication number: CN120371622B
Application number: CN202510864367.6A
Authority: CN
Inventors: 彭利泽; 吴林鑫; 贾弘翊; 韦嶔
Original assignee: XI'AN INTELLIGENCE SILICON TECHNOLOGY Inc
Current assignee: XI'AN INTELLIGENCE SILICON TECHNOLOGY Inc
Priority date: 2025-06-26
Filing date: 2025-06-26
Publication date: 2025-09-09
Anticipated expiration: 2045-06-26
Also published as: CN120371622A

Abstract

The present invention discloses a soft error injection method and an FPGA chip. The method is applied to the soft core IP of an FPGA chip. The injection interface of a soft error correction (SEC) hard core in the FPGA chip is encapsulated in the soft core IP. The method comprises: receiving a setting signal from a user to obtain setting information; generating soft error injection information based on the setting information; and sending the soft error injection information to the SEC hard core via the injection interface, so that the SEC hard core injects soft errors according to the soft error injection information. The present invention does not rely on the JTAG interface when performing soft error injection, occupies less FPGA resources, and has high injection efficiency.

Description

Soft error injection method and FPGA chip

Technical Field

The invention belongs to the technical field of integration, and particularly relates to a soft error injection method and an FPGA chip.

Background

With the ever-increasing size of Field-Programmable gate arrays (Field-Programmable GATE ARRAY, FPGA), the number and density of Static Random-Access memories (SRAMs) therein increases, and the probability of changing the programming logic behavior of the system due to internal Memory errors caused by electromagnetic radiation, external environmental disturbances, etc., but these errors generally do not permanently damage FPGA devices, which are called soft errors. To reduce the impact of soft errors on FPGA system functionality, soft error injection, detection (Soft Error Detect, SED) and error correction (Soft Error Correct, SEC) are typically integrated in larger scale FPGAs, allowing for the detection and correction of 1 bit data errors, as well as the detection of sequential multi-bit data errors.

In the FPGA development process, soft error injection can be used for simulating hardware faults caused by external radiation, not only can soft error detection and error correction functions be tested and verified, but also the fault tolerance, reliability, safety and performance of an FPGA system can be evaluated and optimized so as to meet the field with extremely strict industry standards, such as automobile electronics, medical equipment and the like. By intentionally injecting different soft errors into the FPGA system to simulate circuit faults of different types and degrees, a designer can evaluate the performance of the system in the face of various abnormal conditions, find and solve potential design defects in the system, find a fault-tolerant scheme which is most suitable for a specific application scene, improve the fault-tolerant capability of the system, thereby ensuring the stability and the robustness of the design, evaluate the influence of various soft errors on the performance of the FPGA, find the optimal performance configuration and parameter setting through simulating an optimization strategy, and further improve the overall performance and the power consumption efficiency of the FPGA.

In order to meet the requirements of evaluating and optimizing fault tolerance, reliability, safety, performance and the like of an FPGA system in a high-standard industry, the current popular soft Error injection method designs an independent soft Error injection IP core, an EMR (Error MESSAGE REGISTER) Unloader IP core, an ASD IP core, a soft Error injection debugger software interface and the like, although a user can inject 1 bit or multiple bit soft errors in a designated area according to the requirements, and the single bit Error position is compared with a sensitivity map to meet the field with extremely strict industry standards. However, when the functions of soft error injection, detection, correction, evaluation of fault tolerance capability, reliability and the like of the FPGA system are comprehensively realized, the following drawbacks still exist:

(1) Besides the design of more than three IP cores, the user also needs to instantiate the IP cores for soft error detection and correction, and the internal resources of the FPGA occupy larger resources, so that the resource space required by the actual system design is reduced, the interface is complex, and the use difficulty of the user is increased;

(2) The final soft error injection can be performed only by adopting a joint test working group (Joint Test Action Group, JTAG) interface through a software interface, the JTAG interface can perform soft error injection on only one position at a time, and if soft error injection on a plurality of positions is performed, repeated operation still needs to be performed by depending on JTAG, so that the efficiency is low.

Therefore, the current soft error injection method occupies more internal resources of the FPGA and has lower efficiency when being executed.

Disclosure of Invention

The embodiment of the invention provides a soft error injection method and a system, which can solve the problems that the current soft error injection method occupies more internal resources of an FPGA and has lower efficiency when being executed.

In a first aspect, an embodiment of the present invention provides a soft error injection method, where the method is applied to a soft core IP of an FPGA chip, and an injection interface of a soft error correction SEC hard core in the FPGA chip is encapsulated in the soft core IP, and the method includes:

Receiving a setting signal from a user to obtain setting information;

generating soft error injection information according to the setting information;

and sending the soft error injection information to the SEC hard core through the injection interface so that the SEC hard core can inject soft errors according to the soft error injection information.

In a second aspect, an embodiment of the present invention provides an FPGA chip, including a soft core IP and a soft error correction SEC hard core, and an injection interface of the SEC hard core is encapsulated in the soft core IP;

the soft core IP is used for receiving a setting signal from a user to obtain setting information, generating soft error injection information according to the setting information, and sending the soft error injection information to the SEC hard core through the injection interface;

the SEC hard core is used for injecting soft errors according to the soft error injection information.

Compared with the prior art, the soft error injection method has the advantages that the injection interface of the SEC hard core in the FPGA chip is packaged on the soft core IP (similar to a scheduler of a traditional method), the soft core IP can send the enabling signal to the SEC hard core through the injection interface, and the SEC hard core performs error injection at a soft error injection data address when detecting one rising edge of the enabling signal. When multi-address error injection is carried out, the soft core IP only needs to send a plurality of enabling signals, so that the injection efficiency can be improved. And the generation process of the soft error injection address is executed by the soft core IP, so that the resources of the FPGA are not occupied. The injection quantity of the soft error addresses can be set by a user according to the resource occupation condition of the FPGA. Most importantly, the invention does not depend on JTAG interface, does not need external tools such as JTAG downloader, software real-time controller and the like to carry out soft error injection, and can greatly improve injection efficiency.

Drawings

FIG. 1 is a schematic diagram of a soft error injection scenario according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of a remote soft error injection scenario according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of a generation interface according to an embodiment of the present invention;

fig. 4 is a schematic diagram of an interface of a SEC hard core according to an embodiment of the present invention;

FIG. 5 is a flowchart illustrating a soft error injection method according to an embodiment of the present invention;

fig. 6 is a schematic diagram of an FPGA chip according to an embodiment of the present invention.

Detailed Description

In the following description, for purposes of explanation and not limitation, specific details are set forth such as the particular system architecture, techniques, etc., in order to provide a thorough understanding of the embodiments of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present invention with unnecessary detail.

It should be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

It should also be understood that the term "and/or" as used in the present specification and the appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes such combinations.

As used in the present description and the appended claims, the term "if" may be interpreted as "when..once" or "in response to a determination" or "in response to detection" depending on the context. Similarly, the phrase "if a determination" or "if a [ described condition or event ] is detected" may be interpreted in the context of meaning "upon determination" or "in response to determination" or "upon detection of a [ described condition or event ]" or "in response to detection of a [ described condition or event ]".

Furthermore, the terms "first," "second," "third," and the like in the description of the present specification and in the appended claims, are used for distinguishing between descriptions and not necessarily for indicating or implying a relative importance.

Reference in the specification to "one embodiment" or "some embodiments" or the like means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the invention. Thus, appearances of the phrases "in one embodiment," "in some embodiments," "in other embodiments," and the like in the specification are not necessarily all referring to the same embodiment, but mean "one or more but not all embodiments" unless expressly specified otherwise. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless expressly specified otherwise.

Conventional soft-error injection methods typically implement soft-error injection through the JTAG interface. The soft error information is sent to the FPGA through a JTAG interface and the value of the designated address is modified through the JTAG interface, for example, 0x00001234 is modified to 0x00001235, so that soft error injection is realized.

Because JTAG interface can only send an address each time, if want to modify a plurality of addresses of the chip register, need to transmit soft error injection information many times, the repetitive operation is more, injection efficiency is lower.

In addition, when soft error injection is performed based on a JTAG interface by the traditional soft error injection method, soft error injection IP cores, ASD IP cores, unloader IP cores and debugger assistance are needed besides depending on a software interface, so that the resources of the FPGA are occupied greatly.

The present invention will be described in further detail with reference to specific examples, but embodiments of the present invention are not limited thereto.

Fig. 1 is a schematic diagram of a soft error injection scenario according to an embodiment of the present invention.

As an example, referring to fig. 1, if soft error injection is required for data 0x00001234 stored in the form of binary code "00000000 00000000 00010010 00110100", the SEC hard core will read this data, and when the address to be injected is read, for example, when the address where the last "0" is stored is read, the soft core IP sends an enable signal through the injection interface encapsulated therein, and pulls up a rising edge. The SEC hard core detects a rising edge and performs an error injection at this address, modifying "0" to "1" to "4" in 0x00001234 to "5".

FIG. 2 is a schematic diagram of a remote soft error injection scenario according to an embodiment of the present invention.

As an example, referring to fig. 2, a relatively large system is often composed of multiple small systems, and each has a respective core control module to implement nested control, such as the subsystem control center and the overall control center in fig. 2, which may be both composed of FPGAs. To ensure the reliability of the whole system, SEC functions are usually invoked at each of its control centers to ensure the stability of the configuration data. For example, robots have various complicated controls such as hands, feet and the like, the working temperatures of the hands, the feet and the like are high, or the working environments are bad, and the requirements on the stability of the system are high. The method for independently injecting soft errors into hands and feet of the robot and testing the fault tolerance and reliability of the small system is not beneficial to testing the chain reaction of the whole robot.

Because the injection interface of the SEC hard core is encapsulated in the soft core IP, the soft core IP sends soft error injection information to the SEC hard core based on the injection interface, and a JTAG pin of the debugger and the FPGA is not required to be connected in a wired mode. Therefore, referring to fig. 3, based on the method provided by the present invention, a user may select a verification mode, error data, a soft error injection address, etc. according to the requirement on a generation interface of an external remote control center, and the remote control center generates soft error injection information according to the configuration information and sends the soft error injection information to a general control center of the robot in a manner of injecting an error command. The highest-level total control center of the robot can send soft error injection information to the SEC hard core corresponding to the soft core IP through the injection interface, and the SEC hard core in the subsystem performs soft error injection according to the soft error injection information.

For example, the user may click on the generation interface in fig. 3, select the check mode to continuously check, check the automatic error correction function of the SEC hard core, check the mode of enabling signal to start error injection, select gaussian distribution, and generate soft error injection addresses, and inject errors at 150 addresses at a time.

Therefore, according to the soft error injection method provided by the invention, the injection interface of the SEC hard core in the FPGA chip is packaged on the soft core IP (similar to a scheduler of a traditional method), the soft core IP can send an enabling signal to the SEC hard core through the injection interface, and the SEC hard core performs error injection at a soft error injection data address when detecting a rising edge of the enabling signal. When multi-address error injection is carried out, the soft core IP only needs to send a plurality of enabling signals, and the data quantity of the enabling signals is far smaller than that of soft error injection information, so that the injection efficiency can be improved. And the generation process of the soft error injection address is executed by the soft core IP, so that the resources of the FPGA are not occupied. The injection quantity of the soft error addresses can be set by a user according to the resource occupation condition of the FPGA. Most importantly, the invention does not depend on JTAG interface, does not need external tools such as JTAG downloader, software real-time controller and the like to carry out soft error injection, and can greatly improve injection efficiency.

Fig. 4 is a schematic diagram of an interface of a SEC hard core according to an embodiment of the present invention.

Illustratively, the SEC hard core is an existing hardware module in the FPGA whose functions include verification, soft error injection, and correction functions. Its core interfaces may include SEDENABLE, SEDERR, SEDFRCERR, SEDDONE, ECCERR _ INJECT _ I, SEDINPROG, ECCERR _ INJECT _shf, AUTODONE in fig. 4.

Illustratively, SEDENABLE interface, SEDFRCERR interface, ECCERR _ INJECT _i interface, ECCERR _ INJECT _shf interface are all input interfaces. The SEDENABLE interface is used for starting and stopping SED check, starting SED check when the interface detects the rising edge of the signal, and stopping check when the interface detects the falling edge of the signal. The SEDFRCERR interface is an injection interface encapsulated in soft-core IP for receiving an enable signal. The ECCERR _ INJECT _i interface is an input end of a soft error injection address, and the ECCERR _ INJECT _shf interface is an error address information shift enabling interface, and the interface can enable the SEC hard core to perform error injection of a next address after detecting an enabling signal.

Illustratively, SEDERR interfaces, SEDDONE interfaces, SEDINPROG interfaces, AUTODONE interfaces are output interfaces. The SEDERR interface is configured to output an error flag signal that when high indicates that the SED hard core detected an SED unrepairable error. The SEDDONE interface is used to output a first work flag signal that indicates that a round of SED verification has been completed. The SEDINPROG interface is used for outputting a second working sign signal, and when the signal is high, the signal indicates that verification is in progress. The AUTODONE interface is configured to output a third working flag signal, where the signal is high, indicating that automatic repair is complete or no error is detected, and low, indicating that an error is being automatically repaired.

Fig. 5 is a flowchart illustrating an implementation of a soft error injection method according to an embodiment of the present invention. By way of example and not limitation, the method may be applied in a soft core IP of an FPGA chip in which an injection interface of a SEC hard core is encapsulated. The method may comprise steps S501-S503, each of which is described below.

S501, receiving a setting signal from a user to obtain setting information.

For example, referring to fig. 3, the user may click on a corresponding region in the generation interface, sending a setup signal to the soft-core IP.

In one possible implementation, referring to FIG. 3, the setup information may include a check mode, a number of soft error injections, a specified address, or a soft error injection address generation algorithm.

For example, the user may select a random algorithm as the soft error injection location generation algorithm to generate the soft error injection address or directly input the soft error injection specified address.

In one example, the soft error injection location generation algorithm may include a variety of random algorithms such as gaussian distribution, exponential distribution, beta distribution, and triangular distribution.

Illustratively, the distribution of soft-error injection addresses generated is related to the type of random algorithm, e.g., the distribution of soft-error injection addresses generated based on a gaussian distribution algorithm satisfies a gaussian distribution.

Alternatively, the soft error injection address in the present invention does not include a nonfunctional area (i.e., mask area).

The conventional technique always has no soft error detected as a result of the feedback injection regardless of whether the injection is successful or not, when the soft error is injected into the nonfunctional area. The invention avoids the region when soft error injection is performed, and is beneficial to improving the accuracy of the verification result.

S502, generating soft error injection information according to the setting information.

By way of example, the soft-error injection information may include at least one soft-error injection address and a soft-error injection logic control file. The soft error injection logic control file may control the SEC hard core to perform soft error injection at the soft error address.

S503, soft error injection information is sent to the SEC hard core through the injection interface, so that the SEC hard core can inject soft errors according to the soft error injection information.

In one example, a soft error injection address may be sent from the injection interface to the SEC hard core by way of an enable signal.

For example, referring to fig. 1, the SEC hard core may read data at the soft error injection address under the instruction of the soft error injection logic control file, and when the SEC hard core reads the soft error injection address, the enable signal received by the injection interface may generate a rising edge, and when the injection interface detects the rising edge, the SEC hard core may be instructed to perform error injection by the injection interface.

According to the invention, the injection interface of the SEC hard core in the FPGA chip is packaged on the soft core IP (similar to a scheduler of a traditional method), the soft core IP can send an enabling signal to the SEC hard core through the injection interface, and the SEC hard core performs error injection at a soft error injection data address when detecting a rising edge of the enabling signal. When multi-address error injection is carried out, the soft core IP only needs to send a plurality of enabling signals, so that the injection efficiency can be improved. And the generation process of the soft error injection address is executed by the soft core IP, so that the resources of the FPGA are not occupied. The injection quantity of the soft error addresses can be set by a user according to the resource occupation condition of the FPGA. Most importantly, the invention does not depend on JTAG interface, does not need external tools such as JTAG downloader, software real-time controller and the like to carry out soft error injection, and can greatly improve injection efficiency.

In some embodiments, chip 600 may include a soft core IP 610 and a SEC hard core 620.

Illustratively, the soft core IP 610 may be configured to receive a setting signal from a user to obtain setting information, generate soft error injection information according to the setting information, and send the soft error injection information to the SEC hard core 620 through the injection interface. SEC hard core 620 may be used to inject soft errors based on soft error injection information.

In the foregoing embodiments, the descriptions of the embodiments are focused on, and the details or descriptions of some embodiments may be found in the related descriptions of other embodiments.

Claims

1. A soft error injection method, characterized in that the method is applied to a soft core IP of an FPGA chip, wherein the injection interface of a soft error correction (SEC) hard core in the FPGA chip is encapsulated in the soft core IP, and the method comprises:

receiving a setting signal from a user and obtaining setting information, wherein the user sends the setting signal to the soft core IP by clicking a corresponding area in a generation interface;

Sending the soft error injection information to the SEC hard core through the injection interface, so as to enable the SEC hard core to inject soft errors according to the soft error injection information;

The soft error injection information includes at least one soft error injection address and a soft error injection logic control file, wherein the soft error injection logic control file is used to control the SEC hard core to perform soft error injection at the soft error injection address;

The setting information includes: verification mode, soft error injection quantity, designated address or soft error injection address generation algorithm;

The soft error injection address is the designated address, or is generated according to the soft error injection address generation algorithm;

The soft error injection address generation algorithm includes Gaussian distribution, exponential distribution, Beta distribution and triangular distribution random algorithms;

The soft error injection address does not include a non-functional area of the FPGA chip;

The injection interface is an enable signal interface, which is used to receive an enable signal and instruct the SEC hard core to inject a soft error when a rising edge of the enable signal is detected.

2. The method according to claim 1, characterized in that before receiving the setting signal from the user and obtaining the setting information, the method further comprises:

A generation interface for soft error injection information is displayed to the user, so that the user sends the setting signal based on the generation interface.

3. An FPGA chip, comprising a soft core IP and a soft error correction (SEC) hard core, wherein the injection interface of the SEC hard core is encapsulated in the soft core IP;

The soft core IP is used to: receive a setting signal from a user and obtain setting information, wherein the user sends the setting signal to the soft core IP by clicking a corresponding area in a generation interface; generate soft error injection information according to the setting information; and send the soft error injection information to the SEC hard core through the injection interface; wherein the soft error injection information includes at least one soft error injection address and a soft error injection logic control file, and the setting information includes: a verification mode, a soft error injection quantity, a specified address or a soft error injection address generation algorithm; the soft error injection logic control file is used to control the SEC hard core to perform soft error injection at the soft error injection address; the soft error injection address is the specified address, or is generated according to the soft error injection address generation algorithm; the soft error injection address generation algorithm includes Gaussian distribution, exponential distribution, Beta distribution and triangular distribution random algorithms; the soft error injection address does not include a non-functional area of the FPGA chip; the injection interface is an enable signal interface, used to receive an enable signal, and instruct the SEC hard core to inject a soft error when a rising edge of the enable signal is detected;

The SEC hard core is used to inject soft errors according to the soft error injection information.