CN120386421B - An on-chip integrated voltage regulator chip power supply circuit with adjustable output amplitude - Google Patents
An on-chip integrated voltage regulator chip power supply circuit with adjustable output amplitudeInfo
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- CN120386421B CN120386421B CN202510890726.5A CN202510890726A CN120386421B CN 120386421 B CN120386421 B CN 120386421B CN 202510890726 A CN202510890726 A CN 202510890726A CN 120386421 B CN120386421 B CN 120386421B
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Abstract
The invention belongs to the technical field of motorcycle voltage regulator chip circuits, and particularly relates to an on-chip integrated voltage regulator chip power supply circuit with adjustable output amplitude. The power supply system comprises a first power supply module, a second power supply module, an output voltage detection module and an output voltage regulation module, wherein the first power supply module is used for inputting a battery voltage signal BAT and three-phase electric signals PH 1-PH 3 to generate an on-chip power supply VCC, the power supply end of the second power supply module is connected with the power supply VCC to generate an on-chip reference voltage VREF, and meanwhile output voltages VP 1-VP 2 are respectively used for supplying power to a later-stage digital module and an analog module, the output voltage detection module is used for inputting the battery voltage signal BAT and detecting the voltage thereof to output a voltage signal VSEN to the output voltage regulation module, and the output voltage regulation module is used for regulating the output voltage. The invention realizes stable and reliable voltage output through the on-chip power supply generating circuit, the voltage detecting circuit and the voltage control circuit, and provides stable charging voltage for the load battery.
Description
Technical Field
The invention belongs to the technical field of motorcycle voltage regulator chip circuits, and particularly relates to an on-chip integrated voltage regulator chip power supply circuit with adjustable output amplitude.
Background
With the continuous miniaturization, integration and intelligent development of electronic equipment, the on-chip integrated voltage regulator chip is increasingly widely applied to various electronic products. In the field of motorcycles, a voltage regulator chip is required to stably adapt to complex voltage output by a magneto so as to supply power for an electric system of the whole vehicle. However, the existing on-chip integrated voltage regulator chip power circuit exposes a plurality of problems to be solved when facing diversified application scenes. Taking a traditional thyristor short-circuit voltage regulator as an example, a parallel voltage regulation mode is adopted, and when the output voltage is greater than the voltage regulation voltage, the thyristor is controlled to conduct and regulate the voltage. Under the condition of larger output power of the magneto, the heat load of the voltage regulator increases sharply. In order to ensure that the voltage regulator is not damaged due to overhigh temperature, the heat radiating area is required to be increased, so that the volume of the voltage regulator is greatly increased, the cost is obviously increased, and the voltage regulator is not suitable for a high-power voltage regulation scene. When the existing thyristor short-circuit voltage regulator outputs high power, the heat dissipation area is required to be increased continuously to cope with the heat load problem, and the practicability and the economy of the voltage regulator are seriously affected. The integrated voltage regulator chip in the chip also faces similar heat management problems when processing large current and high power, and the power device in the chip generates a large amount of heat in the working process, if the heat dissipation design is not good, the temperature of the chip is too high, and the performance and the reliability of the chip are further affected.
In terms of voltage regulation precision, the conventional contact voltage regulation power supply has a plurality of problems, such as the influence of factors such as the position precision of the electric brush, the contact resistance change and the like when the electric brush slides on the coil to regulate the voltage, and the voltage regulation precision is difficult to ensure. For an on-chip integrated voltage regulator chip power circuit, the feedback control mechanism may not be able to adjust the output voltage in a timely and accurate manner in the face of complex load variations. For example, when the electric equipment on the motorcycle is switched from a low-power indicator lamp to a high-power headlight, the load current instantaneously changes greatly, and part of the on-chip integrated voltage regulator chip can not quickly stabilize the output voltage at the target value, so that the voltage has larger fluctuation, and the normal operation of the electric equipment is affected. Like some early motorcycle voltage regulator chips, the output voltage can differ by as much as several volts during light and heavy loads, which is extremely detrimental to modern motorcycle electronics (e.g., electronic control units of fuel injection systems) that have high voltage stability requirements.
Electromagnetic compatibility is also a pain point for the power supply circuitry of the integrated voltage regulator chip on-chip. When the traditional silicon controlled rectifier voltage regulating mode works, current mutation can be generated at the moment of switching on and switching off the silicon controlled rectifier, so that larger electromagnetic interference is caused. When there is an inductive load (such as a motor, a relay, etc.) on the motorcycle, this electromagnetic interference is further exacerbated, resulting in unstable output voltages and even affecting the normal operation of other peripheral electronic devices. Although the on-chip integrated voltage regulator chip optimizes the circuit structure to a certain extent, the problem of electromagnetic interference is still difficult to completely avoid under the action of a high-frequency switch and a complex electromagnetic environment.
In summary, the above problems restrict the further improvement of the performance of the motorcycle electrical system, and there is a need to develop an on-chip integrated voltage regulator chip power circuit with adjustable output amplitude to solve the above problems.
Disclosure of Invention
The invention aims to provide an on-chip integrated voltage regulator chip power supply circuit with adjustable output amplitude, which can generate a working power supply in a voltage regulator chip without providing a working power supply outside the chip, and can also generate an analog and digital power supply with high precision of an on-chip circuit, thereby greatly reducing the influence of power supply interference. Meanwhile, accurate adjustment of the voltage output range is realized, and output voltage stability is ensured.
In order to solve the technical problems, the invention provides an on-chip integrated voltage regulator chip power circuit with adjustable output amplitude, which comprises:
the first power module is used for inputting a battery voltage signal BAT and three-phase electric signals PH 1-PH 3 to generate an on-chip power supply VCC;
the power supply end of the second power supply module is connected with a power supply VCC to generate an on-chip reference voltage VREF, and meanwhile, output voltages VP 1-VP 2 respectively supply power to the later-stage digital module and the analog module;
The output voltage detection module is used for inputting the battery voltage signal BAT and detecting the voltage of the battery voltage signal BAT so as to output a voltage signal VSEN to the output voltage regulation module;
The output voltage adjusting module is used for comparing the input voltage signal VSEN with a voltage signal VCH and a voltage signal VCL after being divided by resistors so as to adjust the amplitude of the voltage adjusting signal OUT, wherein the voltage signal VCH and the voltage signal VCL are generated after the reference voltage VREF is divided by resistors.
Preferably, the first power module comprises triodes Q1-Q5, PMOS tubes P1-P8, NMOS tubes N1-N8 and resistors R1-R12; the three-phase electric signals PH1 to PH3 are respectively connected into bases of triodes Q1 to Q3 through a resistor R3, emitting electrodes and collecting electrodes of the triodes Q1 to Q3 are sequentially cascaded, the emitting electrode of the triode Q3 is grounded, and a collecting electrode of the triode Q1 is connected into a base and collecting electrode of a triode Q4, one end of the resistor R4 and a drain electrode of an NMOS tube N2 to generate a control signal TP_C; the emitter of the triode Q4 is connected with one end of a resistor R5-R6 and the grid electrode of an NMOS tube N3 and generates a control signal TP_G5, the other end of the resistor R6 is grounded, the source of the NMOS tube N2 is connected with the ground, the grid electrode is connected with the control signal TP_G3, the other end of the resistor R4 and the source of a PMOS tube P4-P5, one end of a resistor R7 and one end of a resistor R10 and the drain of an NMOS tube N8 are connected with a battery voltage signal BAT, the grid electrode of the PMOS tube P4 is connected with the control signal TP_G2 and the other end of the drain electrode of the resistor R5, the other end of the resistor R7 is connected with the drain electrode of the NMOS tube N3, the source of the NMOS tube N3 is connected with the base electrode and the collector of the triode Q5, the other end of the resistor R8 is connected with one end of the power supply establishment indication signal TD, the other end of the resistor R8 is connected with the drain electrode and the grid electrode of the NMOS tube N4 and the grid electrode of the NMOS tube N6, the grid electrode of the NMOS tube N5-N6, the grid electrode of the PMOS tube N4-N6 is connected with the drain electrode of the PMOS tube P7 and the drain electrode P7 and the grid electrode of the NMOS tube N7 is connected with the drain electrode P7, the drain electrode of the drain electrode P7 is connected with the drain electrode of the PMOS tube N7 and the drain electrode P7 and the drain electrode of the PMOS tube N7 is connected with the drain electrode of the PMOS tube N6, the drain electrode and the grid electrode of the PMOS tube P6 are connected to the source electrode of the PMOS tube P7, the other end of the resistor R10 is connected to the source electrode of the PMOS tube P8, the drain electrode of the PMOS tube P8 is connected to one end of the resistor R11, the other end of the resistor R11 is connected to one end of the resistor R12, the source electrode and the grid electrode of the NMOS tube N8 and the power supply VCC, and the other end of the resistor R12 is grounded.
Preferably, the first power module further comprises a TP_G2 signal generating circuit, wherein the TP_G2 signal generating circuit comprises PMOS pipes P1-P3, NMOS pipes N1 and resistors R1-R2, one end of each resistor R1 and a source electrode of each PMOS pipe P1 are connected with a battery voltage signal BAT, the other end of each resistor R1 is connected with a drain electrode of each NMOS pipe N1, a grid electrode and a drain electrode of each PMOS pipe P3 and outputs a control signal TP_G2, the grid electrode of each NMOS pipe N1 is connected with the control signal TP_G1, the source electrode of each NMOS pipe N1 is connected with one end of each resistor R2, the other end of each resistor R2 is grounded, the grid electrode and the drain electrode of each PMOS pipe P1 are connected with the source electrode of each PMOS pipe P2, and the grid electrode and the drain electrode of each PMOS pipe P2 are connected with the source electrode of each PMOS pipe P3.
Preferably, the power supply establishment indication signal TD further includes an accessed capacitor connected to ground, the power supply VCC further includes two accessed capacitors connected to ground in parallel, and a resistor is connected in series to the other end of one of the capacitors.
Preferably, the second power supply module comprises a band gap reference circuit BGR, a VP power supply generating circuit and a VREF power supply generating circuit, wherein the output ends of the band gap reference circuit BGR are respectively connected with the input ends of the VP power supply generating circuit and the VREF power supply generating circuit, and the output ends of the VP power supply generating circuit and the VREF power supply generating circuit respectively output voltages VP 1-VP 2 and a reference voltage VREF.
The VP power supply generating circuit preferably comprises an operational amplifier OP1, NMOS tubes N9-N11 and resistors R21-R25, wherein the non-inverting input end of the operational amplifier OP1 is connected with an output end signal BGR_OUT of a band gap reference circuit BGR, the inverting input end of the operational amplifier OP1 is connected with one end of a resistor R22-R23, the other end of the resistor R23 is grounded, the output end of the operational amplifier OP1 is connected with a grid electrode of an NMOS tube N9, the drain electrode of the NMOS tube N9 is connected with one end of a resistor R21, the other end of the resistor R21 is connected with a power supply VCC, the source electrode of the NMOS tube N9 is connected with the other end of the resistor R22 and one end of a resistor R24-R25 and outputs a voltage VP, the other ends of the resistors R24-R25 are connected with the grid electrode of an NMOS tube N10-N11 respectively and correspondingly generate a voltage VP1 and a voltage VP2, and the source electrode and the drain electrode of the NMOS tube N10-N11 are grounded.
The VREF power supply generating circuit comprises an operational amplifier OP2, PMOS pipes P17-P18, an NMOS pipe N17 and resistors R51-R57, wherein the in-phase input end of the operational amplifier OP2 is connected with an output end signal BGR_OUT of a band-gap reference circuit BGR, the opposite-phase input end of the operational amplifier OP2 is connected with one end of a resistor R53-R54, the other end of the resistor R54 is grounded, the output end of the operational amplifier OP2 is connected with the grid electrode of the PMOS pipe P17, the drain electrode of the PMOS pipe P17 is grounded, the source electrode of the PMOS pipe P17 is connected with the drain electrode of the PMOS pipe P18 and the grid electrode of the NMOS pipe N17, the grid electrode of the PMOS pipe P18 is connected with a bias voltage VB2, the source electrode of the PMOS pipe P18 is connected with one end of a resistor R51, the other end of the resistor R51 is connected with a power supply VCC, the drain electrode of the NMOS pipe N17 is connected with one end of a resistor R52, the other end of the resistor R52 is connected with the other end of the power supply VCC, the other end of the NMOS pipe N17 is connected with one end of a resistor R55 and the other end of the reference voltage VCR 55 is connected with the other end of the VCR 57, and the other end of the output voltage VCR 56 is connected with the other end of the VCR 57 is connected with the ground.
Preferably, the output voltage adjusting module comprises PMOS tubes P9-P12, comparators COM 1-COM 2, digital modules, resistors R31-R38 and capacitors C1-C5; one end of the resistor R31 is connected with the source electrodes of the PMOS tube P9 and the PMOS tube P12 by a voltage signal VSEN, the other end of the resistor R31 is connected with one end of the resistor R32, the other end of the resistor R32 is connected with a grounded current source Iref, the grid electrode and the drain electrode of the PMOS tube P9 are connected with the source electrode of the PMOS tube P10, the grid electrode and the drain electrode of the PMOS tube P10 are connected with the source electrode of the PMOS tube P11, the grid electrode and the drain electrode of the PMOS tube P11 are connected with one end of the resistor R32 and the grid electrode of the PMOS tube P12, the drain electrode of the PMOS tube P12 is connected with one end of the resistor R33, the other end of the resistor R33 is connected with a grounded resistor R34, a grounded capacitor C3 and one end of a comparator COM 1-COM 2, the other end of the capacitor C2 is connected with one end of the resistor R36, the other end of the resistor R36 is connected with the grounded capacitor C1-C35, the other end of the resistor R35 is connected with the voltage signal VCH, the other end of the comparator COM2 is connected with the other end of the capacitor C4-C37, and the other end of the comparator COM2 is connected with the digital signal module is connected with the output end of the resistor C37.
Preferably, the digital module adopts phase or operation, that is, when the voltage signal VSEN is scaled down by resistor voltage division, the voltage signal VSEN is respectively compared with the voltage signal VCL and the voltage signal VCH, when the voltage signal VSEN is lower than the voltage signal VCL, the output of the voltage regulating signal OUT is low voltage, so as to keep the three-phase power charged continuously, and when the voltage signal VSEN is higher than the voltage signal VCH, the output of the voltage regulating signal OUT is high voltage.
The preferred band gap reference circuit BGR comprises a PMOS transistor P13-P16, an NMOS transistor N12-N16, a resistor R41-R49, a capacitor C6, a triode Q6-Q8 and an operational amplifier OP3, wherein one end of the resistor R41 is connected with a power supply VCC, the other end is connected with the source electrode of the PMOS transistor P13-P16 and one end of the resistor R48, the grid electrode of the PMOS transistor P13 is connected with a bias voltage VB1, the drain electrode of the PMOS transistor P13 is connected with the source electrode of the PMOS transistor P14, the drain electrode of the PMOS transistor P14 is connected with one end of a resistor R42, the other end of the resistor R42 is connected with one end of a resistor R43 and the emitter electrode of a triode Q6 and outputs a signal BGR_OUT, the other end of the resistor R44 and one end of a resistor R45 are connected with the other end of the resistor R44, the other end of the resistor R44 is connected with the emitter electrode of a reverse phase input end of the operational amplifier Q7, the other end of the resistor R45 is connected with the input end of the operational amplifier OP3 and one end of the resistor P46, the drain electrode of the NMOS transistor P13 and one end of the drain electrode of the resistor P13 and the drain electrode of the NMOS transistor N14 are connected with the drain electrode of the NMOS transistor P14, the drain electrode of the resistor P14 and the drain electrode of the NMOS transistor P14 and the drain electrode of the resistor N14 are connected with the resistor P6, the other end of the resistor R14 and the resistor R6 are connected with the N6 and the drain electrode of the resistor P6, the resistor R12 is connected with the other end of the resistor R6 is connected with the N6, the other end of the resistor R6 is connected with the resistor R7 and the drain electrode is connected with the drain electrode of the transistor, the transistor P6 and the drain electrode is connected with the transistor P7, the other end is connected with the transistor and the transistor P7, the other end is connected with the one, the source electrode of the NMOS tube N15 is connected to the grid electrode and the drain electrode of the NMOS tube N16, and the source electrode of the NMOS tube N16 is grounded.
Preferably, when the battery voltage signal BAT is at a high level, which is the power supply of the battery, the control signal tp_g2 is raised to a high level, the control signal tp_g1 and the control signal tp_g3 are both at a low level initially, the PMOS transistor P4 is turned off, the voltage of the battery voltage signal BAT is input to the gate of the NMOS transistor N3 after being subjected to resistance voltage division by the resistor R4 and the resistor R6, so that the NMOS transistor N3 is turned on, and the capacitor externally connected with the power supply establishment indication signal TD is charged, when the power supply establishment indication signal TD is charged to a certain voltage value, the NMOS transistor N4 and the NMOS transistor N5 are turned on, the gate voltage of the PMOS transistor P8 is pulled down, and the PMOS transistor P8 is turned on at this time, so that the voltage of the power supply VCC is raised and is constant, and the power supply VCC is established, and the digital circuit starts to normally operate.
Preferably, when in a normal working mode, the magneto inputs three-phase electricity, the power supply VCC is lifted and is constant in height, and the power supply establishes an indication signal TD to be constant in height;
When in a low power consumption mode, namely when the magneto is in stalling, namely, ph1=ph2=ph3=0, the control signal tp_g3 becomes high level, the NMOS tube N2 is turned on, the control signal tp_c is pulled down, the control signal tp_g5 becomes low level, the NMOS tube N3 is turned off, the power supply establishment indication signal TD discharges through the NMOS tube N4, the mirror current copied by the NMOS tube N5 is reduced along with the NMOS tube N4, the PMOS tube P8 is turned off after the mirror current is reduced to a certain degree, the NMOS tube N8 is further turned off, the power supply VCC starts to discharge, the battery current is not consumed at the moment by the chip, and other modules in the chip are powered by the electric energy stored by the external capacitor of the power supply VCC, so that the other modules are in a normal working state.
Preferably, when the power supply VCC decreases to a certain extent, the digital circuit controls the control signal tp_g3 to become a low level, the NMOS transistor N2 is turned off, the voltage of the battery voltage signal BAT is input to the gate of the NMOS transistor N3 after being subjected to resistance voltage division through the resistor R4 and the resistor R6, so that the NMOS transistor N3 is turned on, the power supply establishment indication signal TD is charged, the power supply VCC is established, and the digital circuit starts to operate normally again, so that the voltage varies periodically.
Compared with the prior art, the invention has the following beneficial effects:
The invention provides a stable and adaptive basic working power supply VCC for the whole chip by using the first power supply module, the voltage regulator does not need an extra off-chip working power supply, the noise of the on-chip power supply is greatly reduced by using the second power supply module by using the high-precision linear voltage regulator circuit, namely the reference voltage VREF and the on-chip low-voltage working power supply VP, and the output voltage is limited in a certain range by using the output voltage regulating module to detect and regulate the output voltage in real time, so that the precision of the output voltage is greatly improved. The invention solves the technical defects of the traditional integrated power supply in the voltage regulator chip in the aspects of heat management, voltage regulation precision, voltage range adaptability and the like, and realizes stable and reliable voltage output by the power supply circuit, the voltage detection circuit and the voltage regulation circuit which are generated in the chip, thereby providing stable charging voltage for the load battery.
Drawings
Fig. 1 is a block diagram of the overall structure of a power supply circuit provided by the present invention.
Fig. 2 is a schematic circuit diagram of a power module according to the present invention.
Fig. 3 is a schematic diagram of a tp_g2 signal generating circuit according to the present invention.
Fig. 4 is a schematic diagram of a VP power generation circuit in a second power module according to the present invention.
Fig. 5 is a schematic diagram of a VREF power generation circuit in a second power module according to the present invention.
Fig. 6 is a schematic circuit diagram of an output voltage regulation module according to the present invention.
Fig. 7 is a schematic diagram of a bandgap reference circuit provided by the present invention.
Detailed Description
The invention is described in further detail below with reference to the drawings and the specific examples. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.
As shown in fig. 1, an embodiment of the present invention specifically provides an on-chip integrated voltage regulator chip power circuit with adjustable output amplitude, including:
the first power module is used for inputting a battery voltage signal BAT and three-phase electric signals PH 1-PH 3 to generate an on-chip power supply VCC;
the power supply end of the second power supply module is connected with a power supply VCC to generate an on-chip reference voltage VREF, and meanwhile, output voltages VP 1-VP 2 respectively supply power to the later-stage digital module and the analog module;
The output voltage detection module is used for inputting the battery voltage signal BAT and detecting the voltage of the battery voltage signal BAT so as to output a voltage signal VSEN to the output voltage regulation module;
The output voltage adjusting module is used for comparing the input voltage signal VSEN with a voltage signal VCH and a voltage signal VCL after being divided by resistors so as to adjust the amplitude of the voltage adjusting signal OUT, wherein the voltage signal VCH and the voltage signal VCL are generated after the reference voltage VREF is divided by resistors. The output voltage adjusting module is used for adjusting the output amplitude, and further suppressing fluctuation and guaranteeing the stability of the output voltage.
As shown in FIG. 2, the first power module comprises triodes Q1-Q5, PMOS tubes P1-P8, NMOS tubes N1-N8 and resistors R1-R12; the three-phase electric signals PH1 to PH3 are respectively connected into bases of triodes Q1 to Q3 through a resistor R3, emitting electrodes and collecting electrodes of the triodes Q1 to Q3 are sequentially cascaded, the emitting electrode of the triode Q3 is grounded, and a collecting electrode of the triode Q1 is connected into a base and collecting electrode of a triode Q4, one end of the resistor R4 and a drain electrode of an NMOS tube N2 to generate a control signal TP_C; the emitter of the triode Q4 is connected with one end of a resistor R5-R6 and the grid electrode of an NMOS tube N3 and generates a control signal TP_G5, the other end of the resistor R6 is grounded, the source of the NMOS tube N2 is connected with the ground, the grid electrode is connected with the control signal TP_G3, the other end of the resistor R4 and the source of a PMOS tube P4-P5, one end of a resistor R7 and one end of a resistor R10 and the drain of an NMOS tube N8 are connected with a battery voltage signal BAT, the grid electrode of the PMOS tube P4 is connected with the control signal TP_G2 and the other end of the drain electrode of the resistor R5, the other end of the resistor R7 is connected with the drain electrode of the NMOS tube N3, the source of the NMOS tube N3 is connected with the base electrode and the collector of the triode Q5, the other end of the resistor R8 is connected with one end of the power supply establishment indication signal TD, the other end of the resistor R8 is connected with the drain electrode and the grid electrode of the NMOS tube N4 and the grid electrode of the NMOS tube N6, the grid electrode of the NMOS tube N5-N6, the grid electrode of the PMOS tube N4-N6 is connected with the drain electrode of the PMOS tube P7 and the drain electrode P7 and the grid electrode of the NMOS tube N7 is connected with the drain electrode P7, the drain electrode of the drain electrode P7 is connected with the drain electrode of the PMOS tube N7 and the drain electrode P7 and the drain electrode of the PMOS tube N7 is connected with the drain electrode of the PMOS tube N6, the drain electrode and the grid electrode of the PMOS tube P6 are connected to the source electrode of the PMOS tube P7, the other end of the resistor R10 is connected to the source electrode of the PMOS tube P8, the drain electrode of the PMOS tube P8 is connected to one end of the resistor R11, the other end of the resistor R11 is connected to one end of the resistor R12, the source electrode and the grid electrode of the NMOS tube N8 and the power supply VCC, and the other end of the resistor R12 is grounded.
As shown in FIG. 3, the first power module further comprises a TP_G2 signal generating circuit, wherein the TP_G2 signal generating circuit comprises PMOS pipes P1-P3, NMOS pipes N1 and resistors R1-R2, one end of each resistor R1 and a source electrode of each PMOS pipe P1 are connected with a battery voltage signal BAT, the other end of each resistor R1 is connected with a drain electrode of each NMOS pipe N1, a grid electrode and a drain electrode of each PMOS pipe P3 and outputs a control signal TP_G2, the grid electrode of each NMOS pipe N1 is connected with the control signal TP_G1, the source electrode of each NMOS pipe N1 is connected with one end of each resistor R2, the other end of each resistor R2 is grounded, the grid electrode and the drain electrode of each PMOS pipe P1 are connected with the source electrode of each PMOS pipe P2, and the grid electrode and the drain electrode of each PMOS pipe P2 are connected with the source electrode of each PMOS pipe P3.
The power supply establishment indication signal TD also comprises an accessed grounded capacitor, the power supply VCC also comprises two accessed capacitors which are connected in parallel, and the other end of one capacitor is connected with a resistor in series.
When the first circuit of the power supply module works, the input is a battery signal BAT, the output is VCC and TD, wherein VCC provides power for the chip, and TD is a power supply establishment indication signal. When the storage battery supplies power, BAT is high, TP_G2 signals are lifted to be high, TP_G1 and TP_G3 are both initially low, a P4 control tube is cut off, BAT voltage is input to a grid electrode of an N3 control tube after being divided by R4 and R6 resistors, the N3 control tube is conducted, so that a voltage is generated to charge a capacitor externally hung on the TD, after the TD is charged to a certain voltage value, the N4 tube and the N5 tube connected with a diode below the point are conducted, a grid electrode of the P8 tube is pulled down, the P8 tube is conducted, VCC is lifted to be constant high, VCC is established, and a digital circuit starts to work normally. In a normal working mode, the magneto inputs three-phase electricity, VCC is lifted to be constant in height, and TD is lifted to be constant in height. In the low power consumption mode, namely when the magneto is stopped, namely ph1=ph2=ph3=0, tp_g3 becomes high level, the N2 tube is turned on, tp_c is pulled down, so tp_g5 becomes low level, the N3 tube is cut off, TD discharges through the N4 tube, mirror current copied by the N5 tube is reduced along with the N4 tube, the P8 tube is cut off after the mirror current is reduced to a certain degree, the N8 tube is cut off, VCC starts to discharge, the chip almost does not consume battery current any more, and other modules in the chip are powered by electric energy stored by the VCC external capacitor and are in a normal working state. When VCC is reduced to 4V, the digital circuit logic controls TP_G3 to become low level, the N2 tube is cut off, BAT voltage is input to the grid of the N3 tube after being divided by R4 and R6 resistors, the N3 control tube is opened to charge TD, VCC is established, and the digital circuit starts to work normally, so that the voltage is periodically changed.
As shown in fig. 4 and 5, the second power supply module includes a bandgap reference circuit BGR, a VP power supply generating circuit, and a VREF power supply generating circuit;
The VP power supply generating circuit comprises an operational amplifier OP1, NMOS tubes N9-N11 and resistors R21-R25, wherein the in-phase input end of the operational amplifier OP1 is connected with output end signals BGR_OUT of band gap reference circuits BGR, the opposite-phase input end of the operational amplifier OP1 is connected with one ends of the resistors R22-R23, the other ends of the resistors R23 are grounded, the output end of the operational amplifier OP1 is connected with the grid electrode of the NMOS tube N9, the drain electrode of the NMOS tube N9 is connected with one end of a resistor R21, the other end of the resistor R21 is connected with a power supply VCC, the source electrode of the NMOS tube N9 is connected with the other end of the resistor R22 and one end of the resistors R24-R25 and outputs voltages VP1 and VP2, the other ends of the resistors R24-R25 are connected with the grid electrodes of the NMOS tubes N10-N11 respectively, and the source electrodes and the drain electrodes of the NMOS tubes N10-N11 are grounded correspondingly;
The VREF power supply generating circuit comprises an operational amplifier OP2, PMOS pipes P17-P18, an NMOS pipe N17 and resistors R51-R57, wherein the in-phase input end of the operational amplifier OP2 is connected with an output end signal BGR_OUT of a band gap reference circuit BGR, the opposite-phase input end of the operational amplifier OP2 is connected with one end of the resistors R53-R54, the other end of the resistor R54 is grounded, the output end of the operational amplifier OP2 is connected with the grid electrode of the PMOS pipe P17, the drain electrode of the PMOS pipe P17 is grounded, the source electrode of the PMOS pipe P17 is connected with the drain electrode of the PMOS pipe P18 and the grid electrode of the NMOS pipe N17, the grid electrode of the PMOS pipe P18 is connected with a bias voltage VB2, the source electrode of the PMOS pipe P18 is connected with one end of the resistor R51, the other end of the resistor R51 is connected with a power supply VCC, the drain electrode of the NMOS pipe N17 is connected with one end of the resistor R52, the other end of the resistor R52 is connected with one end of the resistor R55 and outputs a reference voltage VREF, and the other end of the resistor R55 is connected with the resistor R56 and the other end of the resistor R57 is connected with the ground voltage VCR 57. And the resistances of the resistor R55, the resistor R56 and the resistor R57 are 24kΩ, 2kΩ and 100kΩ in this order. The reference voltage VREF is divided by the above-described resistors R55, R56, and R57 to generate the voltage signals VCH and VCL.
As shown in FIG. 7, the band gap reference circuit BGR comprises PMOS transistors P13-P16, NMOS transistors N12-N16, resistors R41-R49, a capacitor C6, triodes Q6-Q8 and an operational amplifier OP3; one end of the resistor R41 is connected to a power supply VCC, and the other end is connected to sources of the PMOS tube P13 and the PMOS tubes P15-P16 and one end of the resistor R48; the grid electrode of the PMOS tube P13 is connected with the bias voltage VB1, the drain electrode of the PMOS tube P13 is connected with the source electrode of the PMOS tube P14, the drain electrode of the PMOS tube P14 is connected with one end of a resistor R42, and the other end of the resistor R42 is connected with one end of a resistor R43 and the emitter electrode of a triode Q6 and outputs a signal BGR_OUT; the other end of the resistor R43 is connected with one end of a resistor R44 and one end of a resistor R45, the other end of the resistor R44 is connected with an inverting input end of an operational amplifier OP3 and an emitter of a triode Q7, the other end of the resistor R45 is connected with an in-phase input end of the operational amplifier OP3 and one end of a resistor R46, bases and collector electrodes of the triode Q7 and the triode Q8 are grounded, an emitter electrode of the triode Q8 is connected with the other end of the resistor R46, an output end of the operational amplifier OP3 is connected with a base electrode of the triode Q6, a collector electrode of the triode Q6 is grounded, a grid electrode of the PMOS tube P14 is connected with one end of a capacitor C6 and a resistor R47 which are grounded, and a diode which is grounded, a grid electrode of the PMOS tube P15 is connected with the other end of the resistor R47, a grid electrode of the PMOS tube P15 is connected with a grid electrode and a drain electrode of the PMOS tube P16, a drain electrode of the NMOS tube N12 is connected with a grid electrode of the NMOS tube N13 and a grounded resistor R49, a grid electrode of the NMOS tube N12 is connected with the grid electrode of the NMOS tube N13 and the drain electrode of the NMOS tube N13 is connected with the drain electrode of the drain tube N13 and the drain tube is connected with the drain electrode of the NMOS tube N13, the source electrode of the NMOS tube N15 is connected to the grid electrode and the drain electrode of the NMOS tube N16, and the source electrode of the NMOS tube N16 is grounded.
When the band gap reference circuit BGR works, the bias voltage of the NMOS transistor N12 is provided by three NMOS transistors N14, N15 and N16 connected by diodes, the N13 and N12 transistors form a negative feedback structure, so that the bias voltage of the N12 transistor is stabilized, the branch current is mirrored through the P16 transistor to generate a signal to provide the bias voltage VB1 for the high voltage transistor P13 of the band gap reference circuit BGR, and the bias signal of the P14 transistor is provided by a grounded zener diode. Because of the clamping function of the operational amplifier OP3, the voltages at the two ends of the input end of the operational amplifier OP3 are equal, soWhereinIs the voltage difference between the base and the emitter of the triode Q8, and the output end of the operational amplifier OP3 is provided with equal current flowing through two sides because the resistance voltage drops of the R45 and the R44 are equal and the resistance values are equalWhereinThe base-emitter voltage of transistor Q8Therefore, zero temperature drift voltage output can be realized by adjusting the resistance values of R43, R46, R45 and R46. The band gap reference circuit BGR outputs a bgr_out signal which is a low-temperature drift high stable signal, and the signal outputs two stable voltages VP1 and VP2 through the basic operational amplifier circuit OP1 to supply power for the on-chip digital module and the analog module respectively. According to the deficiency, there are:
here VP1 = VP2 ≡ VP.
As shown in FIG. 6, the output voltage adjusting module comprises PMOS tubes P9-P12, comparators COM 1-COM 2, digital modules, resistors R31-R38 and capacitors C1-C5; one end of the resistor R31 is connected with the source electrodes of the PMOS tube P9 and the PMOS tube P12 by a voltage signal VSEN, the other end of the resistor R31 is connected with one end of the resistor R32, the other end of the resistor R32 is connected with a grounded current source Iref, the grid electrode and the drain electrode of the PMOS tube P9 are connected with the source electrode of the PMOS tube P10, the grid electrode and the drain electrode of the PMOS tube P10 are connected with the source electrode of the PMOS tube P11, the grid electrode and the drain electrode of the PMOS tube P11 are connected with one end of the resistor R32 and the grid electrode of the PMOS tube P12, the drain electrode of the PMOS tube P12 is connected with one end of the resistor R33, the other end of the resistor R33 is connected with a grounded resistor R34, a grounded capacitor C3 and one end of a comparator COM 1-COM 2, the other end of the capacitor C2 is connected with one end of the grounded capacitor C2 and one end of the resistor R36, the other end of the resistor R36 is connected with one end of the grounded capacitor C1-C35, the other end of the resistor R35 is connected with the voltage signal VCH, the other end of the comparator COM2 is connected with the capacitor C5-C37 or the other end of the resistor C37 is connected with the digital signal C-C37, and the digital signal is connected with the other end of the output module is connected with the output end of the resistor.
The resistance of the resistor R31 is 486KΩ, the resistance of the resistor R32 is 10.5KΩ, the resistance ratio of the resistor R33 to the resistor R34 is 25:4, the resistances of the resistor R35 and the resistor R37 are 12.3KΩ, the resistances of the resistor R36 and the resistor R38 are 110.7KΩ, the capacitance of the capacitor C1 is 1.98pF, the capacitance of the capacitors C2 and C5 is 2.74pF, the capacitance of the capacitor C3 is 1.03pF, the capacitance of the capacitor C4 is 2.24pF, and the VCH and VCL are VREF, which are obtained by resistance voltage division. The VSEN signal is divided by resistors and scaled down for voltage comparison with VCL and VCH. When the VSEN signal is lower than VCL, the output of the voltage regulating signal OUT is low voltage, the three-phase power is kept to be charged continuously, when the VSEN signal is higher than VCH, the output of the voltage regulating signal OUT is high voltage, at the moment, the protection circuit of the on-chip integrated voltage regulator chip directly outputs high potential to conduct an external NMOS switch tube, and the input voltage is directly connected to the ground to disconnect the charging until the sampled battery level is lower than the set level lower limit voltage.
The above description is only illustrative of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention, and any alterations and modifications made by those skilled in the art based on the above disclosure shall fall within the scope of the appended claims.
Claims (7)
1. An on-chip integrated voltage regulator chip power circuit with adjustable output amplitude, comprising:
the first power module is used for inputting a battery voltage signal BAT and three-phase electric signals PH 1-PH 3 to generate an on-chip power supply VCC;
the power supply end of the second power supply module is connected with a power supply VCC to generate an on-chip reference voltage VREF, and meanwhile, output voltages VP 1-VP 2 respectively supply power to the later-stage digital module and the analog module;
The output voltage detection module is used for inputting the battery voltage signal BAT and detecting the voltage of the battery voltage signal BAT so as to output a voltage signal VSEN to the output voltage regulation module;
The output voltage regulating module is used for respectively comparing the input voltage signal VSEN with a voltage signal VCH and a voltage signal VCL after voltage division through a resistor so as to regulate the amplitude of a regulating voltage signal OUT, wherein the voltage signal VCH and the voltage signal VCL are respectively generated after voltage division of the reference voltage VREF through the resistor;
The first power supply module comprises triodes Q1-Q5, PMOS tubes P1-P8, NMOS tubes N1-N8 and resistors R1-R12; the three-phase electric signals PH1 to PH3 are respectively connected into bases of triodes Q1 to Q3 through a resistor R3, emitting electrodes and collecting electrodes of the triodes Q1 to Q3 are sequentially cascaded, the emitting electrode of the triode Q3 is grounded, and a collecting electrode of the triode Q1 is connected into a base and collecting electrode of a triode Q4, one end of the resistor R4 and a drain electrode of an NMOS tube N2 to generate a control signal TP_C; the emitter of the triode Q4 is connected with one end of a resistor R5-R6 and the grid electrode of an NMOS tube N3 and generates a control signal TP_G5, the other end of the resistor R6 is grounded, the source of the NMOS tube N2 is connected with the ground, the grid electrode is connected with the control signal TP_G3, the other end of the resistor R4 and the source of a PMOS tube P4-P5, one end of a resistor R7 and one end of a resistor R10 and the drain of an NMOS tube N8 are connected with a battery voltage signal BAT, the grid electrode of the PMOS tube P4 is connected with the control signal TP_G2 and the other end of the drain electrode of the resistor R5, the other end of the resistor R7 is connected with the drain electrode of the NMOS tube N3, the source of the NMOS tube N3 is connected with the base electrode and the collector of the triode Q5, the other end of the resistor R8 is connected with one end of the power supply establishment indication signal TD, the other end of the resistor R8 is connected with the drain electrode and the grid electrode of the NMOS tube N4 and the grid electrode of the NMOS tube N6, the grid electrode of the NMOS tube N5-N6, the grid electrode of the PMOS tube N4-N6 is connected with the drain electrode of the PMOS tube P7 and the drain electrode P7 and the grid electrode of the NMOS tube N7 is connected with the drain electrode P7, the drain electrode of the drain electrode P7 is connected with the drain electrode of the PMOS tube N7 and the drain electrode P7 and the drain electrode of the PMOS tube N7 is connected with the drain electrode of the PMOS tube N6, the drain electrode and the grid electrode of the PMOS tube P6 are connected with the source electrode of the PMOS tube P7, the other end of the resistor R10 is connected with the source electrode of the PMOS tube P8, the drain electrode of the PMOS tube P8 is connected with one end of a resistor R11, the other end of the resistor R11 is connected with one end of a resistor R12, the source electrode and the grid electrode of the NMOS tube N8 and a power supply VCC, and the other end of the resistor R12 is grounded;
The first power module further comprises a TP_G2 signal generating circuit, wherein the TP_G2 signal generating circuit comprises PMOS (P-channel metal oxide semiconductor) tubes P1-P3, NMOS (N-channel metal oxide semiconductor) tubes N1 and resistors R1-R2, one end of each resistor R1 and a source electrode of each PMOS tube P1 are connected with a battery voltage signal BAT, the other end of each resistor R1 is connected with a drain electrode of each NMOS tube N1, a grid electrode of each PMOS tube P3 and a drain electrode and outputs a control signal TP_G2, the grid electrode of each NMOS tube N1 is connected with the control signal TP_G1, the source electrode of each NMOS tube N1 is connected with one end of each resistor R2, and the other end of each resistor R2 is grounded;
the power supply establishment indication signal TD also comprises an accessed grounded capacitor, the power supply VCC also comprises two accessed capacitors which are connected in parallel, and the other end of one capacitor is connected with a resistor in series.
2. The on-chip integrated voltage regulator chip power supply circuit with adjustable output amplitude as set forth in claim 1, wherein the second power supply module comprises a band gap reference circuit BGR, a VP power supply generating circuit and a VREF power supply generating circuit, wherein the output ends of the band gap reference circuit BGR are respectively connected with the input ends of the VP power supply generating circuit and the VREF power supply generating circuit, and the output ends of the VP power supply generating circuit and the VREF power supply generating circuit respectively output voltages VP 1-VP 2 and a reference voltage VREF.
3. The on-chip integrated voltage regulator chip power supply circuit according to claim 2, wherein the VP power supply generating circuit comprises an operational amplifier OP1, NMOS transistors N9-N11 and resistors R21-R25, wherein the non-inverting input end of the operational amplifier OP1 is connected with the output end signal BGR_OUT of the band gap reference circuit BGR, the inverting input end of the operational amplifier OP1 is connected with one end of the resistors R22-R23, the other end of the resistors R23 is grounded, the output end of the operational amplifier OP1 is connected with the grid electrode of the NMOS transistor N9, the drain electrode of the NMOS transistor N9 is connected with one end of the resistor R21, the other end of the resistor R21 is connected with a power supply VCC, the source electrode of the NMOS transistor N9 is connected with the other end of the resistors R22 and one end of the resistors R24-R25, the other ends of the resistors R24-R25 are respectively connected with the grid electrodes of the NMOS transistors N10-N11, and accordingly generate voltages VP1 and VP2, and the source electrodes of the NMOS transistors N10-N11 are grounded.
4. The on-chip integrated voltage regulator chip power supply circuit with adjustable output amplitude as claimed in claim 2, wherein the VREF power supply generating circuit comprises an operational amplifier OP2, PMOS pipes P17-P18, NMOS pipes N17 and resistors R51-R57, wherein the in-phase input end of the operational amplifier OP2 is connected with an output end signal BGR_OUT of a band gap reference circuit BGR, the opposite-phase input end of the operational amplifier OP2 is connected with one end of the resistors R53-R54, the other end of the resistor R54 is grounded, the output end of the operational amplifier OP2 is connected with the grid electrode of the PMOS pipe P17, the drain electrode of the PMOS pipe P17 is grounded, the source electrode of the PMOS pipe P17 is connected with the drain electrode of the PMOS pipe P18 and the grid electrode of the NMOS pipe N17, the source electrode of the PMOS pipe P18 is connected with one end of the resistor R51, the other end of the resistor R51 is connected with one end of the power supply source electrode, the drain electrode of the NMOS pipe N52 is connected with one end of the resistor R52, the other end of the NMOS pipe R52 is connected with the power supply source electrode VCC 17, the other end of the resistor VCR 55 is connected with the other end of the resistor VCR 55, and the other end of the output voltage VCR is connected with the resistor VCR 56, and the other end of the output end of the voltage VCR is connected with the resistor is grounded.
5. The on-chip integrated voltage regulator chip power supply circuit with adjustable output amplitude as claimed in claim 1, wherein the output voltage regulating module comprises PMOS tubes P9-P12, comparators COM 1-COM 2, digital modules, resistors R31-R38 and capacitors C1-C5; one end of the resistor R31 is connected with the source electrodes of the PMOS tube P9 and the PMOS tube P12 by a voltage signal VSEN, the other end of the resistor R31 is connected with one end of the resistor R32, the other end of the resistor R32 is connected with a grounded current source Iref, the grid electrode and the drain electrode of the PMOS tube P9 are connected with the source electrode of the PMOS tube P10, the grid electrode and the drain electrode of the PMOS tube P10 are connected with the source electrode of the PMOS tube P11, the grid electrode and the drain electrode of the PMOS tube P11 are connected with one end of the resistor R32 and the grid electrode of the PMOS tube P12, the drain electrode of the PMOS tube P12 is connected with one end of the resistor R33, the other end of the resistor R33 is connected with a grounded resistor R34, a grounded capacitor C3 and one end of a comparator COM 1-COM 2, the other end of the capacitor C2 is connected with one end of the resistor R36, the other end of the resistor R36 is connected with the grounded capacitor C1-C35, the other end of the resistor R35 is connected with the voltage signal VCH, the other end of the comparator COM2 is connected with the other end of the capacitor C4-C37, and the other end of the comparator COM2 is connected with the digital signal module is connected with the output end of the resistor C37.
6. The integrated voltage regulator chip power supply circuit of claim 5, wherein the digital module performs a phase or operation, i.e., when the voltage signal VSEN is scaled down by resistor voltage division, the voltage signal VSEN is compared with the voltage signal VCL and the voltage signal VCH, respectively, when the voltage signal VSEN is lower than the voltage signal VCL, the output of the voltage regulating signal OUT is low voltage, so as to keep the three-phase power charged continuously, and when the voltage signal VSEN is higher than the voltage signal VCH, the output of the voltage regulating signal OUT is high voltage.
7. The on-chip integrated voltage regulator chip power supply circuit with adjustable output amplitude as set forth in claim 2, wherein said bandgap reference circuit BGR comprises PMOS transistors P13-P16, NMOS transistors N12-N16, resistors R41-R49, capacitor C6, transistors Q6-Q8 and operational amplifier OP3, one end of said resistor R41 is connected to the power supply VCC, the other end is connected to the source of PMOS transistor P13 and P16 and one end of resistor R48, the gate of said PMOS transistor P13 is connected to bias voltage VB1, the drain of said PMOS transistor P13 is connected to the source of PMOS transistor P14, the drain of said PMOS transistor P14 is connected to one end of resistor R42, the other end of said resistor R42 is connected to one end of resistor R43 and the emitter of transistor Q6 and outputs signal BGR_OUT, the other end of said resistor R43 is connected to one end of resistor R44 and resistor R45, the other end of said resistor R44 is connected to the inverting input end of operational amplifier OP3 and the inverting input end of transistor Q7 and the other end of transistor P7, the source of said resistor R13 and the drain of said PMOS transistor P13 and one end of said resistor N16 and one end of said resistor N48, the drain of said resistor P14 and the drain of said PMOS transistor P14 and the resistor P6 are connected to the drain of said PMOS transistor P14, the drain of said resistor P14 is connected to the drain of said resistor P12 and the drain of said transistor P12 and the other end of said resistor P6 and the emitter of said resistor P6 is connected to the gate of said resistor, the other end of the resistor R48 is grounded, the source electrode of the NMOS tube N13 is connected with the grid electrode and the drain electrode of the NMOS tube N15, the source electrode of the NMOS tube N15 is connected with the grid electrode and the drain electrode of the NMOS tube N16, and the source electrode of the NMOS tube N16 is grounded.
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| JP5566568B2 (en) * | 2007-03-27 | 2014-08-06 | ピーエスフォー ルクスコ エスエイアールエル | Power supply voltage generation circuit |
| JP5481161B2 (en) * | 2009-10-30 | 2014-04-23 | ルネサスエレクトロニクス株式会社 | Semiconductor device and power supply device |
| CN103268132B (en) * | 2013-06-06 | 2015-11-11 | 重庆三信电子股份有限公司 | Motorcycle MOS voltage regulator special IC |
| US11137788B2 (en) * | 2018-09-04 | 2021-10-05 | Stmicroelectronics International N.V. | Sub-bandgap compensated reference voltage generation circuit |
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| US11927975B2 (en) * | 2021-11-30 | 2024-03-12 | Pixart Imaging Incorporation | Regulator circuit and reference circuit having high PSRR and switch circuit thereof |
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