CN120389998B - Switch boards, switches, and power-on methods for switches - Google Patents
Switch boards, switches, and power-on methods for switchesInfo
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- CN120389998B CN120389998B CN202510873100.3A CN202510873100A CN120389998B CN 120389998 B CN120389998 B CN 120389998B CN 202510873100 A CN202510873100 A CN 202510873100A CN 120389998 B CN120389998 B CN 120389998B
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Abstract
The invention discloses a switching board, a switch and a power-on method of the switch, and relates to the technical field of computers, wherein the switching board comprises a first layer board, a second layer board, a switching network chip and at least one group of connectors, the first layer board comprises at least one first expansion port, the second layer board comprises at least one second expansion port, the first layer board and the second layer board are connected in an inserted mode through the at least one group of connectors, the switching network chip is arranged on the first layer board, and the switching network chip is used for carrying out configuration management on the at least one first expansion port and/or carrying out configuration management on the at least one second expansion port through the at least one group of connectors. Therefore, through the hierarchical design and the opposite plug connection of the connectors, the problems that the number of expansion ports in the prior art is limited, and the requirement of large-model reasoning application on high-capacity memory cannot be met are solved, and the technical effects of high-density expansion capacity, high signal transmission efficiency and the like are achieved.
Description
Technical Field
The present invention relates to the field of computer technologies, and in particular, to a switch board, a switch, and a method for powering on the switch.
Background
With the explosive growth of artificial intelligence applications, server memory systems gradually transition from traditional subordinate roles to key factors that determine AI system performance. Modern artificial intelligence models, particularly large models, place extremely high demands on memory systems, including high capacity, high bandwidth, low latency, etc., to better support complex reasoning computation tasks. In this context, CXL (Compute Express Link, computational high-speed interconnect) technology has evolved. CXL promotes the server architecture to evolve from fixed configuration to dynamic combinable through memory sharing, heterogeneous resource integration and modularized design, and becomes the core memory expansion technology of the next generation data center.
In the related art, a server typically expands memory capacity by connecting to an external MXC (Memory Expander Controller, memory expansion controller) chip through CXL. The MXC chip can be connected to a host through a PCIe (PERIPHERAL COMPONENT INTERCONNECT EXPRESS, high speed serial computer expansion bus standard) interface and supports a number of memory stick extensions. For example, one common prior art solution is to expand the memory by MXC in PCIe standard card form, where a single MXC chip can support up to 4 memory banks, so as to realize expansion of the memory capacity. However, the number of expansion ports allowed by the expansion mode is limited, so that the requirement of the large-model reasoning application on the high-capacity memory cannot be met, and the problem needs to be solved.
Disclosure of Invention
The invention provides a switching board, a switch and a power-on method of the switch, which at least solve the problem that the prior art depends on a fixed load mode, and cannot reflect the dynamic frequency/voltage regulation characteristic of a CPU (Central Processing Unit, a central processing unit) in a real scene, and realize the technical effects of high test efficiency and high accuracy.
The invention provides a switching board, which comprises a first layer board, a second layer board, a switching network chip and at least one group of connectors, wherein,
The first laminate includes at least one first expansion port;
the second laminate includes at least one second expansion port;
the first laminate and the second laminate are connected in a butt-inserting manner through at least one group of connectors;
The switching network chip is arranged on the first layer board and is used for carrying out configuration management on at least one first expansion port and/or carrying out configuration management on at least one second expansion port through at least one group of connectors.
The invention also provides a switch, comprising:
At least one exchange plate as described above;
And the management board is used for acquiring the equipment configuration information of at least one switching board, and sending a configuration instruction to the switching network chip of at least one switching board according to the equipment configuration information so as to complete memory expansion configuration through the switching network chip of at least one switching board.
The invention also provides a power-on method of the switch, which is applied to the switch, wherein the method comprises the following steps:
under the condition of receiving a starting instruction, controlling the structure manager to power on, and sending an electric signal on the exchange board to the baseboard management controller through the structure manager;
And sending the switch board power-on signal to a programmable logic module through the baseboard management controller so as to close at least one switch board power supply channel through the programmable logic module, so that at least one switch board is powered on and then performs initialization action.
The invention also provides electronic equipment which comprises a memory and a processor, wherein the memory is used for storing a computer program, and the processor is used for realizing the step of the power-on method of any switch when executing the computer program.
The invention also provides a non-volatile computer readable storage medium, wherein the non-volatile computer readable storage medium stores a computer program, and the computer program realizes the steps of the power-on method of any switch when being executed by a processor.
The invention also provides a computer program product comprising a computer program which when executed by a processor implements the steps of the power-up method of any of the switches described above.
The invention solves the problems that the expansion ports in the prior art are limited in number and the requirement of large-model reasoning application on high-capacity memory cannot be met by utilizing the hierarchical design of the exchange board and the opposite plug connection of the connectors, and achieves the technical effects of high-density expansion capability, high signal transmission efficiency and the like.
Drawings
For a clearer description of embodiments of the present invention, the drawings that are required to be used in the embodiments will be briefly described, it being apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to the drawings without inventive effort for those skilled in the art.
Fig. 1 is a schematic topology diagram of a switch board according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a related art memory extended by MXC;
fig. 3 is a schematic diagram of the specification and the dimensions of an exchange board according to an embodiment of the present invention;
fig. 4 is a schematic diagram of interconnection of two boards in a switch board according to an embodiment of the present invention;
Fig. 5 is a schematic block diagram of a switch board according to an embodiment of the present invention;
fig. 6 is a schematic block diagram of a switch according to an embodiment of the present invention;
fig. 7 is a schematic topology diagram of a switch according to an embodiment of the present invention;
fig. 8 is a schematic layout diagram of a switch chassis according to an embodiment of the present invention;
Fig. 9 is a schematic diagram of a power supply topology of a switch system according to an embodiment of the present invention;
fig. 10 is a flowchart of a power-on method of a switch according to an embodiment of the present invention;
fig. 11 is a flowchart of a switch power-on sequence provided in an embodiment of the present invention;
Fig. 12 is a schematic structural diagram of an electronic device according to an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by a person of ordinary skill in the art without making any inventive effort are within the scope of the present invention.
It should be noted that in the description of the present invention, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. The terms "first," "second," and the like in this specification are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order.
The present invention will be further described in detail below with reference to the drawings and detailed description for the purpose of enabling those skilled in the art to better understand the aspects of the present invention.
The embodiment of the invention provides a switching board, and the switching board is described in detail by combining the topological structure of the switching board.
Fig. 1 is a schematic topology of a switch board according to one embodiment of the invention.
Before describing the exchange board provided by the embodiment of the invention, the related technical background is briefly described.
In the related art, a schematic diagram of the memory expansion by MXC may be shown in fig. 2, and its form is designed as an expansion card of PCIe standard. Such cards may be used by inserting x16 gold fingers directly into the CEM (Card Electro-Mechanical) connector of the host or into a riser Card, a hardware device for extending the functionality of a server or computer motherboard. Two MXC chips are supported, and each MXC chip can be extended to 4 DIMMs (Dual Inline Memory Modules, dual in-line memory modules), so that the capacity and performance of the memory are greatly improved. Thus, by using the CXL bus technology, the CPU can interconnect with the MXC chip, thereby realizing expansion of the memory.
However, the memory capacity expanded by MXC chips is limited, and is mainly limited by the number of PCIe interfaces in the system, and the number of PCIe interfaces that can be supported in a system determines the number of MXC chips that can be interconnected, thus defining an upper limit for memory expansion. Under the current state of the art, one MXC chip can support at most 4 memory banks. If a single 256GB memory stripe is used, the maximum memory capacity that one MXC chip can expand is 1024GB. While this is already a considerable number, such capacity is far from meeting its enormous demands on memory for reasoning applications that implement large models.
Based on the above problems, the embodiment of the invention provides a switching board, which solves the problems that the number of expansion ports is limited and the requirement of large-model reasoning application on high-capacity memory cannot be met by hierarchical design and opposite-plug connection of connectors in the prior art, and achieves the technical effects of high-density expansion capability, high signal transmission efficiency and the like.
The exchange board according to the embodiment of the present invention will be described in detail.
Illustratively, as shown in FIG. 1, the switch board 10 includes a first board 100, a second board 200, a switch fabric chip 300, and at least one set of connectors 400. The first layer board 100 comprises at least one first expansion port 101, the second layer board 200 comprises at least one second expansion port 201, the first layer board 100 and the second layer board 200 are connected in an inserting way through at least one group of connectors 400, the exchange network chip 300 is arranged on the first layer board 100, and the exchange network chip 300 is used for carrying out configuration management on the at least one first expansion port 101 and/or carrying out configuration management on the at least one second expansion port 201 through at least one group of connectors 400.
Specifically, as shown in fig. 1, in order to achieve a more efficient and modularized structural design, the embodiment of the present invention adopts a layered design concept to divide the Switch board 10 (i.e., switch chip) into a first board 100 (i.e., lower board) and a second board 200 (i.e., upper board), where the size of the second board 200 (i.e., upper board) is 417×96mm as shown in fig. 3 (a), and the size of the first board 100 (i.e., lower board) is 417×218mm as shown in fig. 3 (b).
Each plate supports at least one expansion port, i.e. the first plate 100 comprises at least one first expansion port 101 and the second plate 200 comprises at least one second expansion port 201. For example, in an embodiment of the present invention, a single exchange panel 10 contains 16 expansion ports altogether, a first laminate 100 contains 8 first expansion ports 101, and a second laminate 200 contains 8 second expansion ports 201.
In the design of the external interface, the switch board 10 further includes at least one group of connectors 400, where at least one group of connectors 400 selected in the embodiment of the present invention is a CDFP (Compact Double Face Plug, compact two-sided plug) connector supporting PCIe Gen5 rate standard, and the connector has not only high transmission speed, but also good compatibility and expansibility. At least one group of connectors 400 can effectively connect the first laminate 100 and the second laminate 200 by means of a butt-joint connection, and interconnect the first laminate and the second laminate through MCIO (Micro Coaxial Interconnect Option, micro coaxial interconnection) cables, so that signal transmission and resource sharing are realized, connection density is greatly improved, and the integration level of the whole system is higher. In this way, the at least one second expansion opening 201 comprised by the second lamina 200 can be successfully extracted to the first lamina 100, so that the function of the entire exchange plate is fully revealed.
The switch board 10 further includes a switch fabric 300 disposed on the first board 100 for directly performing configuration management on at least one first expansion port 101 of the first board 100, and further, for performing configuration management on at least one second expansion port 201 of the second board 200 through at least one set of connectors 400. Therefore, the system can more flexibly configure and adjust the parameters of the expansion port through the management of the expansion port by the exchange network chip 300, and the adaptability of the system is improved.
It will be appreciated that the layered design described above has other significant advantages in that it facilitates assembly and maintenance of the structure, in the first place, because each laminate can be individually handled, which can be more convenient and quick to troubleshoot or upgrade. Secondly, the design is also beneficial to ventilation and heat dissipation of the whole system. Since the first laminate 100 and the second laminate 200 are connected by at least one set of connectors 400, a certain space is left between them, which facilitates ventilation, thereby effectively reducing the operating temperature of the entire system, improving the stability and the service life of the device.
Optionally, in some embodiments, at least one set of connectors 400 employs high density connectors and/or mini-edge input-output cables.
It is understood that at least one set of connectors 400 in embodiments of the present invention may be fully selected from high density connectors, or fully selected from mini-edge input-output cables, or a combination of high density connectors and mini-edge input-output cables.
For high density connectors, as shown in fig. 4, at least one set of connectors 400 (high density connector_a1 and high density connector_a2, or high density connector_b1 and high density connector_b2 as shown in fig. 4) may be hermaphroditic, such as ExaMezz snap connectors, which are laid out on the front side of the first deck 100 and on the back side of the second deck 200, thereby ensuring that they are perfectly mated. For example, the high-density connector_a1 can be plugged with the high-density connector_b1, and the high-density connector_a1 and the high-density connector are tightly combined to form a stable connection. Similarly, the high-density connector_a2 can be in opposite connection with the high-density connector_b2, so that the high-density connector and the high-density connector can be tightly buckled together.
For mini-edge input-output cables (MCIO), this is a compact cable solution, which is suitable for space-constrained environments, and the use of mini-edge input-output cables can further optimize space utilization, making the overall system more compact. As for MCIO connectors, MCIO with x16 lanes (16 channels) may be selected, and in practical application, MCIO _a1 may be connected to MCIO _b2 by a cable to achieve data and signal transmission. Meanwhile, MCIO _a2 may be connected to MCIO _b1, MCIO _a3 may be connected to MCIO _b4, MCIO _a4 may be connected to MCIO _b3, and by such connection, efficient interconnection between a plurality of MCIO connectors may be achieved.
Thus, by using high density connectors and/or mini-edge input-output cables, the switch board 10 is able to provide more interfaces in a limited space, meeting the high capacity memory requirements of high performance computing and large model reasoning.
Optionally, in some embodiments, each set of connectors 400 includes a first connection unit and a second connection unit, where the first connection unit of each set of connectors 400 is disposed on the first layer board 100 and is connected to the switch fabric 300, the second connection unit of each set of connectors 400 is disposed on the second layer board 200 and is correspondingly connected to the at least one second expansion port 201, and the first connection unit and the second connection unit of each set of connectors 400 are disposed in positions corresponding to each other.
Specifically, each set of connectors 400 includes two portions, namely a first connection unit and a second connection unit. Wherein a first connection unit is provided on the first layer board 100 and is connected to the switching network chip 300, which allows the switching network chip 300 to directly manage the at least one first expansion port 101 through the first connection unit and to communicate with the at least one second expansion port 201 through the connector 400. The second connection unit is disposed on the second laminate 200 and is connected to the at least one second expansion port 201 such that the at least one second expansion port 201 can communicate with the first connection unit through the second connection unit, thereby achieving signal transmission between the upper and lower laminates. The first and second connection units of each set of connectors 400 are positioned in correspondence, meaning that they are spatially aligned and can be directly plugged into each other. This design not only simplifies the assembly process, but also ensures the stability and reliability of the signal transmission.
By means of the connectors arranged in a corresponding position, the signal transmission path is optimized, and signals can be transmitted from the switching network chip 300 of the first layer board 100 to the second connection unit through the first connection unit and then to the at least one second expansion port 201, thereby reducing the delay of signal transmission and improving the overall performance of the system.
Optionally, in some embodiments, the positions of the at least one first expansion port 101 and the at least one second expansion port 201 are in one-to-one correspondence, and the first expansion port and the second expansion port corresponding in position are located in the same column.
That is, in the embodiment of the present invention, at least one first expansion opening 101 on the first laminate 100 and at least one second expansion opening 201 on the second laminate 200 are in one-to-one correspondence in position, and the first expansion opening and the second expansion opening in the corresponding positions are located in the same column. Because the positions of the expansion ports correspond, the maintenance and replacement operations are more convenient, and signals can be directly transmitted from the first expansion port to the second expansion port through the corresponding position settings, the intermediate links of signal transmission are reduced, and the efficiency of signal transmission is improved.
The layout design allows the expansion ports of the two boards to be directly plugged through at least one set of connectors 400 without requiring complex wiring or additional adapters, and signals can be directly transmitted from the first expansion port to the second expansion port, thereby reducing signal delay and interference while shortening the transmission path.
Optionally, in some embodiments, the switch board 10 further includes an ethernet physical layer interface module 500 and a network interface 600, where the ethernet physical layer interface module 500 is configured to convert the received first signal into the second signal, and the network interface 600 is connected to the ethernet physical layer interface module 500, and performs remote system maintenance and remote management through the network interface 600, and/or performs remote maintenance and management out-of-band.
Specifically, as shown in fig. 5, the switch board 10 further includes two key parts, namely an ethernet physical layer interface (PHYSICAL LAYER INTERFACE TRANSCEIVER, abbreviated PHY) module 500 and a network interface 600. The ethernet physical layer interface module 500 is mainly responsible for performing conversion of physical layer signals (converting digital signals into analog signals that can be transmitted on a physical Medium, or vice versa), i.e. a received first signal (such as SGMII (Serial Gigabit interface MEDIA INDEPENDENT INTERFACE) Serial network signal) can be converted into a second signal (such as MDI (Medium DEPENDENT INTERFACE) signal) that conforms to a specific standard by the ethernet physical layer interface module 500, and the second signal is connected to the network interface 600. The network interface 600 is connected to the ethernet physical layer interface module 500, and is connected to an external network through the network interface 600 (such as an RJ45 ethernet interface), so that remote system maintenance and management can be achieved, that is, an administrator can monitor, configure and troubleshoot the switch board or the whole system from a remote place through the network connection, without directly contacting the device. In addition, out-of-band remote maintenance and management may also be performed through the network interface 600. Out-of-band management refers to system management through a dedicated management channel independent of the system host processor. This approach is particularly important in the event of a system failure or failure of the primary processor, and allows an administrator to access and repair the system via the backup tunnel.
Thus, through the ethernet physical layer interface module 500 and the network interface 600, the switch board 10 is able to support remote system maintenance and management, as well as out-of-band remote maintenance and management. The design enables an administrator to manage the equipment more flexibly, whether the equipment operates normally or not, and the equipment can be repaired rapidly when the system fails, so that the usability and reliability of the system are improved.
Optionally, in some embodiments, the switch board 10 further includes a serial peripheral interface multiplexer 700 and a storage unit 800, where the serial peripheral interface multiplexer 700 is configured to determine the target communication device according to the control signal sent by the switch network chip 300, and the storage unit 800 is configured to store firmware parameters and configuration parameters required for the operation of the switch network chip 300, so that the firmware parameters and the configuration parameters are read from the storage unit in the case that the switch network chip 300 performs the initialization operation.
Specifically, as shown in fig. 5, the switch board 10 further includes a serial peripheral interface multiplexer 700 and a memory unit 800. In complex systems, multiple peripherals may share the same SPI (SERIAL PERIPHERAL INTERFACE ) bus, and the serial peripheral interface multiplexer 700 may select the correct peripheral (i.e., the target communication device) to communicate based on control signals from the switch fabric 300. That is, when the switching network chip 300 needs to communicate with the target communication device, it sends a control signal to the serial peripheral interface multiplexer 700, and the serial peripheral interface multiplexer 700 can connect the SPI bus to the selected target communication device, thereby achieving efficient device management and signal transmission. And the memory unit 800 (e.g., a Flash memory or other nonvolatile memory device) may store firmware parameters and configuration parameters required for the operation of the switching network chip 300. These parameters, including initialization settings, device configuration, firmware script, etc., are the basis for the proper operation of the switching network chip 300. When the switch network chip 300 performs an initialization operation, the control signal spi_sel on the switch board 10 defaults to a low signal, so that the switch network chip 300 can communicate with the storage unit 800 through the SPI bus, and through the SPI bus, the switch network chip 300 can read necessary firmware parameters and configuration parameters in the storage unit 800, thereby ensuring that the switch network chip 300 can complete its initialization and enter a normal operating state.
Thus, the switching network chip 300 can flexibly communicate with a plurality of peripherals through the serial peripheral interface multiplexer 700 and the storage unit 800, improving flexibility and expandability of the system. The necessary firmware parameters and configuration parameters can be quickly loaded through the storage unit 800, so that the switch network chip 300 can be ensured to quickly finish initialization and enter a normal working state, the initialization time is reduced, and the starting efficiency of the system is improved.
Optionally, in some embodiments, the switch board 10 further includes a clock generator 900 and a clock buffer 1000, where the clock generator 900 is configured to generate a clock signal meeting a preset requirement, and the clock buffer 1000 is configured to process the clock signal to obtain a signal meeting a timing requirement of the switch network chip 300, so that the switch network chip 300 operates based on the signal meeting the timing requirement of the switch network chip 300.
Specifically, the switch board 10 further includes a clock generator 900 and a clock buffer 1000, and the clock generator 900 on the switch board 10 may generate a clock signal with a frequency of 100MHz (i.e., meeting a preset requirement), which is a reference frequency required for the normal operation of the switch network chip 300. To ensure stability and accuracy of the clock signal, the clock generator 900 typically employs high precision oscillators, such as crystal oscillators or temperature compensated crystal oscillators, that are capable of maintaining a stable frequency output under different environmental conditions, reducing jitter and noise. The clock buffer 1000 may process the clock signal generated by the clock generator 900 to meet the timing requirements of the switch network chip 300. The clock signal may be divided into two forms after passing through the clock buffer 1000, one being a single-ended 100MHz clock signal (clk_sys as shown in fig. 5) and the other being 16 differential clock signals (16 x clk_port as shown in fig. 5). These signals are ultimately sent to the switching network chip 300 for ensuring proper operation of the chip. By processing the clock buffer 1000, the clock signal can remain stable and accurate during transmission, reducing the effects of jitter and noise.
It will be appreciated that the core of this mechanism is the role of the clock signal, i.e. the clock signal resembles a "heartbeat" in the digital circuit, which is used to synchronize the operation of the various parts. The stability and accuracy of the clock signal directly affects the performance and reliability of the system. If the clock signal is unstable or inaccurate, data transmission errors, system performance degradation, and even system crashes may result. The single-ended signal and the differential signal are different in transmission mode, the use of the differential signal improves the anti-interference capability of the system, is suitable for long-distance or high-precision transmission, and reduces interference in the signal transmission process.
Thus, by the cooperative operation of the clock generator 900 and the clock buffer 1000, it is ensured that the switching network chip 300 can operate based on a stable and accurate clock signal, thereby improving the overall performance and reliability of the system.
According to the exchange board provided by the embodiment of the invention, through layered design and opposite connection of connectors, the problem that the number of expansion ports is limited in the prior art and the requirement of large-model reasoning application on high-capacity memory cannot be met is solved, and the technical effects of high-density expansion capacity, high signal transmission efficiency and the like are realized.
From the description of the above embodiments, it will be clear to a person skilled in the art that the system according to the above embodiments may be implemented by means of software plus the necessary general hardware platform, but of course also by means of hardware, but in many cases the former is a preferred embodiment.
The embodiment of the invention also provides a switch.
Fig. 6 is a schematic topology diagram of a switch according to an embodiment of the present invention.
As shown in fig. 6, the switch 1 includes at least one switch board 10 and a management board 20, where the management board 20 is configured to obtain device configuration information of the at least one switch board 10, and send a configuration instruction to the switch network chip 300 of the at least one switch board 10 according to the device configuration information, so as to complete memory expansion configuration through the switch network chip 300 of the at least one switch board 10.
Specifically, as shown in fig. 6, the switch 1 mainly comprises two switch boards 10 and a management board 20, the management board 20 is interconnected with the two switch boards 10 through a power connector and MCIO cables, and respectively provides power, I2C, UART (Universal Asynchronous Receiver-transceiver), PCIe, GPIO (General Purpose Input/Output ) and other transmission control signals, so that in-band and out-of-band management of the whole machine can be realized. The management board 20 is provided with a length of 424mm and a width of 207mm as a whole. The management board 20 is a control center of the switch 1, is responsible for managing and configuring the whole switch system, and can realize functions of system management, monitoring, configuration and power on/off control of the whole switch, acquire device configuration information of at least one switch board 10 through an I2C (Inter-INTEGRATED CIRCUIT, integrated circuit bus) bus, including, for example, a hardware state, a port type, a firmware board, etc. of the switch board 10, and based on the acquired device configuration information, the management board 20 can generate a configuration instruction and send the configuration instruction to the switch network chip 300 through a PCIe interface. The configuration instruction is used for guiding the switching network chip 300 how to configure the memory expansion, so that flexible allocation and optimal utilization of the memory resources are realized. That is, after receiving the configuration instruction from the management board 20, the switch network chip 300 can dynamically adjust the memory expansion configuration according to the configuration instruction, so as to adapt to different application scenarios and requirements. This dynamic adjustment capability increases the flexibility and adaptability of the system.
In addition, the two switch boards 10 remain independent in arrangement, with each switch board 10 being interconnected together by MCIO cables, high-density connectors (i.e., at least one set of connectors 400) of the upper and lower two-layer boards (i.e., the first layer board 100 and the second layer board 200), together providing 32-port services to the outside. Each switch board 10 can support 16 ports as a node, allows uplink and downlink connection to be configured at will, and each port has 16 lanes and has a speed of up to 32Gb/s, so that the unidirectional data transmission capacity reaches 1024Gb/s, and strong support is provided for data transmission.
Thus, through dynamic configuration management and overall system monitoring of management board 20, flexibility, reliability and performance of the system are improved.
Optionally, in some embodiments, the management board 20 includes a fabric manager 21 and a baseboard management controller 22, where the fabric manager 21 and the baseboard management controller 22 communicate via a first bus, and the baseboard management controller 22 is configured to control the at least one switch board 10 to be powered on according to power-on information of the fabric manager 21.
Specifically, as shown in fig. 7, the management board 20 includes a Fabric Manager (FM) 21 and a baseboard management controller (Baseboard Management Controller, BMC) 22. The first bus (LPC (Low Pin Count Bus, low pin count bus) shown in fig. 5) may be used between the fabric manager 21 and the baseboard management controller 22 to transmit the power-on information of the fabric manager 21 and control the power-on and power-off signals of the switch boards 10, so as to implement communication between the fabric manager 21 and the baseboard management controller 22, and power-on control of at least one switch board 10 by the baseboard management controller 22. The baseboard management controller 22 serves as a management center of the system and plays an important role in out-of-band management and control of the entire switch 1. The system not only supports real-time monitoring and management of out-of-band information of the whole machine, but also monitors state information of a power supply unit (Power Supply Unit, PSU for short), state information of power virtualization resources and temperature information of the whole switch 1.
In addition, the baseboard management controller 22 also has the functions of implementing fan control and system display, ensuring that the system is operating in an optimal state. That is, the baseboard management controller 22 can monitor the temperature inside the switch 1 in real time by a built-in temperature sensor. These sensors are distributed near critical components, such as the CPU, the switch fabric chip 300, etc., ensuring that the temperature of each component can be accurately measured. Based on the monitored temperature data, baseboard management controller 22 can intelligently adjust the rotational speed of the fan. The baseboard management controller 22 can automatically increase the fan speed to increase heat dissipation when the temperature is higher, and the baseboard management controller 22 can decrease the fan speed to reduce noise and energy consumption when the temperature is lower. The baseboard management controller 22 can also detect whether the fan is operating properly. If a fan failure is detected, baseboard management controller 22 can issue an alarm and take other actions (e.g., increase the rotational speed of other fans) to ensure system heat dissipation. For the system display function, the baseboard management controller 22 can display key status information (such as temperature, fan rotation speed, power status, etc.) of the system on a management interface or a physical display screen through the system display function, so that maintenance personnel can intuitively know the operation status of the system. In the event that a fault is detected by baseboard management controller 22, specific fault information may be displayed via a display screen or indicator lights, helping maintenance personnel to quickly locate and resolve the problem. Baseboard management controller 22 can also record system operational logs including temperature changes, fan speed adjustments, fault alarms, etc., which can be used for subsequent analysis and maintenance.
While the fabric manager 21 plays a critical role in the network fabric or fabric management of the switch 1. It is not only responsible for collecting the operating status information of the switch board 10 (including but not limited to health, performance metrics, fault information, etc. of the equipment, which is critical for the stable operation of the real-time monitoring and maintenance system), but also for identifying different types of ports and for obtaining firmware board information of the switch board 10. In addition, the configuration manager 21 has a function of setting a port route, which is critical for configuration and optimization of the network, and by dynamically adjusting the port route according to the network traffic and the device status, the network can automatically adapt to changes, and the flexibility and reliability of the network can be improved. The fabric manager 21 may also manage the memory devices of the downstream ports of the switch board 10 through the PCIe interface, including monitoring the capacity and rate of the memory devices, etc. It should be noted that the memory device management function is not only applicable to the x86 architecture processor, but also applicable to the ARM (ADVANCED RISC MACHINE, advanced reduced instruction set computer) architecture processor, that is, both of the two processors can be used as the main control chip of the management board 20, and are responsible for running management software and processing data, so that the flexibility and adaptability of the system are improved.
Thus, the management board 20 realizes the overall monitoring and management of the switch 1 through the cooperative work of the structure manager 21 and the baseboard management controller 22. The structure manager 21 focuses on optimizing the network structure and collecting information to ensure the high efficiency and stability of the network, while the baseboard management controller 22 focuses on the management and control of the hardware level, from power management, temperature monitoring to fan regulation. The two complement each other and together support the efficient operation and the reliable guarantee of the exchanger 1. In addition, the power-on process of the exchange board 10 is controlled by the baseboard management controller 22 according to the starting-up information of the structure manager 21, so that the system can be started and powered on more flexibly, and the overall performance of the system is improved.
Optionally, in some embodiments, the fabric manager 21 includes at least one management interface and at least one transport interface, wherein the fabric manager 21 obtains device configuration information of the at least one switch board 10 through the at least one management interface, and the fabric manager 21 sends the configuration instruction to the switch fabric chip 300 of the at least one switch board 10 through the at least one transport interface.
That is, as shown in FIG. 7, the fabric manager 21 includes at least one management interface (e.g., an I2C bus) and at least one transmission interface (e.g., a PCIe interface), wherein the I2C bus is a low-speed, low-pin-count serial communication protocol suitable for device status monitoring and transmission of configuration information, and the PCIe interface is a high-speed serial communication protocol suitable for high-speed data transmission and device configuration management. The fabric manager 21 may obtain information such as a status, a port type, a firmware board book, etc. of the switch network chip 300 (i.e., device configuration information of the at least one switch board 10) through the I2C bus (i.e., at least one management interface), and may send a configuration instruction to the switch network chip 300 of the at least one switch board 10 through the PCIe interface (i.e., at least one transport interface). These configuration instructions are used to instruct the switching fabric chip how to configure the memory extensions to ensure that the system is able to efficiently use memory resources.
Therefore, the flexible acquisition of the equipment configuration information and the efficient transmission of the configuration instructions are realized through the management interface and the transmission interface of the structure manager 21, and the flexibility and the performance of the system are improved.
Optionally, in some embodiments, the management board 20 further comprises an ethernet control module 23 and an ethernet switch 24, wherein the ethernet control module 23 is configured to convert the received third signal into a fourth signal, and the ethernet switch 24 is configured to convert the fourth signal into the first signal.
Specifically, in order to realize the switching of the network port function between the two switch boards 10, the mode of an ethernet interaction chip (ETHERNET SWITCH CHIP, abbreviated as Eth SW) may be used to uniformly convert different types of network signals into SGMII serial network signals supporting long transmission distances. Specifically, as shown in fig. 7, the PCIe interface signal (i.e., the third signal) of the fabric manager 21 may be converted into an MDI signal (i.e., the fourth signal) by the ethernet control module 23 (e.g., the I210 chip) and then connected to the ethernet switch 24 and converted into an SGMII (i.e., the first signal), and the RGMII (Reduced Gigabit MEDIA INDEPENDENT INTERFACE, reduced Gigabit independent interface) signal directly output by the baseboard management controller 22 may be converted into an MDI signal (i.e., the fourth signal) by the ethernet control module 23 (e.g., the PHY chip) and then connected to the ethernet switch 24 and converted into an SGMII (i.e., the first signal). The PHY chip may be a type 88E1512, 88E1512 is a high-performance PHY chip, supports gigabit ethernet transmission, and is suitable for various network devices, and the ethernet interaction chip of the ethernet switch 24 may use a type 88E6190, where 88E6190 is a high-performance ethernet switching chip, and supports various network functions including flow control and the like.
Thus, different types of network signals are uniformly converted into SGMII signals through the ethernet control module 23 and the ethernet switch 24. The unified signal format enables the switching of the network port function between the two switching boards 10 flexibly, and adapts to different network configuration requirements. The design supports various network topological structures, so that the system can dynamically adjust network configuration according to different application scenes and requirements, and the flexibility and adaptability of the system are improved.
Optionally, in some embodiments, the management board 20 further comprises an expansion module 25 for expanding any management interface of the fabric manager 21 into at least two management interfaces.
Specifically, in the case where the fabric manager 21 has only one set of I2C interfaces as the control center of the switch board 10, the number of management interfaces may be extended (i.e., any management interface of the fabric manager 21 is extended to at least two management interfaces) by using the extension module 25 (e.g., I2C expander), so that the fabric manager 21 can connect more devices. The configuration manager 21 may be connected to different switch boards 10 through the extension module 25, so as to implement real-time monitoring of the status of each switch board 10, including obtaining information of port type, firmware board, etc. Furthermore, the expansion module 25 may support not only static connections but also dynamic configurations. This means that the system can dynamically adjust the number of devices connected as needed, thereby improving the flexibility and adaptability of the system.
Therefore, the expandability and maintainability of the system are enhanced by introducing the expansion module 25, so that when a management interface is required to be added, the original structure manager 21 is not required to be replaced, and only the expansion module 25 is required to be added, thereby greatly saving the cost and time.
Optionally, in some embodiments, the management board 20 further includes a programmable logic module 26 and a first heat dissipation component 27, where the programmable logic module 26 is configured to obtain an actual rotation speed of the first heat dissipation component 27, so as to adjust the PWM signal of the first heat dissipation component 27 according to the actual rotation speed.
Specifically, as shown in fig. 7, the programmable logic module 26 is connected to the baseboard management controller 22 through an I2C bus, and the baseboard management controller 22 can upgrade the firmware of the programmable logic module 26 through the I2C bus, so that the firmware upgrade function ensures that the programmable logic module 26 can run the latest control logic, support new functions or repair known problems. Baseboard management controller 22 may also transmit power up and power down instructions to programmable logic module 26 to control the power state of switch net chip 300. The baseboard management controller 22 can also send instructions to the programmable logic module 26 to control the switching on of the clock signal of the switching network chip 300 and switch the SPI link channel, so as to ensure that the switching network chip 300 can work normally and support the efficient operation of the system. The programmable logic module 26 may also obtain the actual rotational speed of the first heat dissipating component 27 (e.g., a fan) via a TACH (Tachometer ) signal (a signal for measuring the rotational speed of the motor, typically generated by the motor of the fan), and adjust the duty cycle of the PWM (Pulse Width Modulation ) signal according to the actual rotational speed, so as to control the rotational speed of the first heat dissipating component 27. The PWM signal is a method for controlling the rotation speed of the motor by changing the pulse width, and by adjusting the duty ratio of the PWM signal, the rotation speed of the first heat dissipating component 27 can be precisely controlled, so as to optimize the heat dissipating performance of the system.
Thus, by precisely controlling the rotational speed of the first heat sink assembly 27, the system can dynamically adjust the heat dissipation performance according to actual needs, ensuring adequate heat dissipation at high loads, while reducing noise and energy consumption at low loads. By optimizing the heat dissipation performance, the running time of the hardware at high temperature can be reduced, and the service life of the hardware can be prolonged.
Optionally, in some embodiments, the switch 1 further includes a switch chassis body, where, in a case where the switch 1 includes two switch boards 10, the two switch boards 10 are overlapped, and after being overlapped, the two switch boards are sequentially disposed on the switch chassis body along a first direction with the management board 20, where the first direction is a direction in which a tail of the switch chassis points to a front of the switch chassis.
Specifically, the switch 1 further includes a switch chassis body, where the switch chassis body is 2U high (U is a unit of rack-mounted server and chassis height, and 1U is equal to 1.75 inches (about 44.45 millimeters)), and can support front and rear cabinets to be put on shelves, so that daily maintenance is facilitated. This design allows the exchange 1 to be conveniently installed in standard cabinets while maintaining good heat dissipation. As shown in fig. 8, in the case where the switch 1 includes two switch boards 10, the two switch boards 10 are designed to be arranged in an overlapping manner to effectively use space, reduce the overall size of the switch cabinet body, and maintain the high performance of the system. The two overlapped switch boards 10 and the management board 20 are sequentially arranged in the switch case body along the direction that the tail part of the switch case points to the front part of the switch case, so that the switch case can be conveniently operated when maintenance or component replacement is required.
Further, the front window portion of the switch chassis body includes left and right hangers, a portal, and a CDFP (Common Data Form Factor Pluggable, universal data size pluggable connector) connector. The left and right lugs are used to secure structural components of the chassis that ensure that the chassis is securely mounted in place. The network port part consists of a system network port and a management network port, which respectively bear different network communication tasks. The PWR Button (Power Button ) is the on-off Button of the entire system. When the system needs to be started, the button is only needed to be pressed for a short time, and when the system needs to be closed, the shutdown operation can be realized by pressing the button for a long time. The system portal is a network signal output through the fabric manager 21, which is critical to performing remote system maintenance and management. On the other hand, the management portal is a network signal output by the baseboard management controller 22, which supports the out-of-band remote maintenance and management functions. The right hanging part also comprises a VGA (Video GRAPHICS ARRAY INTERFACE, video graphic array interface) interface which can be directly connected with a display to provide visual output for a user, and meanwhile, a USB (Universal Serial Bus ) interface can be connected with a keyboard and a mouse, and the daily KVM (KeyboardVideoMouse, keyboard, video and mouse) management is simple and convenient due to the access of the peripheral. It should be noted that the system portal and the management portal are disposed on two different switch boards 10, respectively, and the system portal and the management portal are physically interchangeable.
Optionally, in some embodiments, two switch boards 10 are disposed on a first switch board tray and a second switch board tray, respectively, and the first switch board tray and the second switch board tray are locked to the switch chassis body by a locking mechanism.
Specifically, in order to further improve convenience in maintenance and assembly, a type of exchanging plate tray (including a first exchanging plate tray and a second exchanging plate tray) having a forward drawing function is provided, and two exchanging plates 10 may be respectively provided on the first exchanging plate tray and the second exchanging plate tray. Each exchange board tray is provided with handles on two sides, so that a user can easily and independently carry out drawing operation to draw out or push in the exchange board tray from the switch cabinet body. During the installation process, once the exchange board tray is pushed into place, the exchange board tray can be firmly fixed with the switch cabinet body by falling the locking mechanism.
Therefore, through the design of the exchange plate tray, the convenience of maintenance and assembly is greatly improved, and particularly when the exchange plate is required to be checked, maintained or replaced, the exchange plate can be quickly accessed, and the maintenance time and workload are reduced. The design of locking mechanism has ensured the stability and the reliability of exchange board tray in quick-witted incasement, prevents to lead to the tray to become flexible because of vibration or other external force to guarantee the steady operation of system.
Optionally, in some embodiments, the switch 1 further includes a first power supply assembly 30 and a second power supply assembly 40 disposed on the switch chassis body, and the at least one switch board 10 is powered by the second power supply assembly 40 in case of failure of the first power supply assembly 30.
That is, in the embodiment of the present invention, two power supply components (such as PSU power supply) are further disposed at the rear window portion of the switch chassis body, that is, the first power supply component 30 and the second power supply component 40 support a 1+1 redundancy design, and when one of the power supply components fails, the other power supply component can immediately take over the whole system load to continue to supply power to at least one switch board 10. Thereby, it is possible to ensure continuous stable operation of the switch 1, avoiding system downtime or service interruption due to a single power supply component failure. This redundant design not only improves the reliability of the system, but also reduces maintenance costs.
Optionally, in some embodiments, the switch 1 further includes a second heat dissipation assembly disposed on the switch chassis body, where the second heat dissipation assembly includes a first heat dissipation unit and a second heat dissipation unit, and the first heat dissipation unit and the second heat dissipation unit dissipate heat for at least one switch 1 at the same time, or dissipate heat for at least one switch 1 through the second heat dissipation unit in case of a failure of the first heat dissipation unit.
Specifically, the switch 1 further includes other important components, namely a second heat dissipation component, and the second heat dissipation component is disposed at a rear window portion of the switch chassis body, so that heat generated in the operation process of the switch 1 can be effectively dissipated, and therefore normal working temperature of equipment is maintained.
In addition, redundancy is also considered in the design of the second heat dissipating assembly, which further comprises two key parts, namely a first heat dissipating unit and a second heat dissipating unit, each of which may comprise two fans supporting a 2+2 redundancy design. That is, if the first heat dissipating unit fails, the second heat dissipating unit can independently assume responsibility for dissipating heat, ensuring that at least one switch 1 can still be sufficiently dissipated, thereby avoiding equipment failure or performance degradation due to overheating.
Optionally, in some embodiments, the switch 1 further includes an overcurrent monitoring unit 50, configured to send an overcurrent signal to the programmable logic module 26 when any switch board 10 has an overcurrent fault, so as to disconnect a power supply channel of the switch board 10 corresponding to the overcurrent signal through the programmable logic module 26.
It will be appreciated that in order to ensure stable operation and safety of the system, embodiments of the present invention may incorporate an over-current monitoring unit 50 in particular on the link. In this way, the baseboard management controller 22 is able to monitor the magnitude of the current in real time using the I2C signal. Upon detecting that the current exceeds a preset safety threshold, i.e., that an overcurrent fault exists, baseboard management controller 22 can immediately send instructions to programmable logic module 26 via the I2C communication protocol. After receiving the instruction, the programmable logic module 26 will execute the operation of turning off the p12v_sw unit (the power supply unit for providing the 12V voltage to the switch board 10), and disconnect the power supply channel of the switch board 10 corresponding to the overcurrent signal, so as to effectively protect the whole system from the overcurrent damage.
Further, the system topology of the entire switch 1 may be as shown in fig. 9, and the p12v_psu voltage outputted from the first Power supply assembly 30 and the second Power supply assembly 40 is transferred to a p1v_stby (Power 12 Volt Standby Unit, a module providing a standby Power) unit, which may directly convert the p1v_psu voltage into p5v_stby, p3v3_stby, and p1v2_stby voltages, which may then be used by the management board 20 and the switch board 10. The P12V_STBY unit can ensure that the system can stably run in a starting or low-power consumption mode, and starting failure or system instability caused by a power supply problem is reduced.
In addition, the p12v_psu voltage can also be supplied to the p12v_sw unit, and the programmable logic module 26 can enable the p12v_sw unit by controlling the signals p12v_sw0_en and p12v_sw1_en. The design enables the system to dynamically enable or disable the P12V_SW unit according to the requirement, so that the flexibility of power management is improved. Once the p12v_sw unit is activated, it can output p12v_sw0 and p12v_sw1 voltages. These voltages are then further converted to P1V2_SW P1v0_sw and P the 10V9 SW voltage is set to be, to meet different power requirements.
Since different components in the switch 1 may require different power supply voltages, the system is able to generate various voltages by switching of the p12v_stby unit and the p12v_sw unit, satisfying different demands of the management board 20 and the switch board 10. By the control of the programmable logic module 26, the system can dynamically adjust the enabling and disabling of the power supply according to the actual requirements, optimize the power supply management and reduce unnecessary energy consumption.
In summary, the switch provided by the embodiment of the invention has at least the following beneficial effects:
(1) In the 2U-height switch cabinet, 2 CXL switch switching nodes (namely two switching boards) are carefully designed on the basis of ensuring that the heat radiation performance is not affected. These nodes not only provide extremely high switching power densities, but also can provide up to 32 high-speed interconnect interfaces to the outside. The interfaces support bandwidth data transmission up to 2048 GB/s, and provide a solid technical foundation and hardware guarantee for high-performance calculation, data analysis and other application scenes which need strong computational power support.
(2) In the invention, the uplink port of the switch can be connected with the server host, and the downlink port can be connected with the memory expansion card. The design allows a single host to be connected with a plurality of CXL memory expansion cards, so that under the condition of limited PCIe interface quantity, memory resources with higher bandwidth and higher capacity can be obtained, the limit of the quantity of PCIe physical interfaces of the traditional main board is effectively broken through, and more flexible and powerful memory expansion capability is provided for users.
(3) The switch of the embodiment of the invention follows the standard 19 inch rack size, which enables it to perfectly accommodate front-to-back racking requirements in the machine room. The design of the device not only considers the installation convenience of the device, but also considers daily deployment and maintenance work, and ensures the high-efficiency operation and long-term stability of the device.
According to the switch provided by the embodiment of the invention, the advanced configuration supporting 2 switch boards 10 is integrated in the switch cabinet body with the height of 2U, so that the cabinet can provide up to 32 high-speed interconnection interfaces to the outside. These high-speed interconnect interfaces can support bandwidths as high as 2048 GB/s, bringing unprecedented data transfer speeds to users. In addition, the design allows a single host to easily connect a plurality of CXL memory expansion cards, thereby effectively breaking through the limit of the number of PCIe physical interfaces of the traditional main board. Through the innovative connection mode, a user can fully utilize the excellent performance of the CXL bus to obtain high-bandwidth and high-capacity memory resources, and the overall performance and the expansion capacity of the system are greatly improved.
The embodiment of the invention also provides a power-on method of the switch.
As shown in fig. 10, the power-up method of the switch is applied to the switch of the embodiment of fig. 6, wherein the method includes the following steps:
in step S1001, when a power-on command is received, the fabric manager is controlled to power on, and a switch board power-on signal is sent to the baseboard management controller through the fabric manager.
It will be appreciated that the power-on command is typically triggered by a user through a management interface or physical button (i.e., the PWR button of the management board).
Specifically, when the user presses the PWR button, the management board can receive a power-on instruction. After receiving the start-up instruction, the management board can control the structure manager to be powered on. After the structure manager is powered on, a power-on signal is generated and sent to the baseboard management controller through the LPC bus or other communication interfaces.
In step S1002, an electrical signal on the switch board is sent to the programmable logic module by the baseboard management controller, so that the power supply channel of at least one switch board is closed by the programmable logic module, and the at least one switch board is initialized after being powered on.
The baseboard management controller is responsible for out-of-band management and control of the overall switch system. The method supports monitoring and management of out-of-band information of the whole machine, and monitors PSU state information, power VR (Power Voltage Regulator ) state information, whole machine temperature information and the like. The programmable logic module can control the power supply channel of the switch board, and the programmable logic module is communicated with the baseboard management controller through the I2C bus and receives control instructions (namely, electrical signals on the switch board) from the baseboard management controller. The programmable logic module closes the power supply channel by controlling the enable signals (e.g., p12v_sw0_en, p12v_sw1_en) of the p12v_sw unit. These enable signals control the output of the p12v_sw unit to provide the 12V power to the switching board. Once the power supply channel is closed, the switch board will perform an initialization action after power-up. The initialization actions include loading firmware, configuring memory devices, checking hardware status, etc., to ensure that the switch board can function properly.
Further, in some embodiments, after the at least one switch board completes the initializing action, the method further includes sending an overcurrent signal to the programmable logic module to disconnect a power supply channel of the switch board corresponding to the overcurrent signal through the programmable logic module when any switch board has an overcurrent fault.
Specifically, after the switch boards complete the initialization, the system continuously monitors the current condition of each switch board, and if an overcurrent fault is detected in a certain switch board, that is, the current exceeds a preset safety threshold, the system generates an overcurrent signal. The signal indicates that the board is in an abnormal condition and measures need to be taken to prevent further damage. The over-current signal may be sent to the programmable logic module by the baseboard management controller, and the programmable logic module turns off the output of the p12v_sw unit by controlling the enable signals (such as p12v_sw0_en and p12v_sw1_en) of the p12v_sw unit according to the received over-current signal, so as to disconnect the power supply channel of the corresponding switch board.
Further, in some embodiments, after judging that any exchange board has an overcurrent fault, the method further comprises the steps of generating an overcurrent fault reminding instruction based on the overcurrent signal, and carrying out acoustic overcurrent reminding and/or optical overcurrent reminding according to the overcurrent fault reminding instruction.
Specifically, the baseboard management controller can generate an overcurrent fault reminding instruction based on the overcurrent signal. The instructions are used to inform system administrators or maintenance personnel so that they can quickly take action to solve the problem. The overcurrent fault reminding instruction may include specific information of the fault, such as a fault switch board number, fault type (overcurrent), fault time, and the like. This information helps to locate and solve problems quickly. In addition, based on the over-current fault alert instructions, the system may trigger an acoustic alert (e.g., a buzzer or alarm emitting a specific audible signal) and may trigger an optical alert (e.g., one or more lights emitting a specific light signal) to draw the attention of a system administrator or maintenance personnel.
In order to further understand the power-on method of the switch according to the embodiment of the present invention, the following description is further provided with reference to fig. 11.
As shown in fig. 11, the power-up method of the switch may further include the steps of:
step S1101, a Power Supply Unit (PSU) is connected to the 220V ac power supply.
In step S1102, the system outputs a Standby (STBY) power, and the baseboard management controller starts to read the FLASH memory therein to complete its initialization process, and the programmable logic module is powered on and completes its initialization.
In step S1103, after the start button on the front window panel of the switch chassis is pressed, the structure manager starts to power up.
Step S1104, after the system enters the main operation state, sends a switch board power-on instruction to the baseboard management controller through a Low Pin Count (LPC) interface, and the baseboard management controller converts the power-on instruction into an I2C signal and sends the I2C signal to the programmable logic module, thereby controlling the switch board to perform an initialization action after power-on is completed.
According to the switch power-on method provided by the embodiment of the invention, the efficient, stable and safe switch system starting and running are realized. The method not only improves the reliability and availability of the system, but also provides a more convenient and intelligent management means for network administrators.
Fig. 12 is a schematic structural diagram of an electronic device according to an embodiment of the present invention. The electronic device may include:
Memory 1201, processor 1202, and computer program stored on memory 1201 and executable on processor 1202.
The processor 1202, when executing the program, implements the steps of any of the switch power-up method embodiments described above.
Further, the electronic device further includes:
a communication interface 1203 for communication between the memory 1201 and the processor 1202.
A memory 1201 for storing a computer program executable on the processor 1202.
Memory 1201 may include high speed RAM (Random Access Memory ) memory, and may also include non-volatile memory, such as at least one disk memory.
If the memory 1201, the processor 1202, and the communication interface 1203 are implemented independently, the communication interface 1203, the memory 1201, and the processor 1202 may be connected to each other through a bus and perform communication with each other. The bus may be an ISA (Industry Standard Architecture ) bus, a PCI (PERIPHERAL COMPONENT INTERCONNECT, external device interconnect) bus, or EISA (Extended Industry Standard Architecture ) bus, among others. The buses may be divided into address buses, data buses, control buses, etc. For ease of illustration, only one thick line is shown in fig. 12, but not only one bus or one type of bus.
Alternatively, in a specific implementation, if the memory 1201, the processor 1202 and the communication interface 1203 are integrated on a chip, the memory 1201, the processor 1202 and the communication interface 1203 may communicate with each other through internal interfaces.
The processor 1202 may be a CPU or ASIC (Application SPECIFIC INTEGRATED Circuit) or one or more integrated circuits configured to implement embodiments of the present invention.
Embodiments of the present invention also provide a non-volatile computer readable storage medium having a computer program stored therein, wherein the computer program is configured to perform the steps of any of the switch power-up method embodiments described above when run.
In an exemplary embodiment, the above-mentioned non-volatile computer readable storage medium may include, but is not limited to, a U disk, a Read-Only Memory (ROM), a random access Memory, a removable hard disk, a magnetic disk, or an optical disk, etc. various media in which a computer program may be stored.
Embodiments of the present invention also provide a computer program product comprising a computer program which, when executed by a processor, implements the steps of the power-up method embodiment of any of the switches described above.
Embodiments of the present invention also provide another computer program product comprising a non-volatile computer readable storage medium storing a computer program which, when executed by a processor, implements the steps of the power-up method embodiment of any of the switches described above.
Those of skill would further appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative elements and steps are described above generally in terms of functionality in order to clearly illustrate the interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
The power-on method of the switch provided by the invention is described in detail above. The principles and embodiments of the present invention have been described herein with reference to specific examples, the description of which is intended only to facilitate an understanding of the method of the present invention and its core ideas. It should be noted that it will be apparent to those skilled in the art that various modifications and adaptations of the invention can be made without departing from the principles of the invention and these modifications and adaptations are intended to be within the scope of the invention as defined in the following claims.
Claims (23)
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| US6416333B1 (en) * | 1999-03-24 | 2002-07-09 | Ando Electric Co., Ltd. | Extension boards and method of extending boards |
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| CN105471752B (en) * | 2014-08-21 | 2019-11-19 | 中兴通讯股份有限公司 | Equipment, the method and system of rack stacking are realized based on switching network |
| TWI573515B (en) * | 2015-06-01 | 2017-03-01 | 宜鼎國際股份有限公司 | Laminated structure |
| CN111030950B (en) * | 2019-11-30 | 2021-07-27 | 苏州浪潮智能科技有限公司 | A kind of stack switch topology construction method and device |
| CN221978967U (en) * | 2023-12-22 | 2024-11-08 | 北京傲星科技有限公司 | Exchange board card |
| CN118245228B (en) * | 2024-05-22 | 2025-02-11 | 苏州元脑智能科技有限公司 | CXL switch card, CXL memory allocation system, allocation method and device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US6416333B1 (en) * | 1999-03-24 | 2002-07-09 | Ando Electric Co., Ltd. | Extension boards and method of extending boards |
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