CN120417442B - Semiconductor structure and semiconductor device - Google Patents
Semiconductor structure and semiconductor deviceInfo
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- CN120417442B CN120417442B CN202510899885.1A CN202510899885A CN120417442B CN 120417442 B CN120417442 B CN 120417442B CN 202510899885 A CN202510899885 A CN 202510899885A CN 120417442 B CN120417442 B CN 120417442B
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Abstract
The application provides a semiconductor structure and a semiconductor device, the semiconductor structure comprises a substrate, an epitaxial layer, a grid structure, a first metal layer, a first doping region and a first doping region, wherein the epitaxial layer is positioned on the surface of the substrate and comprises an epitaxial layer body and a groove, the groove is positioned in the epitaxial layer body, the grid structure is at least positioned in the groove, the side wall of the grid structure is in contact with part of the side wall of the groove, the first metal layer is at least positioned in the groove, the side wall of the first metal layer is in contact with part of the side wall of the groove, in a first direction, the first metal layer is positioned on one side of the grid structure, in a direction perpendicular to the thickness of the substrate, the first doping region is positioned in the epitaxial layer body, the first doping region is positioned on one side of the first metal layer, far away from the grid structure, and is in contact with the first metal layer, and the doping type of the first doping region is different from the doping type of the epitaxial layer. The application solves the problem that the cell size of the trench gate MOSFET in the prior art is difficult to ensure the firmness of the trench bottom and is smaller.
Description
Technical Field
The application relates to the technical field of semiconductors, in particular to a semiconductor structure and a semiconductor device.
Background
Silicon carbide (SiliconCarbide, siC for short) is used as a wide forbidden band semiconductor material, and has wide application prospect in the application fields of high voltage, high power, high temperature and high frequency by virtue of the advantages of wide forbidden band, high critical electric field intensity, high thermal conductivity, high saturation drift speed and the like.
Compared with a planar gate MOSFET, a trench gate MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) has higher trench mobility and smaller cell width Pitch size, thereby having better on-state characteristics and smaller chip size, and has remarkable advantages in the application fields of high voltage, high frequency, high power density and the like by combining the faster switching speed.
However, the robustness of the trench gate MOSFET is to solve the gate oxide electric field problem on the one hand and the latch-up problem of the parasitic thyristor on the other hand, which requires a smart structural design to avoid erosion of the conduction characteristics to improve the trade-off between robustness and conductivity.
The double trench structure (DT-MOS) of Rohm company is improved in robustness by adding an additional source trench etch and then ion implantation to the source trench to obtain a P-well region of sufficient depth to improve the electric field at the gate oxide location at the bottom of the trench gate, but this structure separates the trench source and gate trenches, limiting the reduction of the cell width Pitch.
The trench gate MOSFET in the prior art has difficulty in ensuring the cell size to be small while ensuring the robustness of the trench bottom.
Disclosure of Invention
The application mainly aims to provide a semiconductor structure and a semiconductor device, which are used for solving the problem that a trench-gate MOSFET in the prior art is difficult to ensure the firmness of the trench bottom and the small size of a cell.
In order to achieve the above object, according to one aspect of the present application, there is provided a semiconductor structure including a substrate, an epitaxial layer on a surface of the substrate, the epitaxial layer including an epitaxial layer body and a trench in the epitaxial layer body, a gate structure at least in the trench, a sidewall of the gate structure being in contact with a portion of the sidewall of the trench, a first metal layer at least in the trench, a sidewall of the first metal layer being in contact with a portion of the sidewall of the trench, the first metal layer being located on one side of the gate structure in a first direction, the first direction being perpendicular to a direction of a thickness of the substrate, a first doping region being located in the epitaxial layer body, the first doping region being located on a side of the first metal layer remote from the gate structure, and the first doping region being in contact with the first metal layer, the doping type of the first doping region being different from a doping type of the epitaxial layer.
Optionally, the semiconductor structure further comprises an isolation dielectric layer at least in the trench and between the gate structure and the first metal layer.
Optionally, the semiconductor structure further comprises a second doped region, a third doped region and a third doped region, wherein the second doped region is positioned in the epitaxial layer body and is positioned on one side, close to the substrate, of the groove, the doping type of the second doped region is the same as that of the first doped region, the third doped region is positioned in the epitaxial layer body and is at least positioned on a part of the surface, far away from the substrate, of the second doped region, the third doped region is in contact with the groove, the doping type of the third doped region is the same as that of the first doped region, and the doping concentration of the third doped region is larger than that of the first doped region.
Optionally, the semiconductor structure further comprises a fourth doped region, a fifth doped region and a fifth doped region, wherein the fourth doped region is located in the epitaxial layer body and is located on one side, away from the substrate, of the first doped region, the first doped region is in contact with the fourth doped region, the doping type of the fourth doped region is the same as that of the first doped region, the doping concentration of the fourth doped region is smaller than that of the first doped region, the fifth doped region is located in the epitaxial layer body and is located at least on a part of the surface, away from the substrate, of the first doped region and on a part of the surface, away from the substrate, of the fourth doped region, the doping type of the fifth doped region is the same as that of the epitaxial layer, and the doping concentration of the fifth doped region is larger than that of the epitaxial layer, and the isolation medium layer is located in the groove, on the surface, away from the substrate, of the gate structure, and on the part of the surface, away from the substrate, of the fifth doped region.
Optionally, the semiconductor structure further comprises a sixth doped region located in the epitaxial layer body and located at least on a surface of the first doped region close to the substrate and on a part of a surface of the fourth doped region close to the substrate, wherein the doping type of the sixth doped region is the same as that of the epitaxial layer.
Optionally, the sixth doped region is located on a surface of the first doped region near the substrate and on a surface of the fourth doped region near the substrate.
Optionally, the sixth doped region is located on a surface of the first doped region close to the substrate and a part of a surface of the fourth doped region close to the substrate, and the sixth doped region is not in contact with the first metal layer, wherein a schottky contact is formed at a portion of a side wall of the first metal layer, which is in contact with the epitaxial layer body.
Optionally, the gate structure is located in the trench, and the gate structure comprises a gate oxide layer located in the trench, wherein the thickness of the isolation medium layer is greater than that of the gate oxide layer, and a gate electrode is located on the surface, away from the substrate, of the gate oxide layer.
Optionally, the gate structure is located in the groove and on a part of the surface of the fifth doped region, which is far away from the substrate, and comprises a gate oxide layer, a gate and a gate electrode, wherein the gate oxide layer is located in the groove and on a part of the surface of the fifth doped region, which is far away from the substrate, and the thickness of the isolation medium layer is larger than that of the gate oxide layer, and the gate electrode is located on the surface of the gate oxide layer, which is far away from the substrate.
Optionally, the fifth doped region is located on a surface of the first doped region remote from the substrate and on a surface of the fourth doped region remote from the substrate, and the first metal layer is located in the trench and on a portion of the surface of the fifth doped region remote from the substrate.
Optionally, the fifth doped region is located on a portion of a surface of the first doped region remote from the substrate, a portion of a sidewall of the first doped region remote from the first metal layer, and a surface of the fourth doped region remote from the substrate, the first metal layer being located in the trench, on a portion of a surface of the fifth doped region remote from the substrate, and on a portion of a surface of the first doped region remote from the substrate.
Optionally, the fifth doped region is located on a portion of a surface of the first doped region remote from the substrate, a portion of a sidewall of the first doped region remote from the first metal layer, and a surface of the fourth doped region remote from the substrate, the first metal layer is located in the trench, a portion of a surface of the fifth doped region remote from the substrate, a portion of a sidewall of the fifth doped region near the first metal layer, and a portion of a surface of the first doped region remote from the substrate.
Optionally, a portion of the surface of the first metal layer adjacent to the substrate is in contact with the epitaxial layer body, and a portion of the surface of the first metal layer adjacent to the substrate is in schottky contact with the epitaxial layer body.
Optionally, the sixth doped region is in contact with the first metal layer, and a schottky contact is formed at a portion of the sixth doped region in contact with the first metal layer.
Optionally, the third doped region is located at least on a portion of a surface of the second doped region remote from the substrate and on a sidewall of the sixth doped region proximate to the first metal layer.
Optionally, the projection pattern of the third doped region on the substrate is different.
Optionally, the semiconductor structure further comprises a second metal layer located on a surface of the substrate remote from the epitaxial layer.
According to another aspect of the present application, there is provided a semiconductor device comprising any of the semiconductor structures described.
By applying the technical scheme of the application, the semiconductor structure comprises a substrate, an epitaxial layer, a grid electrode structure, a first metal layer and a first doping region, wherein the epitaxial layer is arranged on the surface of the substrate, the epitaxial layer comprises an epitaxial layer body and a groove, the groove is arranged in the epitaxial layer body, the grid electrode structure and the first metal layer are respectively arranged in the groove at least, in the first direction, the first metal layer is arranged on one side of the grid electrode structure, the first direction is perpendicular to the thickness direction of the substrate, the first doping region is arranged in the epitaxial layer body, the first doping region is arranged on one side, far away from the grid electrode structure, of the first metal layer, the first doping region is in contact with the first metal layer, and the doping type of the first doping region is different from that of the epitaxial layer. Compared with the prior art that the trench-gate MOSFET is difficult to ensure the firmness of the trench bottom and the small cell size, the first metal layer and the gate structure are configured in the same trench, so that the limitation of the decoupling trench digging process capability on the small-size cell width (the width of the gate and the width of the source can be reduced) is facilitated, the whole cell size is further facilitated to be reduced, the first metal layer is positioned in the trench and contacted with part of the side wall of the trench, and is positioned on one side of the gate structure in the first direction, so that stable electrical connection is facilitated, an additional conductive path can be provided on one side of the gate structure, current density is facilitated to be dispersed, current concentration is reduced, parasitic capacitance is reduced, the firmness of a device is improved, and in addition, the doping type of the first doping region is different from that of the epitaxial layer, so that a good PN junction is facilitated to be formed, and the electrical stability of the device is improved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the application. In the drawings:
Fig. 1 to 13 respectively show schematic cross-sectional structures of different semiconductor structures provided according to embodiments of the present application.
Wherein the above figures include the following reference numerals:
10. the semiconductor device comprises a substrate, 11, an epitaxial layer, 111, an epitaxial layer body, 112, a groove, 12, a grid structure, 13, a first metal layer, 14, a first doped region, 15, an isolation medium layer, 16, a second doped region, 17, a third doped region, 18, a fourth doped region, 19, a fifth doped region, 20, a sixth doped region, 121, a grid oxide layer, 122, a grid, 21 and a second metal layer.
Detailed Description
It should be noted that the following detailed description is illustrative and is intended to provide further explanation of the application. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.
It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of exemplary embodiments according to the present application. As used herein, the singular is also intended to include the plural unless the context clearly indicates otherwise, and furthermore, it is to be understood that the terms "comprises" and/or "comprising" when used in this specification are taken to specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof.
It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. Furthermore, in the description and in the claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element or "connected" to the other element through a third element.
As described in the background art, it is difficult to ensure cell size to be small while ensuring trench bottom robustness in the trench gate MOSFET of the prior art, and in order to solve the above-described problems, embodiments of the present application provide a semiconductor structure and a semiconductor device.
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.
An embodiment of the present application provides a semiconductor structure, as shown in fig. 1 to 13, including:
A substrate 10;
an epitaxial layer 11 on the surface of the substrate 10, the epitaxial layer 11 including an epitaxial layer body 111 and a trench 112, the trench 112 being located in the epitaxial layer body 111;
a gate structure 12 located at least in the trench 112, wherein a sidewall of the gate structure 12 contacts a portion of a sidewall of the trench 112;
A first metal layer 13 located at least in the trench 112, wherein a sidewall of the first metal layer 13 contacts a portion of a sidewall of the trench 112, and the first metal layer 13 is located on one side of the gate structure 12 in a first direction perpendicular to a thickness direction of the substrate 10;
the first doped region 14 is located in the epitaxial layer body 111, the first doped region 14 is located on a side of the first metal layer 13 away from the gate structure 12, the first doped region 14 is in contact with the first metal layer 13, and a doping type of the first doped region 14 is different from a doping type of the epitaxial layer 11.
Through the embodiment, the semiconductor structure comprises a substrate, an epitaxial layer, a gate structure, a first metal layer and a first doped region, wherein the epitaxial layer comprises an epitaxial layer body and a groove, the groove is formed in the epitaxial layer body, the gate structure and the first metal layer are respectively at least located in the groove, the first metal layer is located on one side of the gate structure in a first direction, the first direction is perpendicular to the thickness direction of the substrate, the first doped region is located in the epitaxial layer body, the first doped region is located on one side, far away from the gate structure, of the first metal layer, the first doped region is in contact with the first metal layer, and the doping type of the first doped region is different from that of the epitaxial layer. Compared with the prior art that the trench-gate MOSFET is difficult to ensure the firmness of the trench bottom and the small cell size, the first metal layer and the gate structure are configured in the same trench, so that the limitation of the decoupling trench digging process capability on the small-size cell width (the width of the gate and the width of the source can be reduced) is facilitated, the whole cell size is further facilitated to be reduced, the first metal layer is positioned in the trench and contacted with part of the side wall of the trench, and is positioned on one side of the gate structure in the first direction, so that stable electrical connection is facilitated, an additional conductive path can be provided on one side of the gate structure, current density is facilitated to be dispersed, current concentration is reduced, parasitic capacitance is reduced, the firmness of a device is improved, and in addition, the doping type of the first doping region is different from that of the epitaxial layer, so that a good PN junction is facilitated to be formed, and the electrical stability of the device is improved.
Specifically, the arrangement of the first metal layer is beneficial to heat conduction and improves the height Wen Nailiang.
Specifically, the semiconductor structure in the application is a trench gate MOSFET, the first metal layer is used as source metal,
In the embodiment of the application, the doping types of the substrate and the epitaxial layer are both N-type, the doping concentration of the substrate is greater than that of the epitaxial layer, the substrate is 4H-SiC, the doping concentration of the substrate is 5E18cm -3~1E21cm-3, the thickness of the substrate is 50-500 μm, the doping type of the first doping region is P-type, the doping concentration of the first doping region is 2E17cm -3~8E19cm-3, the thickness of the first doping region is 0-5 μm, the width of the groove (i.e. the length in the first direction) is 0.5-5 μm, and the depth of the groove (i.e. the length in the direction parallel to the thickness of the substrate) is 0.5-5 μm.
Specifically, the material of the first metal layer includes, but is not limited to, nickel and titanium.
In other embodiments, the epitaxial layer body includes a first sub-epitaxial layer and a second sub-epitaxial layer, the first sub-epitaxial layer is located on a surface of the substrate, the second sub-epitaxial layer is located on a surface of the first sub-epitaxial layer away from the substrate, a doping concentration of the first sub-epitaxial layer is greater than a doping concentration of the second sub-epitaxial layer, and the trench is located in the second sub-epitaxial layer.
Specifically, the thickness of the first sub-epitaxial layer is smaller than the thickness of the second sub-epitaxial layer.
In the embodiment of the application, the doping concentration of the first sub-epitaxial layer is 5E15cm -3~1E19cm-3, the thickness of the first sub-epitaxial layer is 5-50 μm, the doping concentration of the second sub-epitaxial layer is 1E14cm -3~5E17cm-3, and the thickness of the second sub-epitaxial layer is 5-150 μm.
In an alternative, as shown in fig. 1, the semiconductor structure further includes an isolation dielectric layer 15 at least in the trench 112 and between the gate structure 12 and the first metal layer 13. In this embodiment, an isolation dielectric layer is introduced into the trench and is located between the gate structure and the first metal layer, which can reduce direct electrical contact between the gate structure and the first metal layer, thereby reducing the risk of electrical breakdown and further enhancing the electrical robustness of the device.
In the embodiment of the present application, the materials of the isolation dielectric layer include but are not limited to BPSG, siO 2, and Si xOyNz.
In other embodiments, as shown in fig. 1 to 13, the semiconductor structure further includes a second doped region 16 located in the epitaxial layer body 111 and located on a side of the trench 112 near the substrate 10, wherein the doping type of the second doped region 16 is the same as the doping type of the first doped region 14, and a third doped region 17 located in the epitaxial layer body 111 and located at least on a portion of the surface of the second doped region 16 away from the substrate 10, wherein the third doped region 17 is in contact with the trench 112, wherein the doping type of the third doped region 17 is the same as the doping type of the first doped region 14, and the doping concentration of the third doped region 17 is greater than the doping concentration of the first doped region 14. In this embodiment, the second doped region is disposed under the trench, that is, under the gate structure, which is advantageous for reducing CGD and improving switching characteristics, and in addition, the introduction of the second doped region and the third doped region is beneficial to improving the electric field distribution at the bottom of the groove and reducing the electric field concentration, so that the breakdown risk of the device under high voltage is reduced, and the firmness of the device is further improved.
In the embodiment of the application, the doping type of the second doping region is P-type, the doping concentration of the second doping region is 8E16cm -3~5E19cm-3, the thickness of the second doping region is 0.5-3 μm, the doping type of the third doping region is N-type, the doping concentration of the third doping region is 4E17cm -3~1E20cm-3, the thickness of the third doping region is 0.2-2 μm, and the length of the third doping region in the first direction is 0.5-20 μm.
In the embodiment of the application, the doping element of the doped region with the doping type of P type comprises but is not limited to aluminum ions, and the doping element of the doped region with the doping type of N type comprises but is not limited to nitrogen ions.
According to some exemplary embodiments of the present application, as shown in fig. 1 to 13, the semiconductor structure further includes a fourth doped region 18 located in the epitaxial layer body 111 and located on a side of the first doped region 14 away from the first metal layer 13, the first doped region 14 is in contact with the fourth doped region 18, the doping type of the fourth doped region 18 is the same as the doping type of the first doped region 14, the doping concentration of the fourth doped region 18 is smaller than the doping concentration of the first doped region 14, a fifth doped region 19 located in the epitaxial layer body 111 and located at least on a portion of the first doped region 14 away from the substrate 10 and on a surface of the fourth doped region 18 away from the substrate 10, the doping type of the fifth doped region 19 is the same as the doping type of the epitaxial layer 11, and the doping concentration of the fifth doped region 19 is greater than the doping concentration of the epitaxial layer 11, wherein the isolation dielectric layer 15 is located in the portion of the substrate 10 away from the surface of the fifth doped region 19 and the gate electrode 12 and the portion of the substrate 10. In this embodiment, by introducing the fourth doped region and the fifth doped region into the semiconductor structure and precisely controlling the doping types and the concentrations of the fourth doped region and the fifth doped region, the electrical characteristics of the semiconductor device, such as improving the mobility of carriers and reducing the resistivity, can be further optimized, so that the overall performance of the device is further improved, the doping concentration of the fifth doped region is greater than that of the epitaxial layer, which is conducive to more uniformly distributing the electric field during operation of the device, reducing the concentration of the electric field, so as to improve the voltage-withstanding capability and the reliability of the device, the presence of the fourth doped region, and the doping concentration thereof being smaller than that of the first doped region, are conducive to enhancing the control capability of the gate to the channel, which is critical for improving the switching speed of the device and reducing the leakage current, and the design of the isolation dielectric layer is conducive to reducing the leakage current, so that the insulation performance of the device is further improved, thereby further improving the overall electrical reliability.
In the embodiment of the application, the doping type of the fourth doping region is P-type, the doping concentration of the fourth doping region is 5E15cm -3~2E18cm-3, the thickness of the fourth doping region is 0.2-3 μm, the doping type of the fifth doping region is N-type, the doping concentration of the fifth doping region is 1E18cm -3~5E21cm-3, and the thickness of the fifth doping region is 0.1-3 μm.
In other embodiments, as shown in fig. 1 to 13, the semiconductor structure further includes a sixth doped region 20 located in the epitaxial layer body 111 and located at least on a surface of the first doped region 14 adjacent to the substrate 10 and a portion of a surface of the fourth doped region 18 adjacent to the substrate 10, wherein a doping type of the sixth doped region 20 is the same as a doping type of the epitaxial layer 11. In this embodiment, the electrical characteristics of the semiconductor structure may be further adjusted and optimized by introducing the sixth doped region, and since the doping type of the sixth doped region is the same as that of the epitaxial layer, it may affect the distribution and mobility of carriers to some extent, thereby improving the conductivity and switching speed of the device.
In the embodiment of the present application, the doping type of the sixth doped region is N-type, the doping concentration of the sixth doped region is 5E15cm -3~1E19cm-3, and the thickness of the sixth doped region is 0.5 μm to 5 μm.
In particular, the third doped region may have various modifications, such as those of the third doped region of fig. 1 to 8.
According to further exemplary embodiments of the present application, as shown in fig. 1 to 11, the sixth doped region 20 is located on a surface of the first doped region 14 adjacent to the substrate 10 and on a surface of the fourth doped region 18 adjacent to the substrate 10.
In some alternatives of the present application, as shown in fig. 12 and 13, the sixth doped region 20 is located on a surface of the first doped region 14 adjacent to the substrate (not shown) and a portion of a surface of the fourth doped region 18 adjacent to the substrate, and the sixth doped region 20 is not in contact with the first metal layer 13, wherein a portion of a sidewall of the first metal layer 13 in contact with the epitaxial layer body (not shown) forms a schottky contact. In this embodiment, by forming the schottky contact, the contact resistance can be reduced, the conductivity of the device can be further improved, and the arrangement of the sixth doped region can reduce the current density near the SBD (Schottky Barrier Diode ) region, thereby reducing the temperature peak of the SBD region, and further improving the robustness of the device.
Specifically, the local configuration of the nJFET region (i.e., the sixth doped region) (the local configuration refers to the channel side configuration and the source contact side configuration) can reduce the current density near the SBD region, thereby reducing the temperature peak of the SBD region and further improving the robustness of the device. The source contact side refers to a side near the source metal (i.e., the first metal layer), and the channel side refers to a side near the channel formed between the fourth doped region and the gate oxide layer.
Specifically, as shown in fig. 12 and 13, a portion of the sidewall of the first metal layer 13 forming schottky contact with the epitaxial layer body is a vertical schottky contact region (not shown).
In other embodiments, as shown in FIG. 13, the gate structure 12 is disposed in the trench 112, the gate structure 12 includes a gate oxide layer 121 disposed in the trench 112, the thickness of the isolation dielectric layer 15 is greater than the thickness of the gate oxide layer 121, and a gate 122 disposed on a surface of the gate oxide layer 121 remote from the substrate (not shown). In this embodiment, the electric field between the gate and other parts of the semiconductor can be effectively isolated by setting the gate oxide layer, so as to improve the insulation performance of the gate.
Specifically, in the same groove, an isolation medium layer is arranged between the first metal layer and the gate structure, an original gate oxide layer is replaced, the thickness and the area of the medium layer are increased, CGS (CAPACITANCE BETWEEN GATE AND SOURCE, capacitance between gate sources) is reduced, and further switching characteristics are improved.
In still other alternatives of the present application, as shown in fig. 1 to 12, the gate structure 12 is located in the trench 112 and on a portion of the surface of the fifth doped region 19 away from the substrate 10, the gate structure 12 includes a gate oxide layer 121 located in the trench 112 and on a portion of the surface of the fifth doped region 19 away from the substrate 10, the thickness of the isolation dielectric layer 15 is greater than the thickness of the gate oxide layer 121, and a gate electrode 122 is located on a surface of the gate oxide layer 121 away from the substrate 10. In this embodiment, by disposing the gate oxide layer in the trench and on the surface of the portion of the fifth doped region away from the substrate, and ensuring that the thickness of the isolation dielectric layer is greater than that of the gate oxide layer, the gate and the trench can be effectively isolated, the leakage current can be reduced, and the electrical performance of the device can be further improved.
Specifically, the gate oxide layer is located on a portion of the sidewall, a portion of the surface (i.e., the bottom surface) and a portion of the fifth doped region of the trench, wherein the thickness of the gate oxide layer located on a portion of the sidewall and a portion of the fifth doped region of the trench is greater than the thickness of the gate oxide layer located on a portion of the sidewall of the trench, such that carriers in the gate oxide layer can be reduced from migrating to the gate oxide location, thereby improving threshold stability.
Specifically, the ILD (INTERLAYER DIELECTRIC ) dielectric layer (i.e., isolation dielectric layer) may further extend to the upper surface of the epitaxial layer, and thicken the thickness of the dielectric layer between the P-field stop region (i.e., second doped region) and the gate, which is beneficial to threshold stability.
In still other alternatives of the present application, as shown in fig. 10, the fifth doped region 19 is located on a surface of the first doped region 14 remote from the substrate (not shown) and on a surface of the fourth doped region 18 remote from the substrate, and the first metal layer 13 is located in the trench 112 and on a portion of a surface of the fifth doped region 19 remote from the substrate. In this embodiment, by precisely controlling the position of the fifth doped region, the electric field distribution in the semiconductor structure, especially in the vicinity of the trench region, can be optimized, which helps to further improve the withstand voltage performance of the device.
In other embodiments, as shown in fig. 9, the fifth doped region 19 is located on a portion of the surface of the first doped region 14 away from the substrate (not shown), a portion of the sidewall of the first doped region 14 away from the first metal layer 13, and a surface of the fourth doped region 18 away from the substrate, and the first metal layer 13 is located in the trench 112, a portion of the surface of the fifth doped region 19 away from the substrate, and a portion of the surface of the first doped region 14 away from the substrate. In this embodiment, by precisely controlling the positions of the first doped region, the fifth doped region, and the first metal layer, the electrical characteristics of the semiconductor device, such as reducing resistance, improving carrier mobility, and the like, can be further optimized.
According to further exemplary embodiments of the present application, as shown in fig. 11, the fifth doped region 19 is located on a portion of the surface of the first doped region 14 remote from the substrate (not shown), on a portion of the sidewall of the first doped region 14 remote from the first metal layer 13, and on a surface of the fourth doped region 18 remote from the substrate, the first metal layer 13 is located in the trench 112, on a portion of the surface of the fifth doped region 19 remote from the substrate, on a portion of the sidewall of the fifth doped region 19 remote from the first metal layer 13, and on a portion of the surface of the first doped region 14 remote from the substrate. In this embodiment, by increasing the ohmic contact area between the fifth doped region and the first metal layer, the contact resistance can be reduced, thereby improving the short circuit characteristics.
Specifically, the portion of the first doped region contacting the first metal layer forms an ohmic contact, and the portion of the fifth doped region contacting the first metal layer forms an ohmic contact.
In other embodiments, as shown in fig. 2,4 and 6, a portion of the surface of the first metal layer 13 near the substrate 10 is in contact with the epitaxial layer body 111, and a portion of the surface of the first metal layer 13 near the substrate 10 is in schottky contact with the epitaxial layer body 111. In this embodiment, by forming the schottky contact, stability and reliability of the device under high voltage and high current conditions can be improved, because the schottky contact has a lower reverse leakage current and a higher breakdown voltage.
Specifically, the portion of the surface of the first metal layer, which is close to the substrate, and forms schottky contact with the epitaxial layer body is a horizontal schottky contact region, and the length of the horizontal schottky contact region in the first direction is 0.1 μm to 3 μm.
According to still other exemplary embodiments of the present application, as shown in fig. 1 to 6 and fig. 9 to 11, the sixth doped region 20 is in contact with the first metal layer 13, and a portion of the sixth doped region 20 in contact with the first metal layer 13 forms a schottky contact. In this embodiment, the schottky contact is formed at the contact portion between the sixth doped region and the first metal layer, so that the switching speed of the device can be further improved.
Specifically, schottky is configured at the source metal contact position, which is beneficial to reducing the reverse leakage current of the device.
Specifically, the portion of the sixth doped region forming schottky contact with the first metal layer is a vertical schottky contact region.
In particular, the vertical schottky contact region and the horizontal schottky contact region may have the same or different barrier heights, which is not particularly limited by the present application. In particular, the vertical schottky contact region and the horizontal schottky contact region offer the possibility of achieving two barrier heights.
In particular, the P-field stop region is configured in a split manner with the p++ doped region (i.e., the third doped region) to provide a possibility for the configuration of the horizontal schottky contact.
Specifically, the local sidewall SBD region (i.e., the vertical schottky contact region) in combination with the source ohmic contact region (i.e., the portion of the first metal layer in contact with the first doped region and the fifth doped region, respectively) can change the blocking state, and the flow path of the avalanche hole current, which is beneficial to improving the misleading of the BJT transistor.
Specifically, the local side wall SBD area is divided into small sections, and the P-type doped area is fully configured on the periphery, so that the high-temperature electric leakage condition of the SBD area is improved, and meanwhile, the anti-surge capability of the reverse freewheeling diode can be improved.
According to further exemplary embodiments of the present application, as shown in fig. 7and 8, the third doped region 17 is located at least on a portion of the surface of the second doped region 16 remote from the substrate (not shown) and on a sidewall of the sixth doped region 20 adjacent to the first metal layer 13. In this embodiment, the third doped region is disposed on the sidewall of the sixth doped region, which is close to the first metal layer, so as to help reduce parasitic effects, such as parasitic transistor effects, and further improve the switching speed and efficiency of the device.
In other embodiments, as shown in fig. 7, the third doped region 17 is located on the surface of the second doped region 16 away from the substrate and on the sidewall of the sixth doped region 20 near the first metal layer 13.
In other embodiments, as shown in fig. 1 and 9 to 13, the third doped region 17 is located on a surface of the second doped region 16 away from the substrate 10.
Specifically, the third doped region may be provided to the entire bottom of the trench or to a part of the bottom.
Specifically, the change of the implantation position of the P-field stop region can further increase the width of the JFET region, improving the on-characteristics.
In other embodiments, the third doped region has a difference in the projection pattern on the substrate. Specifically, the projection pattern of the third doped region on the substrate may be different at different positions in the second direction, the second direction is perpendicular to the first direction, and the second direction is perpendicular to the thickness direction of the substrate.
Specifically, the third doped region may have a pattern difference in the second direction, and the semiconductor structure is cut at two different positions in the second direction, so that the third doped region may have a difference in two cross-sectional views, such as fig. 5 and fig. 6.
Specifically, the first doped region may have a pattern difference in the second direction, and the semiconductor structure is cut at two different positions in the second direction, so that the first doped region may be different in the two cross-sectional views, such as fig. 9 and 10.
In other embodiments, as shown in fig. 1 to 13, there are two grooves 112, and the two grooves 112 are spaced apart in the first direction.
Specifically, as shown in fig. 1 to 13, the sixth doped region 20 may be disposed entirely or partially between two of the trenches 112.
Specifically, the number of the third doped regions is two, and the specific positions of the first third doped region (i.e., the third doped region under the first trench) and the second third doped region (i.e., the third doped region under the second trench) may be different or the same, which is not particularly limited in the present application. For example, a first third doped region is located below the isolation dielectric in the first trench and a second doped region is located below the first metal layer in the second trench.
In other embodiments, as shown in fig. 1 and 2, the semiconductor structure further includes a second metal layer 21 on a surface of the substrate 10 remote from the epitaxial layer 11.
Specifically, the semiconductor structure in the application is a trench gate MOSFET, wherein the first metal layer is used as a source electrode, and the second metal layer is used as a drain electrode.
Specifically, in the embodiment of the application, the first metal layer is used as source metal, the second metal layer is used as drain metal, the first doped region is used as a p+ doped region, the second doped region is used as a P field stop region, the third doped region is used as a source p++ doped region, the fourth doped region is used as a P well region, the fifth doped region is used as a source n+ doped region, and the sixth doped region is used as an nJFET region.
The embodiment of the application also provides a preparation method of the semiconductor structure, which comprises the following steps that step 1, a nBuffer epitaxial layer (namely a first sub-epitaxial layer) and a ndrift epitaxial layer (namely a second sub-epitaxial layer) are epitaxially grown on an n+ silicon carbide substrate; the method comprises the steps of forming an nJFET region (namely a sixth doped region) on an epitaxial layer ndrift by injection, forming a P well region (namely a fourth doped region) in the nJFET region by injection, forming a patterned P+ doped region (namely a first doped region) and an N+ doped region (namely a fifth doped region) in the P well region by injection, forming a trench shared by a gate source by an etching process, forming a P field stop region (namely a second doped region) at the bottom of the trench by injection, forming a patterned P++ doped region (namely a third doped region) at the bottom of the trench and part of the side wall of the trench, annealing and activating doping at a high temperature of 1600-1800 ℃, covering a carbon film, performing a sacrificial oxidation injection damage layer, performing wet etching to remove the sacrificial oxide layer, forming SiO 2 by SiC thermal oxidation, or a process of directly depositing SiO 2 or a process of depositing Si oxide into SiO 2, forming polysilicon on the gate oxide layer, forming a gate electrode (namely a gate electrode) by etching process, forming polysilicon, wherein the polysilicon is required to be subjected to voltage regulation and control the gate resistance, and the gate dielectric layer is removed, and the step 12 is removed;
Step 13, forming an isolation oxide layer on part of the N+ doped region and part of the P+ doped region, depositing metals or alloys such as Ni, forming ohmic contact with the P+ doped region and part of the N+ doped region contacted with the metals after high-temperature annealing, and removing unreacted metals;
step 14, depositing metals or alloys (namely a first metal layer) such as Ti and the like by a sputtering or evaporation method, and forming a Schottky contact with the ndrift epitaxial layer contacted with the metals after high-temperature annealing;
And step 16, turning the wafer, thinning the substrate, and depositing metal to form a back ohmic contact (namely a second metal layer) serving as a drain electrode of the device.
The embodiment of the application also provides a semiconductor device which comprises any one of the semiconductor structures.
In the above embodiment, the semiconductor device includes a semiconductor structure, where the semiconductor structure includes a substrate, an epitaxial layer located on a surface of the substrate, a gate structure, a first metal layer, and a first doped region, where the epitaxial layer includes an epitaxial layer body and a trench, the trench is located in the epitaxial layer body, the gate structure and the first metal layer are located at least in the trench, respectively, in a first direction, the first metal layer is located at one side of the gate structure, the first direction is perpendicular to a thickness direction of the substrate, the first doped region is located in the epitaxial layer body, the first doped region is located at a side of the first metal layer away from the gate structure, and the first doped region contacts the first metal layer, and a doping type of the first doped region is different from a doping type of the epitaxial layer. Compared with the prior art that the trench-gate MOSFET is difficult to ensure the firmness of the trench bottom and the small cell size, the first metal layer and the gate structure are configured in the same trench, so that the limitation of the decoupling trench digging process capability on the small-size cell width (the width of the gate and the width of the source can be reduced) is facilitated, the whole cell size is further facilitated to be reduced, the first metal layer is positioned in the trench and contacted with part of the side wall of the trench, and is positioned on one side of the gate structure in the first direction, so that stable electrical connection is facilitated, an additional conductive path can be provided on one side of the gate structure, current density is facilitated to be dispersed, current concentration is reduced, parasitic capacitance is reduced, the firmness of a device is improved, and in addition, the doping type of the first doping region is different from that of the epitaxial layer, so that a good PN junction is facilitated to be formed, and the electrical stability of the device is improved.
From the above description, it can be seen that the above embodiments of the present application achieve the following technical effects:
1) In the semiconductor structure, the semiconductor structure comprises a substrate, an epitaxial layer, a grid electrode structure, a first metal layer and a first doping region, wherein the epitaxial layer is arranged on the surface of the substrate, the epitaxial layer comprises an epitaxial layer body and a groove, the groove is arranged in the epitaxial layer body, the grid electrode structure and the first metal layer are respectively arranged at least in the groove, in the first direction, the first metal layer is arranged on one side of the grid electrode structure, the first direction is perpendicular to the thickness direction of the substrate, the first doping region is arranged in the epitaxial layer body, the first doping region is arranged on one side, far away from the grid electrode structure, of the first metal layer, the first doping region is in contact with the first metal layer, and the doping type of the first doping region is different from that of the epitaxial layer. Compared with the prior art that the trench-gate MOSFET is difficult to ensure the firmness of the trench bottom and the small cell size, the first metal layer and the gate structure are configured in the same trench, so that the limitation of the decoupling trench digging process capability on the small-size cell width (the width of the gate and the width of the source can be reduced) is facilitated, the whole cell size is further facilitated to be reduced, the first metal layer is positioned in the trench and contacted with part of the side wall of the trench, and is positioned on one side of the gate structure in the first direction, so that stable electrical connection is facilitated, an additional conductive path can be provided on one side of the gate structure, current density is facilitated to be dispersed, current concentration is reduced, parasitic capacitance is reduced, the firmness of a device is improved, and in addition, the doping type of the first doping region is different from that of the epitaxial layer, so that a good PN junction is facilitated to be formed, and the electrical stability of the device is improved.
2) In the semiconductor device, the semiconductor device comprises a semiconductor structure, wherein the semiconductor structure comprises a substrate, an epitaxial layer, a grid electrode structure, a first metal layer and a first doping region, the epitaxial layer is arranged on the surface of the substrate, the epitaxial layer comprises an epitaxial layer body and a groove, the groove is arranged in the epitaxial layer body, the grid electrode structure and the first metal layer are respectively arranged in the groove at least, in a first direction, the first metal layer is arranged on one side of the grid electrode structure, the first direction is perpendicular to the thickness direction of the substrate, the first doping region is arranged in the epitaxial layer body, the first doping region is arranged on one side of the first metal layer, which is far away from the grid electrode structure, and is in contact with the first metal layer, and the doping type of the first doping region is different from that of the epitaxial layer. Compared with the prior art that the trench-gate MOSFET is difficult to ensure the firmness of the trench bottom and the small cell size, the first metal layer and the gate structure are configured in the same trench, so that the limitation of the decoupling trench digging process capability on the small-size cell width (the width of the gate and the width of the source can be reduced) is facilitated, the whole cell size is further facilitated to be reduced, the first metal layer is positioned in the trench and contacted with part of the side wall of the trench, and is positioned on one side of the gate structure in the first direction, so that stable electrical connection is facilitated, an additional conductive path can be provided on one side of the gate structure, current density is facilitated to be dispersed, current concentration is reduced, parasitic capacitance is reduced, the firmness of a device is improved, and in addition, the doping type of the first doping region is different from that of the epitaxial layer, so that a good PN junction is facilitated to be formed, and the electrical stability of the device is improved.
The above description is only of the preferred embodiments of the present application and is not intended to limit the present application, but various modifications and variations can be made to the present application by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application.
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