CN120456589A - Semiconductor structure and method for forming the same - Google Patents

Abstract

The semiconductor structure comprises a substrate, a fin portion, an isolation layer, a gate layer, a first gate dielectric layer, a second gate dielectric layer and a gate layer, wherein the substrate comprises a first region and a second region, the device working voltage of the first region is smaller than that of the second region, the fin portion is separated on the substrate of the first region and the second region, the isolation layer is located on the substrate and surrounds part of the side wall of the fin portion, the fin portion exposed by the isolation layer is used as an effective fin portion, the height of the effective fin portion of the first region is larger than that of the effective fin portion of the second region, the first gate dielectric layer is located on the effective fin portion of the second region, the thickness of the second gate dielectric layer is smaller than that of the first gate dielectric layer, the gate layer stretches across the effective fin portion and covers part of the top and part of the side wall of the effective fin portion. The embodiment of the invention reduces the depth-to-width ratio of the space surrounded by the first gate dielectric layer and the isolation layer and reduces the probability of generating defects such as gaps, holes and the like in the gate layer of the second region.

Description

Semiconductor structure and forming method thereof

Technical Field

Embodiments of the present disclosure relate to semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.

Background

With the rapid development of the semiconductor integrated circuit (INTEGRATED CIRCUIT, IC) industry, semiconductor technology is continually driven by moore's law toward smaller process nodes, resulting in the development of integrated circuits with smaller volumes, higher circuit accuracy, and higher circuit complexity.

To better accommodate the demand for device scaling, semiconductor processes are gradually beginning to transition from planar transistors to three-dimensional transistors with higher power, such as fin field effect transistors (FINFIELD EFFECT transistors, finfets), and the like. In the Fin-type field effect transistor, three sides of the gate surround a Fin-shaped channel, and compared with a planar transistor, the Fin-type field effect transistor has stronger control capability of the gate on the channel and can better inhibit short channel effect.

However, the performance of the fin field effect transistor is still to be improved.

Disclosure of Invention

The embodiment of the invention provides a semiconductor structure and a forming method thereof, which are used for improving the performance of the semiconductor structure.

In order to solve the problems, the embodiment of the invention provides a semiconductor structure, which comprises a substrate, a fin portion, an isolation layer, a gate layer, a first gate dielectric layer and a second gate dielectric layer, wherein the substrate comprises a first region and a second region, the device working voltage of the first region is smaller than that of the second region, the fin portion is separated on the substrate of the first region and the second region, the isolation layer is located on the substrate and surrounds part of the side wall of the fin portion, the fin portion exposed by the isolation layer is used as an effective fin portion, the height of the effective fin portion of the first region is larger than that of the effective fin portion of the second region, the first gate dielectric layer is located on the effective fin portion of the second region, the thickness of the second gate dielectric layer is smaller than that of the first gate dielectric layer, the gate layer spans the effective portion and covers the part of the side wall of the first gate dielectric layer and the second gate dielectric layer, and the gate layer covers the part of the side wall of the top of the effective fin portion.

Correspondingly, the embodiment of the invention also provides a method for forming the semiconductor structure, which comprises the steps of providing a substrate, wherein the substrate comprises a first region and a second region, the device working voltage of the first region is smaller than that of the second region, fin parts which are separated from each other are formed on the substrate of the first region and the substrate of the second region, an isolation layer surrounding the fin parts is formed on the substrate of the side parts of the fin parts, the fin parts exposed by the isolation layer are used as effective fin parts, the height of the effective fin parts of the first region is larger than that of the effective fin parts of the second region, a first gate dielectric layer is formed on the effective fin parts of the second region, the thickness of the second gate dielectric layer is smaller than that of the first gate dielectric layer, a grid layer which spans the effective fin parts is formed on the substrate of the side parts of the first gate dielectric layer and the second gate dielectric layer, and the grid layer covers the top parts and the side walls of the effective fin parts.

Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:

The semiconductor structure provided by the embodiment of the invention comprises the isolation layer which is positioned on the substrate and surrounds part of the side wall of the fin part, the fin part exposed by the isolation layer is used as an effective fin part, the height of the effective fin part of the first region is larger than that of the effective fin part of the second region, the first gate dielectric layer is positioned on the effective fin part of the second region, the second gate dielectric layer is positioned on the effective fin part of the first region, and the thickness of the first gate dielectric layer is larger than that of the second gate dielectric layer. Although the thickness of the first gate dielectric layer is greater than that of the second gate dielectric layer, the height of the effective fin portion of the second region is smaller than that of the first region, so that the depth-to-width ratio of a space surrounded by the first gate dielectric layer and the isolation layer between adjacent effective fin portions of the second region is reduced, and accordingly the top position of the space is not easy to be sealed prematurely in the process of forming the gate layer, thereby reducing the probability of generating defects such as gaps (sea) and hollows in the gate layer of the second region, improving the uniformity of the thickness of the gate layer, correspondingly improving the uniformity of the performance of a semiconductor device, and further improving the performance of a semiconductor structure.

In the method for forming the semiconductor structure provided by the embodiment of the invention, the isolation layer surrounding the fin part is formed on the substrate at the side part of the fin part, the fin part exposed by the isolation layer is used as the effective fin part, the height of the effective fin part of the first region is larger than that of the effective fin part of the second region, the first gate dielectric layer is formed on the effective fin part of the second region, the second gate dielectric layer is formed on the effective fin part of the first region, and the thickness of the first gate dielectric layer is larger than that of the second gate dielectric layer. Although the thickness of the first gate dielectric layer is greater than that of the second gate dielectric layer, the height of the effective fin portion of the second region is smaller than that of the effective fin portion of the first region, so that the depth-to-width ratio of a space surrounded by the first gate dielectric layer and the isolation layer between adjacent effective fin portions of the second region is reduced, and accordingly the top position of the space is not easy to be sealed prematurely in the process of forming the gate layer, thereby reducing the probability of generating defects such as gaps and hollows in the gate layer of the second region, improving the uniformity of the thickness of the gate layer, correspondingly improving the uniformity of the performance of a semiconductor device, and further improving the performance of a semiconductor structure.

Drawings

Fig. 1 to 9 are schematic structural views corresponding to steps in a method for forming a semiconductor structure;

FIG. 10 is a schematic diagram of a semiconductor structure according to an embodiment of the present invention;

FIG. 11 is a schematic diagram of the structure of FIG. 10 with the second gate dielectric layer and gate layer omitted;

Fig. 12 to 22 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.

Detailed Description

Currently, the performance of semiconductor structures is still to be improved. The method for forming the semiconductor structure is combined, and the reason that the performance of the semiconductor structure needs to be improved is analyzed. Fig. 1 to 9 are schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure.

Referring to fig. 1, a substrate 10 is provided, the substrate including a first region i 'and a second region ii', the device operating voltage of the first region i 'being less than the device operating voltage of the second region ii', the substrate 10 of the first region i 'and the second region ii' each having a fin 11 formed thereon that is discrete from each other.

Referring to fig. 2 to 3, an isolation layer 12 surrounding the fin 11 is formed on the substrate 10 at the side of the fin 11, and the fin 11 exposed by the isolation layer 12 serves as an effective fin 13.

Referring to fig. 4 to 5, a first gate dielectric layer 14 is formed on the active fin 13 of the second region ii'.

Referring to fig. 6, a second gate dielectric layer 15 is formed on the effective fin portion 13 of the first region i', and the thickness of the second gate dielectric layer 15 is smaller than that of the first gate dielectric layer 14.

Referring to fig. 7 to 9, fig. 9 is a partially enlarged view of region a of fig. 8, a gate layer 16 is formed on the first gate dielectric layer 14 and the second gate dielectric layer 15 to span the effective fin 13, and the gate layer 16 covers a portion of the top and a portion of the sidewall of the effective fin 13.

It has been found that, since the device operating voltage of the first region i 'is smaller than the device operating voltage of the second region ii', i.e., the device operating voltage of the second region ii 'is greater than the device operating voltage of the first region i', the thickness of the first gate dielectric layer 14 in the second region ii 'needs to be greater than the thickness of the second gate dielectric layer 15 in the first region i', i.e., the thickness of the second gate dielectric layer 15 is smaller than the thickness of the first gate dielectric layer 14, so that the depth-to-width ratio of the space enclosed by the first gate dielectric layer 14 and the isolation layer 12 between adjacent effective fins 13 in the second region ii 'is relatively large, and thus the top position of the space is easily and prematurely closed in the process of forming the gate layer 16, and thus defects such as gaps 17, voids and the like are generated in the gate layer 16 in the second region ii' (as shown in fig. 9), so that the uniformity of the thickness of the gate layer 16 is poor, and the performance of the semiconductor structure is affected.

In order to solve the technical problems, the embodiment of the invention provides a semiconductor structure, which comprises a substrate, a fin portion, an isolation layer, a gate layer, a first gate dielectric layer and a second gate dielectric layer, wherein the substrate comprises a first region and a second region, the device working voltage of the first region is smaller than that of the second region, the fin portion is separated on the substrate of the first region and the second region, the isolation layer is located on the substrate and surrounds part of the side wall of the fin portion, the fin portion exposed by the isolation layer is used as an effective fin portion, the height of the effective fin portion of the first region is larger than that of the effective fin portion of the second region, the first gate dielectric layer is located on the effective fin portion of the second region, the thickness of the second gate dielectric layer is smaller than that of the first gate dielectric layer, the gate layer spans the effective portion and covers the part of the side wall of the first gate dielectric layer and the second gate dielectric layer, and the gate layer covers the part of the top of the effective fin portion.

The semiconductor structure provided by the embodiment of the invention comprises the isolation layer which is positioned on the substrate and surrounds part of the side wall of the fin part, the fin part exposed by the isolation layer is used as an effective fin part, the height of the effective fin part of the first region is larger than that of the effective fin part of the second region, the first gate dielectric layer is positioned on the effective fin part of the second region, the second gate dielectric layer is positioned on the effective fin part of the first region, and the thickness of the first gate dielectric layer is larger than that of the second gate dielectric layer. Although the thickness of the first gate dielectric layer is greater than that of the second gate dielectric layer, the height of the effective fin portion of the second region is smaller than that of the effective fin portion of the first region, so that the depth-to-width ratio of a space surrounded by the first gate dielectric layer and the isolation layer between adjacent effective fin portions of the second region is reduced, and accordingly the top position of the space is not easy to be sealed prematurely in the process of forming the gate layer, thereby reducing the probability of generating defects such as gaps and hollows in the gate layer of the second region, improving the uniformity of the thickness of the gate layer, correspondingly improving the uniformity of the performance of a semiconductor device, and further improving the performance of a semiconductor structure.

In order that the above objects, features and advantages of embodiments of the invention may be readily understood, a more particular description of embodiments of the invention will be rendered by reference to the appended drawings.

Fig. 10 is a schematic structural diagram of an embodiment of the semiconductor structure of the present invention, and fig. 11 is a schematic structural diagram of fig. 10 with the second gate dielectric layer and the gate layer omitted.

Referring to fig. 10 to 11, in this embodiment, the semiconductor structure includes a substrate 100, the substrate 100 includes a first region i and a second region ii, the device operating voltage of the first region i is smaller than the device operating voltage of the second region ii, a fin 110 separated on the substrate 100 of the first region i and the second region ii, an isolation layer 120 located on the substrate 100 and surrounding a portion of a sidewall of the fin 110, the fin 110 exposed by the isolation layer 120 serving as an effective fin 111, the effective fin 111 of the first region i having a height greater than the effective fin 111 of the second region ii, a first gate dielectric layer 140 located on the effective fin 111 of the second region ii, a second gate dielectric layer 150 located on the effective fin 111 of the first region i, the thickness of the second gate dielectric layer 150 being smaller than the thickness of the first gate dielectric layer 140, and a gate layer 160 located across the effective fin 111 and covering the first gate dielectric layer 140 and the second gate dielectric layer 150, and the gate layer 160 covering a portion of the top and a portion of the sidewall of the effective fin 111.

Here, the height of the effective fin 111 refers to a distance in a normal direction along the top surface of the substrate 100.

The substrate 100 is used to provide a process platform for the formation of semiconductor structures.

In this embodiment, the substrate 100 is used to form a field effect transistor. As one example, substrate 100 is used to form a fin field effect transistor.

In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the substrate may be made of germanium, silicon carbide, gallium arsenide, indium gallium arsenide, or other materials, and the substrate may be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates.

The substrate 100 includes a first region i and a second region ii.

The first region i and the second region ii are used to form field effect transistors having different operating voltages.

In this embodiment, the first region I is used to form a Core device (Core device), and the second region ii is used to form an Input/Output device (I/O device).

The core device mainly refers to a device used in the chip, usually adopts lower voltage and has higher working frequency, the input/output device generally refers to a device used when the chip interacts with an external interface, the working voltage of the device is generally higher, the working voltage of the input/output device is generally larger than the working voltage of the core device, and the working frequency of the input/output device is generally smaller than the working frequency of the core device.

The fins 110 provide a process basis for forming the effective fins 111.

In this embodiment, the material of the fin 110 includes silicon. In other embodiments, the fin material may also include other materials such as germanium, silicon germanium, III-V semiconductor materials, and the like.

As an example, the fin 110 and the substrate 100 are a unitary structure.

The isolation layer 120 is used to achieve isolation between adjacent fins 110, and to achieve isolation between the substrate 100 and the individual semiconductor devices.

In this embodiment, the isolation layer 120 is a shallow trench isolation structure (Shallow Trench Isolation, STI). As an example, the material of the isolation layer 120 is silicon oxide. In other embodiments, the material of the isolation layer may be silicon nitride or other dielectric materials such as silicon oxynitride.

In this embodiment, the thickness of the isolation layer 120 in the first region i is smaller than the thickness of the isolation layer 120 in the second region ii along the normal direction of the top surface of the substrate 100.

The step of forming the isolation layer 120 generally includes forming an isolation material layer (not shown) around the fin 110 on the substrate 100 on the sides of the fin 110, the isolation material layer covering the top and sidewalls of the fin 110, removing a first portion of the isolation material layer of the second region ii to form an effective fin 111 in the second region ii, removing a second portion of the isolation material layer of the first region i to form an effective fin 111 in the first region i, the second portion having a thickness greater than the first portion, removing the first portion of the isolation material layer of the second region ii, and removing the second portion of the isolation material layer of the first region i, the remaining isolation material layer being the isolation layer 120. Therefore, the thickness of the isolation layer 120 of the first region i is smaller than the thickness of the isolation layer 120 of the second region ii, so that the effective fin 111 height of the first region i is greater than the effective fin 111 height of the second region ii.

In other embodiments, the fin height of the first region may be greater than the fin height of the second region, such that when the thickness of the isolation layer of the first region is equal to the thickness of the isolation layer of the second region, the effective fin height of the first region is still greater than the effective fin height of the second region.

The active fin (ACTIVE FIN) 111 is used to provide a conductive channel when the semiconductor device is in operation.

Although the thickness of the first gate dielectric layer 140 is greater than the thickness of the second gate dielectric layer 150, the height of the effective fin 111 in the first region i is greater than the height of the effective fin 111 in the second region ii, so that the depth-to-width ratio of the space 142 surrounded by the first gate dielectric layer 140 and the isolation layer 120 between adjacent effective fin 111 in the second region ii is reduced, and accordingly the top position of the space 142 is not easily and prematurely sealed in the process of forming the gate layer 160, thereby reducing the probability of generating defects such as gaps and hollows in the gate layer 160 in the second region ii, improving the uniformity of the thickness of the gate layer 160, correspondingly improving the uniformity of the performance of the semiconductor device, and further improving the performance of the semiconductor structure.

In this embodiment, the first region i is used to form a core device and the second region ii is used to form an input/output device. The operating frequency of the input/output devices is typically less than the operating frequency of the core devices. Therefore, the effective fin 111 height of the first region i is greater than the effective fin 111 height of the second region ii, that is, the effective fin 111 height of the second region ii is smaller than the effective fin 111 height of the first region i, and the influence on the operating frequency of the input/output device is small.

It should be noted that, along the normal direction of the top surface of the substrate 100, the height difference between the effective fin 111 of the first region i and the effective fin 111 of the second region ii should not be too small or too large. If the height difference between the effective fin 111 of the first region i and the effective fin 111 of the second region ii is too small, the effect of reducing the aspect ratio of the space 142 surrounded by the first gate dielectric layer 140 and the isolation layer 120 between adjacent effective fin 111 of the second region ii is not good, and if the height difference between the effective fin 111 of the first region i and the effective fin 111 of the second region ii is too large, the height of the effective fin 111 of the second region ii is too small, so that the design requirement is difficult to meet. In this embodiment, the difference in height between the effective fin 111 of the first region i and the effective fin 111 of the second region ii is 50 to 200 a in the normal direction of the top surface of the substrate 100.

The first gate dielectric layer 140 is used to isolate the gate layer 160 from the substrate 100 in the second region ii.

In this embodiment, the material of the first gate dielectric layer 140 is a dielectric material. As an example, the material of the first gate dielectric layer 140 is silicon oxide. In other embodiments, the material of the first gate dielectric layer may be other suitable dielectric materials.

It should be noted that, between the adjacent effective fins 111 in the second region ii, the depth and width of the space 142 enclosed by the first gate dielectric layer 140 and the isolation layer 120 should not be too large. If the aspect ratio of the space 142 surrounded by the first gate dielectric layer 140 and the isolation layer 120 is too large, defects such as gaps and voids generated in the gate layer 160 in the second region ii are easily reduced during the formation of the gate layer 160. In this embodiment, the aspect ratio of the space 142 surrounded by the first gate dielectric layer 140 and the isolation layer 120 between the adjacent effective fins 111 in the second region ii is less than 1.5:1.

The second gate dielectric layer 150 is used to isolate the gate layer 160 from the substrate 100 of the first region i.

Since the device operating voltage of the first region i is smaller than that of the second region II, the thickness of the second gate dielectric layer 150 is also required to be smaller correspondingly, and thus, the thickness of the second gate dielectric layer 150 is smaller than that of the first gate dielectric layer 140.

Although the thickness of the first gate dielectric layer 140 is greater than the thickness of the second gate dielectric layer 150, the height of the effective fin 111 in the second region ii is smaller than that of the effective fin 111 in the first region i, so that the depth-to-width ratio of the space 142 surrounded by the first gate dielectric layer 140 and the isolation layer 120 between the adjacent effective fin 111 in the second region ii is reduced, and accordingly the top position of the space 142 is not easy to be sealed prematurely in the process of forming the gate layer 160, thereby reducing the probability of generating defects such as gaps and hollows in the gate layer 160 in the second region ii, improving the uniformity of the thickness of the gate layer 160, correspondingly improving the uniformity of the performance of the semiconductor device, and further improving the performance of the semiconductor structure.

In this embodiment, the material of the second gate dielectric layer 150 is a dielectric material. As an example, the material of the second gate dielectric layer 150 is silicon oxide. In other embodiments, the material of the second gate dielectric layer may be other suitable dielectric materials.

In this embodiment, the second gate dielectric layer 150 also covers the first gate dielectric layer 140.

The second gate dielectric layer 150 also covers the first gate dielectric layer 140, which is beneficial to simplifying the process steps and saving the process cost.

The gate layer 160 is used to control the turning on or off of the conductive channel when the device is in operation.

In this embodiment, the gate layer 160 includes one or more work function layers 161.

The work function layer 161 is used to adjust the work function of the gate layer 160, thereby adjusting the threshold voltage of the field effect transistor.

Since the threshold voltage requirements of the field effect transistor may be different in each region, the thickness of the work function layer 161 may be different in each region. Therefore, it is necessary to provide different numbers of work function layers in each region to adjust the threshold voltage requirements of the field effect transistor in each region.

It is to be noted that reducing the probability of defects such as gaps and voids occurring in the gate layer 160 in the second region ii is also advantageous in improving the uniformity of the thickness of the work function layer 161.

Specifically, when the NMOS transistor is formed, the work function layer 161 is an N-type work function layer, the material of the work function layer includes one or more of titanium aluminide, tantalum carbide, aluminum, or titanium carbide, and when the PMOS transistor is formed, the work function layer 161 is a P-type work function layer, the material of the work function layer includes one or more of titanium nitride, tantalum nitride, titanium carbide, tantalum silicon nitride, titanium silicon nitride, and tantalum carbide.

In this embodiment, the gate layer 160 further includes a gate electrode layer (not shown) covering the work function layer 161.

The gate electrode layer serves as an external electrode for electrically connecting the gate layer 160 to an external circuit.

Specifically, the gate electrode layer 160 is a conductive material such as titanium aluminide, tungsten, aluminum, copper, silver, gold, platinum, nickel, or titanium.

In this embodiment, the semiconductor structure further includes a gate sidewall (not shown) on the sidewall of the gate layer, a source/drain doped layer (not shown) in the effective fin 111 on both sides of the gate layer 160, and an interlayer dielectric layer (not shown) covering the source/drain doped layer and the top of the gate layer 160.

The gate sidewall is used for defining the formation position of the source/drain doped layer in the process of forming the source/drain doped layer and protecting the sidewall of the gate layer 160. The grid side wall can be of a single-layer structure or a laminated structure, and the material of the grid side wall comprises one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride oxide, silicon oxynitride, boron nitride and boron carbonitride.

The source-drain doped layer is used as a source region or a drain region of the formed transistor. Specifically, the material of the source-drain doped layer may include silicon germanium doped with P-type ions including B, ga or In, and the material of the source-drain doped layer may also include silicon or silicon carbide doped with N-type ions including P, as or Sb.

The interlayer dielectric layer is used for isolating adjacent devices. Specifically, the material of the interlayer dielectric layer comprises one or more of silicon oxide, silicon nitride, silicon carbide nitride, silicon boride nitride, silicon oxycarbide nitride and silicon oxynitride.

Correspondingly, the invention further provides a method for forming the semiconductor structure. Fig. 12 to 22 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.

Referring to fig. 12, a substrate 500 is provided, the substrate 500 including a first region I and a second region II, the first region I having a device operating voltage less than that of the second region II, the first region I and the second region II each having a fin 510 formed thereon that is separate from each other.

The substrate 500 is used to provide a process platform for subsequent processing.

In this embodiment, the substrate 500 is used to form a field effect transistor. As one example, substrate 500 is used to form a fin field effect transistor.

In this embodiment, the substrate 500 is a silicon substrate. In other embodiments, the substrate may be made of germanium, silicon carbide, gallium arsenide, indium gallium arsenide, or other materials, and the substrate may be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates.

The substrate 500 includes a first region I and a second region II.

The first region I and the second region II are used for forming field effect transistors with different operating voltages.

In this embodiment, the first region I is used to form a core device, and the second region II is used to form an input/output device.

The core device mainly refers to a device used in the chip, usually adopts lower voltage and has higher working frequency, the input/output device generally refers to a device used when the chip interacts with an external interface, the working voltage of the device is generally higher, the working voltage of the input/output device is generally larger than the working voltage of the core device, and the working frequency of the input/output device is generally smaller than the working frequency of the core device.

Fin 510 provides a process basis for subsequently forming an effective fin.

In this embodiment, the material of fin 510 includes silicon. In other embodiments, the fin material may also include other materials such as germanium, silicon germanium, III-V semiconductor materials, and the like.

As one example, the fin 510 and the substrate 500 are a unitary structure.

Referring to fig. 13 to 17, an isolation layer 520 surrounding the fin 510 is formed on the substrate 500 at the side of the fin 510, the fin 510 exposed by the isolation layer 520 serves as an effective fin 511, and the effective fin 511 of the first region I has a height greater than that of the effective fin 511 of the second region II.

Here, the height of the effective fin 511 refers to a distance in a normal direction along the top surface of the substrate 500.

The isolation layer 520 is used to achieve isolation between adjacent fins 510, as well as isolation between the substrate 500 and subsequently formed individual semiconductor devices.

In this embodiment, the isolation layer 520 is a shallow trench isolation structure. As an example, the material of the isolation layer 520 is silicon oxide. In other embodiments, the material of the isolation layer may be silicon nitride or other dielectric materials such as silicon oxynitride.

In this embodiment, the step of forming the isolation layer 520 includes forming an isolation material layer 521 around the fin 510 on the substrate 500 on the side of the fin 510, the isolation material layer 521 covering the top and the sidewall of the fin 510, removing a first portion of the isolation material layer 521 in the second region II to form an effective fin 511 in the second region II, removing a second portion of the isolation material layer 521 in the first region I to form an effective fin 511 in the first region I, the second portion having a thickness greater than the first portion, removing the first portion of the isolation material layer 521 in the second region II, and removing the second portion of the isolation material layer 521 in the first region I, wherein the remaining isolation material layer 521 serves as the isolation layer 520.

The isolation material layer 521 surrounding the fin 510 is formed on the substrate 500 at the side of the fin 510, and then the isolation material layer 521 of the first partial thickness of the second region II is removed, and the isolation material layer 521 of the second partial thickness of the first region I is removed, wherein the second partial thickness is greater than the first partial thickness, so that the thickness of the remaining isolation material layer 521 of the second region II is greater than the thickness of the remaining isolation material layer 521 of the first region I, and thus the effective fin 511 height of the first region I is greater than the effective fin 511 height of the second region II.

In other embodiments, the fin height of the first region may be greater than the fin height of the second region in the step of providing the substrate, so that the effective fin height of the first region is still greater than the effective fin height of the second region when the thickness of the isolation layer of the first region is equal to the thickness of the isolation layer of the second region in the step of forming the isolation layer.

Specifically, the step of removing the isolation material layer 521 of the second partial thickness of the first region I includes removing the isolation material layer 521 of the first partial thickness of the second region II and the first partial thickness of the first region I (as shown in FIG. 14), and removing the isolation material layer 521 of the third partial thickness of the first region I after removing the isolation material layer 521 of the first partial thickness, wherein the sum of the first partial thickness and the third partial thickness is the second partial thickness (as shown in FIG. 16).

In the step of removing the isolation material layer 521 of the first partial thickness of the second region II, after removing the isolation material layer 521 of the first partial thickness of the second region II and the first region I, removing the isolation material layer 521 of the third partial thickness of the first region I, wherein the sum of the first partial thickness and the third partial thickness is the second partial thickness, which is beneficial to reducing the difficulty of removing the isolation material layer 521 of the second partial thickness of the first region I and is also beneficial to combining with the existing process.

More specifically, the process of removing the isolation material layer 521 of the third partial thickness of the first region I includes a dry etching process.

The dry etching process can remove the isolation material layer 521 of the third portion of the thickness of the first region I more uniformly, thereby being beneficial to making the uniformity of the thickness of the isolation layer 520 better and being beneficial to combining with the existing process.

In this embodiment, after removing the isolation material layer 521 of the second region II and the first region I, before removing the isolation material layer 521 of the first region I, a first mask layer 530 is formed on the isolation material layer 521 of the second region II (as shown in fig. 15), and during removing the isolation material layer 521 of the first region I of the third region, the first mask layer 530 is used to protect the isolation material layer 521 of the second region II (as shown in fig. 16), and after forming the isolation layer 520, a first mask layer 530 is removed (as shown in fig. 17).

Before removing the isolation material layer 521 of the third part of the thickness of the first region I, the first mask layer 530 is formed on the isolation material layer 521 of the second region II, so that the first mask layer 530 can protect the isolation material layer 521 of the second region II during the process of removing the isolation material layer 521 of the third part of the thickness of the first region I, thereby being beneficial to reducing the damage probability of the isolation material layer 521 of the second region II, improving the quality of the isolation material layer 521 of the second region II, correspondingly improving the quality of the isolation layer 520 of the second region II, and reducing the difficulty of removing the isolation material layer 521 of the third part of the thickness of the first region I.

Note that the process of forming the first mask layer 530 includes a spin coating process, an exposure process, and a development process. The spin coating process, the exposure process and the development process have the characteristics of high process maturity, low process cost and the like.

It should be further noted that, in the step of forming the first mask layer 530, the material of the first mask layer 530 includes photoresist.

The material of the first mask layer 530 includes photoresist to facilitate subsequent removal of the first mask layer 530. In other embodiments, the first mask layer may be another spin-on material or another material that can obtain better flatness of the first mask layer 530.

It should be further noted that the process of removing the first mask layer 530 includes one or both of a dry etching process and a wet cleaning process.

The dry etching process is a common process in the semiconductor process, and has higher process maturity.

The wet cleaning process is convenient for removing impurities, and has the characteristics of low process cost, simple and convenient operation and the like.

The active fin 511 is used to provide a conductive channel when the semiconductor device is in operation.

Although the thickness of the subsequently formed first gate dielectric layer is greater than that of the second gate dielectric layer, the height of the effective fin 511 of the first region I is greater than that of the effective fin 511 of the second region II, so that the depth-to-width ratio of a space surrounded by the first gate dielectric layer and the isolation layer 520 between adjacent effective fin 511 of the second region II is reduced, and accordingly the top position of the space is not easy to be sealed prematurely in the process of subsequently forming the gate layer, thereby reducing the probability of generating defects such as gaps and hollows in the gate layer of the second region II, improving the uniformity of the thickness of the gate layer, correspondingly improving the uniformity of the performance of the semiconductor device, and further improving the performance of the semiconductor structure.

In this embodiment, the first region I is used to form a core device, and the second region II is used to form an input/output device. The operating frequency of the input/output devices is typically less than the operating frequency of the core devices. Therefore, the height of the effective fin 511 of the first region I is greater than the height of the effective fin 511 of the second region II, i.e., the height of the effective fin 511 of the second region II is smaller than the height of the effective fin 511 of the first region I, so that the influence on the operating frequency of the input/output device is small.

It should be noted that, the difference in height between the effective fin 511 of the first region I and the effective fin 511 of the second region II should not be too small or too large. If the height difference between the effective fin 511 of the first region I and the effective fin 511 of the second region II is too small, the effect of reducing the space depth-to-width ratio enclosed by the first gate dielectric layer and the isolation layer 520 between adjacent effective fin 511 of the second region II is not good, and if the height difference between the effective fin 511 of the first region I and the effective fin 511 of the second region II is too large, the height of the effective fin 511 of the second region II is too small, so that it is difficult to meet the design requirements. In this embodiment, in the step of forming the isolation layer 520, the difference in height between the effective fin 511 of the first region I and the effective fin 511 of the second region II is 50 to 200 a in the normal direction of the top surface of the substrate 500.

Referring to fig. 18 to 19, a first gate dielectric layer 540 is formed on the effective fin 511 of the second region II.

The first gate dielectric layer 540 is used to isolate the subsequently formed gate layer from the substrate 500 of the second region II.

In this embodiment, the material of the first gate dielectric layer 540 is a dielectric material. As an example, the material of the first gate dielectric layer 540 is silicon oxide. In other embodiments, the material of the first gate dielectric layer may be other suitable dielectric materials.

In this embodiment, the step of forming the first gate dielectric layer 540 includes forming an initial first gate dielectric layer 541 (shown in fig. 18) on the effective fin 511 of the first region I and the effective fin 511 of the second region II, forming a second mask layer (not shown) on the initial first gate dielectric layer 541 of the second region II, where the second mask layer and the first mask layer are formed by the same photomask, removing the initial first gate dielectric layer 541 of the first region I, and using the remaining initial first gate dielectric layer 541 as the first gate dielectric layer 540 (shown in fig. 19), and removing the second mask layer after forming the first gate dielectric layer 540.

The second mask layer and the first mask layer 530 are formed by the same photomask, which is beneficial to saving the number of photomasks, thereby reducing the process cost of manufacturing the integrated circuit.

In this embodiment, the process of forming the first gate dielectric layer 540 includes a furnace thermal oxidation process. In other embodiments, the process of forming the first gate dielectric layer 540 may also include other suitable thermal oxidation processes.

It should be noted that, the first grooves 542 surrounded by the first gate dielectric layer 540 and the isolation layer 520 are formed between the effective fin portions 511 of the adjacent second regions II, and the ratio of the depth to the width of the first grooves 542 should not be too large. If the ratio of the depth to the width of the first groove 542 is too large, the effect of reducing defects such as gaps and voids generated in the gate layer of the second region II in the subsequent gate layer forming process is not good. In this embodiment, in the step of forming the first gate dielectric layer 540 on the effective fin 511 of the second region II, the first groove 542 surrounded by the first gate dielectric layer 540 and the isolation layer 520 is formed between the effective fin 511 of the adjacent second region II, and the ratio of the depth to the width of the first groove 542 is less than 1.5:1.

Referring to fig. 20, a second gate dielectric layer 550 is formed on the effective fin 511 of the first region I, and the thickness of the second gate dielectric layer 550 is smaller than that of the first gate dielectric layer 540.

The second gate dielectric layer 550 is used to isolate the subsequently formed gate layer from the substrate 500 of the first region I.

Since the device operating voltage of the first region I is smaller than the device operating voltage of the second region II, the thickness of the second gate dielectric layer 550 is also required to be smaller correspondingly, and thus, the thickness of the second gate dielectric layer 550 is smaller than the thickness of the first gate dielectric layer 540.

Although the thickness of the first gate dielectric layer 540 is greater than that of the second gate dielectric layer 550, the height of the effective fin 511 of the second region II is smaller than that of the effective fin 511 of the first region I, so that the aspect ratio of the space surrounded by the first gate dielectric layer 540 and the isolation layer 520 between adjacent effective fin 511 of the second region II is reduced, and accordingly the top position of the space is not easy to be sealed prematurely in the subsequent process of forming the gate layer, thereby reducing the probability of generating defects such as gaps and hollows in the gate layer of the second region II, improving the uniformity of the thickness of the gate layer, correspondingly improving the uniformity of the performance of the semiconductor device, and further improving the performance of the semiconductor structure.

In this embodiment, the material of the second gate dielectric layer 550 is a dielectric material. As an example, the material of the second gate dielectric layer 550 is silicon oxide. In other embodiments, the material of the second gate dielectric layer may be other suitable dielectric materials.

In this embodiment, in the step of forming the second gate dielectric layer 550, the second gate dielectric layer 550 also covers the first gate dielectric layer 540.

The second gate dielectric layer 550 also covers the first gate dielectric layer 540, which is beneficial to simplifying the process steps and saving the process cost.

In this embodiment, the process of forming the second gate dielectric layer 550 includes an ozone oxidation process. In other embodiments, the process of forming second gate dielectric layer 550 may also include other suitable thermal oxidation processes.

In this embodiment, after the first gate dielectric layer 540 is formed, the second gate dielectric layer 550 is formed. In other embodiments, the first gate dielectric layer 540 may also be formed after the second gate dielectric layer 550 is formed.

Referring to fig. 21 to 22, a gate layer 560 is formed on the first gate dielectric layer 540 and the second gate dielectric layer 550 across the effective fin 511, the gate layer 560 covering a portion of the top and a portion of the sidewall of the effective fin 511.

The gate layer 560 is used to control the turning on or off of the conductive channel when the device is in operation.

In this embodiment, in the step of forming the gate layer 560, the gate layer 560 includes one or more work function layers 561.

The work function layer 561 is used to adjust the work function of the gate layer 560 and thus the threshold voltage of the field effect transistor.

Note that, since the threshold voltage requirements of the field effect transistor may be different in each region, the thickness of the work function layer 561 may be different in each region. Therefore, it is necessary to provide different numbers of work function layers in each region to adjust the threshold voltage requirements of the field effect transistor in each region.

It is to be noted that reducing the probability of defects such as gaps and voids occurring in the gate layer 560 in the second region II is also advantageous in improving the uniformity of the thickness of the work function layer 561.

Specifically, when the NMOS transistor is formed, the work function layer 561 is an N-type work function layer, the material of the work function layer includes one or more of titanium aluminide, tantalum carbide, aluminum, or titanium carbide, and when the PMOS transistor is formed, the work function layer 561 is a P-type work function layer, the material of the work function layer includes one or more of titanium nitride, tantalum nitride, titanium carbide, tantalum silicon nitride, titanium silicon nitride, and tantalum carbide.

In the step of forming the gate layer 560 in this embodiment, the gate layer 560 further includes a gate electrode layer (not shown) covering the work function layer 561.

The gate electrode layer is used as an external electrode for electrically connecting the gate layer 560 to an external circuit.

Specifically, the gate electrode layer is a conductive material such as titanium aluminide, tungsten, aluminum, copper, silver, gold, platinum, nickel, or titanium.

In this embodiment, after the first gate dielectric layer 540 and the second gate dielectric layer 550 are formed and before the gate layer 560 is formed, the method further includes forming a dummy gate layer (not shown) crossing over the effective fin 511 on the first gate dielectric layer 540 and the second gate dielectric layer 550, forming gate sidewalls (not shown) on sidewalls of the dummy gate layer, forming source-drain doped layers (not shown) in the effective fin 511 on both sides of the dummy gate layer, forming an interlayer dielectric layer (not shown) covering the source-drain doped layers, and removing the dummy gate layer after the interlayer dielectric layer is formed to form a gate opening (not shown).

The dummy gate layer is used to define the location of the formed gate layer 560. The material of the dummy gate layer may include one or more of polysilicon, amorphous silicon, or amorphous carbon.

The grid side wall and the pseudo grid layer are used for defining the forming position of the source-drain doped layer, and the grid side wall is also used for protecting the side walls of the pseudo grid layer and the grid layer. The grid side wall can be of a single-layer structure or a laminated structure, and the material of the grid side wall comprises one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride oxide, silicon oxynitride, boron nitride and boron carbonitride.

The source-drain doped layer is used as a source region or a drain region of the formed transistor. Specifically, the material of the source-drain doped layer may include silicon germanium doped with P-type ions including B, ga or In, and the material of the source-drain doped layer may also include silicon or silicon carbide doped with N-type ions including P, as or Sb.

The interlayer dielectric layer is used for isolating adjacent devices. Specifically, the material of the interlayer dielectric layer comprises one or more of silicon oxide, silicon nitride, silicon carbide nitride, silicon boride nitride, silicon oxycarbide nitride and silicon oxynitride.

Accordingly, in the present embodiment, in the step of forming the gate layer 560, the gate layer 560 is formed in the gate opening.

Note that the semiconductor structure may be formed by using the forming method described in the foregoing embodiment, or may be formed by using other forming methods. For a specific description of the semiconductor structure in this embodiment, reference may be made to the corresponding description in the foregoing embodiment, which is not repeated here.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims (17)

1.A semiconductor structure, comprising:

A substrate comprising a first region and a second region, the first region having a device operating voltage less than the second region;

the fin part is separated from the substrate of the first region and the second region;

The isolation layer is positioned on the substrate and surrounds part of the side wall of the fin part, the fin part exposed by the isolation layer is used as an effective fin part, and the effective fin part height of the first region is larger than that of the second region;

The first gate dielectric layer is positioned on the effective fin part of the second region;

The second gate dielectric layer is positioned on the effective fin part of the first region, and the thickness of the second gate dielectric layer is smaller than that of the first gate dielectric layer;

and the grid electrode layer stretches across the effective fin part and covers the first grid dielectric layer and the second grid dielectric layer, and the grid electrode layer covers part of the top and part of the side wall of the effective fin part.

2. The semiconductor structure of claim 1, wherein a thickness of the spacer layer of the first region is less than a thickness of the spacer layer of the second region along a direction normal to the top surface of the substrate.

3. The semiconductor structure of claim 1 or 2, wherein a difference in height between the effective fin of the first region and the effective fin of the second region along a direction normal to the top surface of the substrate is 50 to 200 a.

4. The semiconductor structure of claim 1 or 2, wherein an aspect ratio of a space surrounded by the first gate dielectric layer and the isolation layer between adjacent active fins of the second region is less than 1.5:1.

5. The semiconductor structure of claim 1 or 2, wherein the gate layer comprises one or more work function layers.

6. A method of forming a semiconductor structure, comprising:

Providing a substrate, wherein the substrate comprises a first region and a second region, the working voltage of a device in the first region is smaller than that of a device in the second region, and fins which are mutually separated are formed on the substrates in the first region and the second region;

Forming an isolation layer surrounding the fin portion on a substrate at the side of the fin portion, wherein the fin portion exposed by the isolation layer serves as an effective fin portion, and the effective fin portion of the first region is higher than that of the second region;

forming a first gate dielectric layer on the effective fin part of the second region;

Forming a second gate dielectric layer on the effective fin part of the first region, wherein the thickness of the second gate dielectric layer is smaller than that of the first gate dielectric layer;

And forming a gate layer crossing the effective fin part on the first gate dielectric layer and the second gate dielectric layer, wherein the gate layer covers part of the top and part of the side wall of the effective fin part.

7. The method of forming a semiconductor structure of claim 6, wherein the step of forming the isolation layer comprises:

Forming an isolation material layer surrounding the fin portion on the substrate at the side of the fin portion, wherein the isolation material layer covers the top and the side wall of the fin portion;

Removing the isolation material layer with the first part thickness of the second region to form an effective fin part in the second region;

removing the isolation material layer with the second part thickness of the first region to form an effective fin part in the first region, wherein the second part thickness is larger than the first part thickness;

And removing the isolation material layer with the first part thickness of the second region, and removing the isolation material layer with the second part thickness of the first region, wherein the rest isolation material layer is used as an isolation layer.

8. The method of forming a semiconductor structure of claim 7, wherein removing the second partial thickness of the isolation material layer of the first region comprises:

removing the isolation material layer of the first partial thickness of the second region and the first region in the step of removing the isolation material layer of the first partial thickness of the second region;

and removing the isolation material layer with the first part thickness, and removing the isolation material layer with the third part thickness of the first region, wherein the sum of the first part thickness and the third part thickness is the second part thickness.

9. The method of forming a semiconductor structure of claim 8, wherein after removing the second region and the first portion of the thickness of the isolation material layer, a first mask layer is formed over the second region of the isolation material layer before removing the third portion of the thickness of the isolation material layer;

The first mask layer is used for protecting the isolation material layer of the second region in the process of removing the isolation material layer of the third part of the thickness of the first region;

and removing the first mask layer after the isolation layer is formed.

10. The method of forming a semiconductor structure of claim 9, wherein forming the first gate dielectric layer comprises:

Forming an initial first gate dielectric layer on the effective fin part of the first region and the effective fin part of the second region;

Forming a second mask layer on the initial first gate dielectric layer of the second region, wherein the second mask layer and the first mask layer are formed through the same photomask;

removing an initial first gate dielectric layer of the first region, wherein the rest initial first gate dielectric layer is used as a first gate dielectric layer;

and removing the second mask layer after the first gate dielectric layer is formed.

11. The method of forming a semiconductor structure of claim 9, wherein the process of forming the first mask layer comprises a spin-on process, an exposure process, and a development process.

12. The method of forming a semiconductor structure of claim 9, wherein in the step of forming the first mask layer, the material of the first mask layer comprises photoresist.

13. The method of forming a semiconductor structure of claim 9, wherein the process of removing the first mask layer comprises one or both of a dry etching process and a wet cleaning process.

14. The method of forming a semiconductor structure of claim 13, wherein the process of removing the third partial thickness of the isolation material layer of the first region comprises a dry etching process.

15. The method of claim 6, wherein in the step of forming a first gate dielectric layer on the effective fin portion of the second region, a first groove surrounded by the first gate dielectric layer and the isolation layer is formed between the effective fin portions of adjacent second regions, and a ratio of a depth to a width of the first groove is less than 1.5:1.

16. The method of claim 6, wherein in the step of forming the isolation layer, a difference in height between the effective fin of the first region and the effective fin of the second region along a normal direction of the top surface of the substrate is 50 to 200 a.

17. The method of forming a semiconductor structure of claim 6, wherein in the step of forming the gate layer, the gate layer comprises one or more work function layers.