CN120508517A - Single-line bidirectional communication method, system and computer-readable storage medium - Google Patents

Abstract

The invention relates to a single-wire bidirectional communication method, a system and a computer readable storage medium, which comprises a first chip and a second chip, wherein the first chip and the second chip are used for carrying out communication in a single-wire half-duplex mode, the first chip and the second chip are switched between a bus transmission state and a bus receiving state, the method comprises the following steps that the chip in the bus transmission state is configured to transmit serial data, the chip in the bus receiving state is configured to detect and receive the serial data, when the chip in the bus receiving state has the serial data which is not transmitted, a read-write switching instruction is transmitted, the chip in the bus transmission state is switched into the bus transmission state and is used for transmitting the serial data which is not transmitted, the chip in the bus transmission state is used for receiving the serial data which is transmitted, and the information delay of the single-wire bidirectional communication is reduced by constructing non-master-slave communication.

Description

Single-wire two-way communication method, system and computer readable storage medium

Technical Field

The present invention relates to the field of serial port communications technologies, and in particular, to a single-wire bidirectional communication method, a system, and a computer readable storage medium.

Background

In the embedded field, serial data communication between micro control chips generally uses asynchronous serial ports, parallel ports, CAN and RS485 to perform serial data interaction. Single-wire half-duplex communication allows signals to be transmitted in two directions, but only allows signals to be transmitted unidirectionally on a channel at a time, thereby greatly reducing the complexity of wiring. The existing single-wire half-duplex communication generally adopts a master-slave communication mode, a transmitter and a receiver are divided into a master machine and a slave machine, the master machine is connected with the slave machine through a bus, and in order to avoid bus competition between the master machine and the slave machine, the working state of the slave machine is controlled by the master machine. Therefore, when receiving the serial data of the host, the slave is in a serial data receiving state, if important information needs to be fed back, the micro control chip serving as the slave needs to wait for the host to send the serial data and then send the serial data, so that the important information of the slave cannot be fed back at the first time.

Accordingly, the prior art is still in need of improvement and development.

Disclosure of Invention

In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a single-wire two-way communication method, system and computer readable storage medium, which adopts non-master-slave communication to solve the problem that the prior art cannot freely communicate with a master-slave communication mode with a micro control chip as a slave.

The technical scheme of the invention is as follows:

a single wire bi-directional communication method for a first chip and a second chip that communicate in a single wire half duplex manner, the first chip and the second chip transitioning between a bus transmit state and a bus receive state, comprising the steps of:

Configuring the chip in a bus transmitting state to transmit serial data, and configuring the chip in a bus receiving state to detect and receive the serial data;

When the chip in the bus receiving state has the serial data which is not transmitted, the chip in the bus receiving state transmits a read-write conversion instruction and converts the read-write conversion instruction into a bus transmitting state for transmitting the serial data;

When the chip in the bus transmitting state detects a read-write conversion instruction transmitted by the chip in the bus receiving state, the chip in the bus transmitting state stores the unsent serial data and converts the unsent serial data into the bus receiving state for receiving the transmitted serial data.

The further arrangement of the present invention, the chip in the bus transmitting state is configured to transmit serial data, and the chip in the bus receiving state is configured to detect and receive serial data, includes:

Storing read-write conversion instructions in the first chip and the second chip in advance;

The first chip is configured as a chip in a bus sending state, and the second chip is configured as a chip in a bus receiving state, or the first chip is configured as a chip in a bus receiving state, and the second chip is preset as a chip in a bus sending state;

and carrying out power-on initialization processing on the chip preset in the bus sending state and the chip preset in the bus receiving state.

The invention further provides that the power-on initialization processing for the chip preset in the bus sending state and the chip preset in the bus receiving state comprises the following steps:

Controlling a chip preset in a bus transmission state to be electrified and started, so that the chip preset in the bus transmission state enters a serial data transmission state;

controlling the chip preset in the bus sending state to send a wake-up signal to the chip preset in the bus receiving state;

the chip preset in the bus receiving state leaves the low power consumption state according to the received wake-up signal, enters the serial data receiving state and waits for receiving serial data.

According to the invention, the chip in the bus sending state and the chip in the bus receiving state are subjected to clock synchronization at the start bit of the serial data.

In a further arrangement of the present invention, the read-write conversion instruction is a low level of three bytes.

According to the further arrangement of the invention, the chip preset in the bus receiving state wakes up at a low level.

In a further arrangement of the present invention, when the chip in the bus transmitting state detects a read-write conversion instruction transmitted by the chip in the bus receiving state, the chip in the bus transmitting state stores the serial data that is not transmitted and converts the serial data into the bus receiving state, and then the method further includes:

the receiving end of the chip in the bus sending state detects the serial data and checks the serial data of the current frame;

When the serial data check result is true, the bus transmission state takes the serial data of the next frame as the non-transmitted serial data;

when the serial data check result is false, the chip in the bus receiving state discards the serial data, and the chip in the bus transmitting state takes the serial data of the current frame as the serial data of the next frame.

Based on the same inventive concept, the invention also discloses a single-wire bidirectional communication system, which comprises a first chip, a second chip and a first resistor, wherein the first chip comprises a first transmitting end and a first receiving end, the second chip comprises a second transmitting end and a second receiving end, the second transmitting end of the second chip is connected with the second receiving end of the second chip, the first receiving end of the first chip is connected with the second transmitting end of the second chip through a serial bus, the first transmitting end of the first chip is connected with the first receiving end of the first chip, the second receiving end of the second chip is connected with the second transmitting end of the second chip, one end of the first resistor is connected with a common connecting end of the first transmitting end of the first chip and the second transmitting end of the second chip, and the other end of the first resistor is connected with a power supply voltage.

The invention further provides that the serial bus is one of an RS485 bus, a CAN bus and a UART bus.

Based on the same inventive concept, the invention also discloses a computer readable storage medium, on which a computer program is stored, which when being executed by a processor, implements the single-wire two-way communication method as described above.

The invention discloses a single-wire bidirectional communication method, a system and a computer readable storage medium, in particular to a single-wire bidirectional communication method, which is used for a first chip and a second chip which are communicated in a single-wire half-duplex mode, wherein the first chip and the second chip are switched between a bus sending state and a bus receiving state; when the chip in the bus receiving state detects the read-write conversion instruction sent by the chip in the bus receiving state, the chip in the bus sending state saves the unsent serial data and converts the unsent serial data into the bus receiving state for receiving the sent serial data. The chip for carrying out single-wire bidirectional communication in the invention can be converted between a bus sending state and a bus receiving state through the read-write conversion instruction, so as to construct non-master-slave communication. When any party is in the bus receiving state, the serial data transmission of the chip in the bus transmitting state can be interrupted by transmitting the read-write conversion instruction, and the serial data can be converted into the bus transmitting state to transmit the serial data without waiting for the completion of the chip in the bus transmitting state at the current moment. The important information of both parties can be sent outwards at the first time, and the information delay of single-wire two-way communication is reduced.

Drawings

In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the following description will briefly explain the drawings used in the embodiments or the description of the prior art, and it is obvious that the drawings in the following description are only some embodiments of the invention, and that other drawings can be obtained from the structures shown in these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a flow chart of a single-wire two-way communication method in accordance with a preferred embodiment of the present invention.

Fig. 2 is a flow chart of a single wire bi-directional communication method in accordance with a preferred embodiment of the present invention.

FIG. 3 is a schematic diagram of the workflow of a chip in accordance with a preferred embodiment of the present invention.

Fig. 4 is a schematic diagram of a single-wire two-way communication system according to a partially preferred embodiment of the present invention.

Detailed Description

The invention provides a single-wire two-way communication method, a system and a computer readable storage medium, which are used for making the purposes, technical schemes and effects of the invention clearer and more specific, and the invention is further described in detail below by referring to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.

In the description and claims, unless the context specifically defines the terms "a," "an," "the," and "the" include plural referents. If there is a description of "first", "second", etc. in an embodiment of the present invention, the description of "first", "second", etc. is for descriptive purposes only and is not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature.

It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may also be present. Further, "connected" or "coupled" as used herein may include wirelessly connected or wirelessly coupled. The term "and/or" as used herein includes all or any element and all combination of one or more of the associated listed items.

It will be understood by those skilled in the art that all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs unless defined otherwise. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the prior art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

In addition, the technical solutions of the embodiments may be combined with each other, but it is necessary to base that the technical solutions can be realized by those skilled in the art, and when the technical solutions are contradictory or cannot be realized, the combination of the technical solutions should be considered to be absent and not within the scope of protection claimed in the present invention.

The inventor researches and discovers that the existing single-bus communication only uses one serial bus to realize the integration of receiving and transmitting serial data, has the advantages of reducing one line, obviously reducing hardware cost, saving wiring space of a PCB design and the occupied pin number of a micro control chip, and has particular advantages for large-scale equipment deployment or products sensitive to cost. However, at the same time, because the conventional serial communication protocol is designed based on two lines, and the master and slave machines share one line in single bus communication, when the master machine and the slave machine wake up from a sleep state and send serial data to each other at the same time, the serial bus can only be in a level state at one moment, so that a competition relationship is generated between the master machine and the slave machine. In this case, since there is only one communication line, serial data transmitted from both parties interfere with each other on the bus, so that the master-slave machine may not correctly recognize serial data transmitted from the other party, resulting in communication failure. Therefore, the single-wire bidirectional communication method generally adopts a master-slave communication mode, controls and manages the serial data communication state of the slave through the host, and if important information needs to be fed back, the host as a micro-control chip of the slave needs to send serial data and then sends the serial data, so that the important information of the slave cannot be fed back for the first time. And meanwhile, as the device serving as a host and the device serving as a slave are fixed in the master-slave communication mode, serial data exchange must be initiated by the device serving as the host, so that a certain synchronization delay exists in serial data serving as a micro control chip or device of the slave.

Based on the above-mentioned problems in the prior art, please refer to fig. 1 to 3, the present invention provides a part of preferred embodiments of a single-wire bidirectional communication method.

In some preferred embodiments, as shown in fig. 1, the present invention provides a single-wire bidirectional communication method for a first chip and a second chip that communicate in a single-wire half duplex manner, the first chip and the second chip being switched between a bus transmission state and a bus reception state, comprising the steps of:

S100, configuring a chip in a bus transmitting state to transmit serial data, and configuring a chip in a bus receiving state to detect and receive the serial data;

Specifically, referring to fig. 1, since the first chip and the second chip communicate in a single-wire half duplex manner, only one of the first chip and the second chip is in a bus transmitting state at the same time, the other chip is in a bus receiving state, the chip in the bus receiving state is used for receiving serial data transmitted by the chip in the bus transmitting state, and the chip in the bus transmitting state transmits the serial data. The bus sending state and the bus receiving state are chip modes set in advance through software burning, namely when the chip is in the bus sending state, serial data on an internal sending array of the chip are read, and corresponding high level and low level are sent outwards according to frames in sequence. When the chip is in the bus receiving state, the chip receives serial data and sequentially stores the serial data into the array. One frame of data may be split into a predetermined number of byte-length serial data, and preferably, one frame of data is composed of at least three byte-length serial data.

S200, when the chip in the bus receiving state has the serial data which is not transmitted, the chip in the bus receiving state transmits a read-write conversion instruction and converts the read-write conversion instruction into a bus transmitting state for transmitting the serial data;

specifically, when the chip in the bus reception state transmits a read/write conversion instruction, the chip originally in the bus reception state is converted into the chip in the bus transmission state. The read-write conversion instruction is an instruction signal with a predetermined byte length, and illustratively, the read-write conversion instruction is a low level 0x00 of three bytes, or may be a low level of other byte lengths, or a level sequence formed by any high and low levels, which is not described herein.

And S300, when the chip in the bus transmitting state detects a read-write conversion instruction transmitted by the chip in the bus receiving state, the chip in the bus transmitting state stores the unsent serial data and converts the unsent serial data into the bus receiving state for receiving the transmitted serial data.

Specifically, when the chip in the bus transmitting state detects the read-write switching instruction, the chip in the bus transmitting state is converted into the chip in the bus receiving state. The chip receiving end in the bus sending state and the chip receiving end in the bus receiving state at the current moment both receive the read-write conversion instruction, so that the communication modes of the first chip and the second chip are converted at the same time. After the conversion is completed, the process returns to step S100, where the chip that was in the bus transmission state is already converted to the bus reception state at the current time, and starts to transmit serial data at the next frame. At this time, if the chip in the bus receiving state has the serial data which is not transmitted, the chip in the bus receiving state will transmit the read-write switching instruction, apply for the control right of the serial bus, if the read-write switching instruction is not detected before the serial data is transmitted, the chip in the bus transmitting state at the current moment can continue to transmit the serial data until the transmission of the serial data is completed, or the chip in the bus receiving state transmits the read-write switching instruction due to the fact that the chip has the serial data which is not transmitted. The unsent serial data may be new serial data that needs to be subjected to single-wire half duplex communication, or serial data that is not transmitted by a chip in a bus receiving state when the chip is in a bus sending state. Therefore, the first chip and the second chip can be freely switched between the bus sending state and the bus receiving state through the read-write switching instruction, and the signal transmission delay is reduced.

Further, referring to fig. 2, the configuring the chip in the bus transmitting state to transmit serial data and the configuring the chip in the bus receiving state to detect and receive serial data includes:

S110, storing read-write conversion instructions in the first chip and the second chip in advance;

S120, configuring the first chip as a chip in a bus sending state and configuring the second chip as a chip in a bus receiving state, or configuring the first chip as a chip in a bus receiving state, wherein the second chip is preset as a chip in a bus sending state;

specifically, by default setting, the system is ensured to have definite serial bus control authority attribution when being started, and the competition problem caused by uncertain identity is avoided. For example, a default communication state during startup may be indicated in advance by setting a specific flag bit in a software code of the first chip or the second chip, so as to ensure that only one chip is in a bus transmission state at the same time.

S130, carrying out power-on initialization processing on a chip preset in a bus sending state and a chip preset in a bus receiving state.

Further, the power-on initialization processing for the chip preset in the bus transmitting state and the chip preset in the bus receiving state includes:

S131, controlling a chip preset in a bus transmission state to be electrified and started, so that the chip preset in the bus transmission state enters a serial data transmission state;

referring to fig. 2, the chip preset in the bus transmission state is powered on, or the chip in the bus transmission state receives the serial data which is not transmitted and enters the bus transmission state, and the transmitting array and the receiving array of the chip preset in the bus transmission state are initialized.

S132, controlling the chip preset in the bus sending state to send a wake-up signal to the chip preset in the bus receiving state;

specifically, the wake-up signal is used for waking up the chip preset in the bus receiving state, and the wake-up signal may be selected from an ignition signal wake-up, a CAN bus wake-up, a time sequence wake-up, a timer period wake-up, or a rising edge and a falling edge of a serial data level signal trigger wake-up. Illustratively, each time a communication is started, the chip in the bus transmission state transmits a low level signal indicating the start of transmission of serial data, and since the bus is set to a high level when it is idle, a level signal significantly different from the idle state is transmitted when the communication is started. And waking up a chip preset to be in a bus receiving state, and simultaneously, the first chip and the second chip can perform clock synchronization through signals of the start bit.

S133, the chip preset in the bus receiving state leaves the low-power consumption state according to the receiving wake-up signal, enters the serial data receiving state and waits for receiving serial data.

Specifically, the serial data specifies that the start bit is low, that the stop bit and the idle bit are both high, and that the serial data includes 8 serial data bits. The chip in the bus transmit state and the chip in the bus receive state are clocked at the start bit of the serial data by the falling edge at the start bit marking the start of one byte transmission. It should be noted that the serial data provision and clock synchronization settings are merely exemplary and should not be construed as limiting the scope of the invention in any way. The serial data may be formatted as desired by one skilled in the art to other formats to meet different communication protocols without departing from the inventive principles of this patent disclosure.

In a further implementation manner of the preferred embodiment of the present invention, when the chip in the bus transmission state detects a read-write conversion instruction sent by the chip in the bus reception state, the chip in the bus transmission state stores the unsent serial data and converts the unsent serial data into the bus reception state, and the method further includes:

s400, acquiring serial data, wherein the chip in a bus transmission state processes the acquired serial data and verifies the acquired serial data;

S500, according to the checking result, the chip in the bus transmitting state transmits serial data, and when the checking result of the serial data is true, the chip in the bus transmitting state transmits the serial data of the next frame determined in advance;

S600, when the serial data checking result is false, the chip in the bus receiving state discards the serial data, and the chip in the bus transmitting state takes the serial data of the current frame as the serial data of the next frame.

Specifically, since the serial bus is used, the chip itself in the bus transmission state can read the serial data transmitted on the bus when transmitting the serial data. By comparing the transmitted serial data with the received serial data, it can be judged whether the serial data is transmitted successfully. And the chip in the bus transmitting state can judge whether the serial data is in transmission error caused by interference by checking the read serial data, and when the serial data checking result is true, the chip in the bus transmitting state can continuously transmit the serial data of the next frame in the array. When the serial data check result is false, the system is proved to generate unpredictable influence interference to the signal due to internal or external factors, and the serial data of the current frame is not successfully transmitted, the chip in the bus transmission state takes the serial data of the current frame as the serial data of the next frame and retransmits the serial data of the current frame in the next frame.

Referring to fig. 2 and 3, since the existing serial communication protocol needs two lines to realize the transceiving integration, the existing serial communication protocol uses one line to realize the transceiving integration of the dual-chip serial data transmission, so that a competition relationship is generated, and when the chip in the bus transmitting state and the chip in the bus receiving state leave the sleep state and simultaneously transmit serial data, only one serial bus is used as the communication line, serial information to be transmitted cannot be mutually identified due to competition. Therefore, any one of the first chip or the second chip sends out a read-write conversion instruction at any time, and the chip can acquire the control bus use right and can be used as a chip in a bus sending state to send serial data. When the first chip or the second chip is in the bus transmitting state, the transmitting end transmits serial data to the serial bus according to frames, one frame of the serial data at least comprises three bytes, when the serial data needs to be transmitted, the transmitting end of the chip in the bus receiving state at the current moment pulls down the level, and the chip in the bus receiving state pulls down the low level with the length of three bytes, namely, the transmitting 0X00,0X00,0X00 pulls down the serial bus, no matter what serial data transmission state the first chip or the second chip is in, the low level can be identified, so that the chip in the bus transmitting state in the two chips gives up bus control rights, and the chip in the bus receiving state uses the serial bus as the chip in the bus transmitting state from the next frame of serial data.

Further, the first chip and the second chip are both provided with a transmitting serial data and a receiving array, the transmitting serial data is used for storing serial data to be transmitted by the transmitting end of the corresponding chip, and the receiving array is used for storing serial data received by the receiving end of the corresponding chip. In the software design, after power-on or dormancy awakening, a chip with a preset bus sending state and a sending array and a receiving array inside the chip with a preset bus receiving state are initialized. When the chip in the bus transmitting state needs to transmit serial data, the serial data of the next frame to be transmitted is put into a transmitting array, and the serial data is transmitted to the serial bus through a transmitting end. In the transmitting process, the chip in the bus transmitting state can simultaneously receive the level change of the serial signal on the bus and store the received serial data into a receiving array of the chip. After the transmission is completed, the serial data in the transmitting array is compared with the serial data in the receiving array. If the two are consistent, the serial data transmission is successful, and if the two are inconsistent, the transmission failure may be caused by the fact that the chip in the bus receiving state applies for the bus or other interference. For example, when a chip in a bus receiving state applies for a bus by sending a read-write conversion instruction, the serial bus will be pulled down by a low level in the read-write conversion instruction, so that serial data sent by the chip in the bus sending state is inconsistent with received serial data. And initializing the transmission arrays of the first chip and the second chip to 0XFF, and waiting for the transmission of the serial data of the next frame. And furthermore, no matter the preset state of the first chip and the second chip when the first chip and the second chip are powered on, in the single-wire bidirectional communication process, the serial data communication can be carried out by who applies for the bus control right as the chip in the serial transmission state.

In some preferred embodiments, as shown in fig. 4, based on the same inventive concept, the present invention further discloses a single-wire bidirectional communication system, which is configured to implement the single-wire bidirectional communication method described above, and the single-wire bidirectional communication system includes a first chip U1, a second chip U2, and a first resistor R1, where the first chip U1 includes a first transmitting end and a first receiving end, the second chip U2 includes a second transmitting end and a second receiving end, the first receiving end of the first chip U1 is connected to the second transmitting end of the second chip U2 through a serial bus, the first transmitting end of the first chip U1 is connected to the first receiving end of the first chip U1, the second receiving end of the second chip U2 is connected to the second transmitting end of the second chip U2, one end of the first resistor R1 is connected to a common terminal of the first transmitting end of the first chip U1 and the second transmitting end of the second chip U2, and the other end of the first resistor R1 is connected to a power supply voltage.

Specifically, the single-wire bidirectional communication system may further include a first capacitor C1 and a second capacitor C2, one end of the first capacitor C1 is connected to the first receiving end of the first chip, and the other end of the first capacitor C1 is grounded. One end of the second capacitor C2 is connected with a second receiving end of the second chip, the other end of the second capacitor C2 is grounded, and the first capacitor C1 and the second capacitor C2 are accommodated in 1nF and are used for achieving filtering decoupling. The serial bus is one of an RS485 bus, a CAN bus and a UART bus, and the first chip U1 and the second chip U2 CAN adopt micro-control chips with the model number of SC8F093AD 7. The resistance value of the first resistor R1 is 20kΩ, and is used for pulling up the voltage at the serial bus, so that the first receiving end of the first chip U1, the first transmitting end of the first chip U1, the second receiving end of the second chip U2, and the second transmitting end of the second chip U2 and the serial bus keep high level at the moment when no serial data is transmitted after the serial bus is powered on. The time without serial data transmission at least includes that the chip in the bus receiving state does not have the serial data of the next frame to be received and the chip in the bus receiving state is in a low power consumption state. When the chip in the bus transmitting state transmits serial data, the level on the serial bus jumps to wake up the chip in the low power consumption state. Therefore, when serial data transmission exists, the voltage at the serial bus is pulled up or pulled down by the jump level at the output pin of the chip in the bus transmitting state, and the specific serial data output condition of the chip in the bus transmitting state at the current moment can be known no matter which chip of the first chip U1 and the second chip U2 is used for serial data transmission, and the first chip U1 can acquire the specific serial data output condition of the chip in the bus transmitting state at the current moment through the first receiving end of the first chip U1 and the second chip U2 through the second receiving end of the second chip U2.

Meanwhile, when the chip in the bus receiving state applies for the bus control right, a low level with a predetermined byte length is sent to serve as a read-write conversion instruction, and at the moment, the serial bus is pulled down by the chip in the bus receiving state by the corresponding byte length and is received by the receiving end of the chip in the bus sending state at the current moment no matter the serial data content output by the chip in the bus sending state. The chip in the bus transmitting state can compare the serial data received at the receiving end with the serial data transmitted by the chip, and the chip in the bus transmitting state can judge that the chip in the bus receiving state is applying for bus control because the chip in the bus transmitting state can not transmit low levels with continuous lengths of a plurality of bytes under normal conditions and only can appear when the chip in the bus receiving state transmits a read-write conversion instruction, so that if the chip in the bus transmitting state receives low levels of a plurality of bytes and the transmitted serial data does not have low levels with corresponding lengths of bytes. When any one of the first chip or the second chip is in a bus transmission state, the serial data on the internal transmission array of the chip is read, and corresponding high level and low level are sequentially transmitted outwards according to frames. When the chip is in the bus receiving state, the chip receives serial data and sequentially stores the serial data into the array. Because the transmitting end and the receiving end of the first chip and the second chip are connected with the serial bus, no matter the corresponding chips are in a bus transmitting state or a bus receiving state, the first receiving end and the second receiving end of the first chip keep receiving serial data in a bus serial port, whether the serial data of the current frame contain a read-write switching instruction or not is detected in real time, and only the chips in the bus transmitting state judge whether the serial data of the receiving end of the current frame chip is required to be stored in an array or not.

Fig. 3 is a schematic workflow diagram of the first chip U1 or the second chip U2 when the single-wire bidirectional communication method is used for communication, and by way of example, the power-on default of the first chip U1 is set to be in a bus transmission state, and the power-on default of the second chip U2 is set to be in a bus reception state, and specifically, the working state of the single-wire bidirectional communication system is as follows:

1. After power-on, when the first chip U1 in the bus transmitting state transmits serial data, the second chip U2 in the bus receiving state does not transmit serial data, because the communication port is provided with the first resistor R1 for external pull-up, the serial bus keeps high level, the communication port of the first chip U1 in the bus transmitting state is pulled down due to the standard serial port protocol, the second chip U2 in the bus receiving state detects that the falling edge wakes up and waits for receiving the serial data, and the first chip U1 in the bus transmitting state transmits a frame of serial data to the second chip U2 in the bus receiving state.

2. After power-on, the first chip U1 in the bus sending state does not send serial data to the second chip U2 in the bus sending state, namely the second chip U2 in the bus receiving state sends a read-write switching instruction, and the read-write switching instruction is in a low level of three bytes, so that a receiving end of the first chip U1 in the bus sending state receives the read-write switching instruction, the first chip U1 is converted into a read-write receiving state, the second chip U2 applies for the use right of the serial bus, and the second chip U2 in the bus sending state waits for and receives one frame of serial data sent by the first chip U1 in the bus receiving state.

3. When the first chip U1 in the bus transmitting state transmits serial data, the second chip U2 in the bus receiving state also needs to preempt the bus to transmit serial data, namely, when the first chip U1 in the bus transmitting state transmits serial data, the second chip U2 in the bus receiving state transmits a read-write switching instruction in the current frame, the receiving end of the first chip U1 recognizes that the serial data of the current frame comprises the read-write switching instruction, gives out the bus control right, saves the serial data which is not transmitted successfully at the moment, reserves the first chip U1 which is transmitted once and is converted into the first chip U1 in the bus receiving state, and waits for the second chip U2 in the next frame to transmit the serial data. When the second chip U2 in the bus transmitting state finishes transmitting or the first chip U1 in the bus receiving state has unsent data, the first chip U1 transmits a read-write switching instruction, becomes a chip in the bus transmitting state again and resends the serial data which is not transmitted successfully.

4. When the second chip U2 sends serial data, the first chip U1 in the bus receiving state also needs to preempt the bus to send the serial data, when the second chip U2 is sending the serial data, the first sending end of the first chip U1 sends a read-write switching instruction, the second receiving end of the second chip U2 in the bus sending state recognizes the read-write switching instruction, gives out the bus control right, saves the serial data which is not sent successfully at the time, leaves one time for sending, and waits for the first chip U1 in the bus sending state to send the serial data. The first chip U1 in the bus transmitting state finishes transmitting, or the second chip U2 in the bus receiving state has unsent data, and the second chip U2 in the bus receiving state transmits a read-write switching instruction and transmits serial data which is not transmitted successfully.

Based on the same inventive concept, the invention also discloses a computer-readable storage medium, on which a computer program is stored, which computer program, when being executed by a processor, implements a method as described above.

In the above embodiments, it may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loaded and executed on a computer, produces a flow or function in accordance with embodiments of the present application, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer instructions may be stored in or transmitted across a computer-readable storage medium. The computer instructions may be transmitted from one website, computer, server, or serial data center to another website, computer, server, or serial data center by a wired (e.g., coaxial cable, fiber optic, digital subscriber line (digital subscriber line, DSL)) or wireless (e.g., infrared, wireless, microwave, etc.). The computer readable storage medium may be any available medium that can be accessed by a computer or a serial data storage device including one or more servers, serial data centers, etc. integrated with the available medium. The usable medium may be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., digital versatile disk (DIGITAL VERSATILE DISC, DVD)), or a semiconductor medium (e.g., solid State Disk (SSD)), etc.

The invention discloses a single-wire bidirectional communication method, a system and a computer readable storage medium, in particular to a single-wire bidirectional communication method. When any party is in the bus receiving state, the serial data transmission of the chip in the bus transmitting state can be interrupted by transmitting the read-write conversion instruction, and the serial data can be converted into the bus transmitting state to transmit the serial data without waiting for the completion of the chip in the bus transmitting state at the current moment. The important information of both parties can be sent outwards at the first time, and the information delay of single-wire two-way communication is reduced. Meanwhile, the roles of a plurality of micro control chips in single-wire bidirectional communication can be flexibly set according to actual requirements, different application scenes are adapted, stable and efficient single-bus communication can be realized, and an economic and practical solution is provided for the field of electronic communication.

It is to be understood that the invention is not limited in its application to the examples described above, but is capable of modification and variation in light of the above teachings by those skilled in the art, and that all such modifications and variations are intended to be included within the scope of the appended claims.

Claims (10)

1. A single-wire two-way communication method for a first chip and a second chip that communicate in a single-wire half-duplex manner, the first chip and the second chip being switched between a bus transmission state and a bus reception state, the method comprising the steps of:

Configuring a chip in a bus transmitting state to transmit serial data, and configuring a chip in a bus receiving state to detect and receive serial data;

When the chip in the bus receiving state has the unsent serial data, the chip in the bus receiving state sends a read-write conversion instruction and converts the read-write conversion instruction into a bus sending state for sending the unsent serial data;

When the chip in the bus transmitting state detects a read-write conversion instruction transmitted by the chip in the bus receiving state, the chip in the bus transmitting state stores the unsent serial data and converts the unsent serial data into the bus receiving state for receiving the transmitted serial data.

2. The single-wire bidirectional communication method according to claim 1, wherein the configuring the chip in the bus transmission state to transmit serial data and the configuring the chip in the bus reception state to detect and receive serial data includes:

Storing read-write conversion instructions in the first chip and the second chip in advance;

The first chip is configured as a chip in a bus sending state, and the second chip is configured as a chip in a bus receiving state, or the first chip is configured as a chip in a bus receiving state, and the second chip is preset as a chip in a bus sending state;

and carrying out power-on initialization processing on the chip preset in the bus sending state and the chip preset in the bus receiving state.

3. The single-wire bidirectional communication method according to claim 2, wherein the power-on initialization processing for the chip preset in the bus transmission state and the chip preset in the bus reception state includes:

Controlling a chip preset in a bus transmission state to be electrified and started, so that the chip preset in the bus transmission state enters a serial data transmission state;

controlling the chip preset in the bus sending state to send a wake-up signal to the chip preset in the bus receiving state;

the chip preset in the bus receiving state leaves the low power consumption state according to the received wake-up signal, enters the serial data receiving state and waits for receiving serial data.

4. The single wire bi-directional communication method of claim 1, wherein the chip in the bus transmission state and the chip in the bus reception state are clock-synchronized at a start bit of the serial data.

5. The single-wire bidirectional communication method according to claim 1, wherein the read-write switching instruction is a low level of three bytes.

6. The method of claim 3, wherein the chip preset to the bus reception state wakes up at a low level.

7. The single-wire bidirectional communication method according to claim 1, wherein when the chip in the bus transmission state detects a read-write conversion instruction transmitted by the chip in the bus reception state, the chip in the bus transmission state holds the non-transmitted serial data and converts the non-transmitted serial data into the bus reception state, and further comprising after receiving the transmitted serial data:

Acquiring serial data, wherein the chip in a bus transmission state processes the acquired serial data and verifies the acquired serial data;

When the serial data checking result is true, the chip in the bus sending state sends the serial data of the next frame determined in advance;

when the serial data check result is false, the chip in the bus receiving state discards the serial data, and the chip in the bus transmitting state takes the serial data of the current frame as the serial data of the next frame.

8. A single-wire bidirectional communication system for realizing the single-wire bidirectional communication method according to any one of claims 1 to 7, characterized in that the single-wire bidirectional communication system comprises a first chip, a second chip and a first resistor, the first chip comprises a first transmitting end and a first receiving end, the second chip comprises a second transmitting end and a second receiving end, the first receiving end of the first chip is connected with the second transmitting end of the second chip through a serial bus, the first transmitting end of the first chip is connected with the first receiving end of the first chip, the second receiving end of the second chip is connected with the second transmitting end of the second chip, one end of the first resistor is connected with a common connecting end of the first transmitting end of the first chip and the second transmitting end of the second chip, and the other end of the first resistor is connected with a power supply voltage.

9. The single wire bi-directional communication system of claim 8, wherein said serial bus is one of an RS485 bus, a CAN bus, a UART bus.

10. A computer readable storage medium, on which a computer program is stored, characterized in that the computer program, when being executed by a processor, implements the single-wire two-way communication method according to any one of claims 1-7.