CN120547932A - Semiconductor device structure, manufacturing method and electronic device - Google Patents
Semiconductor device structure, manufacturing method and electronic deviceInfo
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- CN120547932A CN120547932A CN202511051606.2A CN202511051606A CN120547932A CN 120547932 A CN120547932 A CN 120547932A CN 202511051606 A CN202511051606 A CN 202511051606A CN 120547932 A CN120547932 A CN 120547932A
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Abstract
The application relates to the technical field of semiconductors, and discloses a semiconductor device structure, a manufacturing method and an electronic device, wherein the semiconductor device structure comprises the following components: the semiconductor device comprises a substrate, a buffer layer, a channel layer, a barrier layer and a gate cap layer which are sequentially arranged on the substrate, wherein the gate cap layer comprises a first transistor structure and a second transistor structure, the semiconductor device structure further comprises a first transistor and a second transistor, a p-type doping element in the first transistor structure has a first concentration, a p-type doping element in the second transistor structure has a second concentration, and the first concentration is larger than the second concentration, so that the depletion degrees of electrons of the channel layers corresponding to different transistors are different, a plurality of transistors with different threshold voltages are formed on the same substrate, and the flexibility of the application of the semiconductor device structure is improved.
Description
Technical Field
The application relates to the technical field of semiconductors, and provides a semiconductor device structure, a manufacturing method and an electronic device.
Background
Gallium nitride is used as a material with large forbidden bandwidth, high critical breakdown electric field and high electron saturation speed, and can well meet the requirements of power electronic devices. In addition, the gallium nitride transistor also has high electron mobility, can form two-dimensional electron gas with high concentration and high carrier mobility at the interface of gallium nitride or gallium aluminum nitride, and can ensure the current capability of the device while considering the breakdown voltage of the device.
Currently, due to control of process uniformity, the threshold voltages of a plurality of gallium nitride transistors formed on a wafer are generally the same. However, there is a need for different threshold voltages for multiple gallium nitride transistors in a multi-device integration scenario. How to realize different threshold voltages of multiple transistors in a multi-device integration scenario is a problem to be solved in the art.
Disclosure of Invention
The embodiment of the application provides a semiconductor device structure, a manufacturing method and an electronic device, which are used for realizing different threshold voltages of a plurality of transistors in a multi-device integration scene.
The specific technical scheme provided by the application is as follows:
In a first aspect, an embodiment of the present application provides a semiconductor device structure, including:
a substrate;
the buffer layer, the channel layer, the barrier layer and the gate cap layer are sequentially arranged on the substrate, wherein the gate cap layer comprises a first transistor structure and a second transistor structure;
The semiconductor device structure further includes a first transistor and a second transistor;
The p-type doping element in the first transistor structure has a first concentration, and the p-type doping element in the second transistor structure has a second concentration, the first concentration being greater than the second concentration.
In a second aspect, an embodiment of the present application further provides a method for manufacturing the semiconductor device structure described in the first aspect, including:
forming a buffer layer, a channel layer, a barrier layer and a gate cap layer which are sequentially stacked on a substrate;
forming a first transistor structure over the barrier layer, the first transistor structure having a first concentration of a p-type dopant element therein;
a second transistor structure is formed over the barrier layer, the second transistor structure having a second concentration of the p-type dopant element, the first concentration being greater than the second concentration.
In a third aspect, an embodiment of the present application provides an electronic device, including a semiconductor device structure as described in the first aspect above.
The application has the following beneficial effects:
The semiconductor device structure comprises a substrate, a buffer layer, a channel layer, a barrier layer and a grid cap layer which are sequentially arranged on the substrate, wherein the grid cap layer comprises a first transistor structure and a second transistor structure, the first transistor and the second transistor are arranged in the semiconductor device structure, p-type doping elements in the first transistor structure have a first concentration, p-type doping elements in the second transistor structure have a second concentration, and the first concentration is larger than the second concentration, and therefore the first concentration of the p-type doping elements in the first transistor structure and the second concentration of the p-type doping elements in the second transistor structure are arranged differently, so that the depletion degrees of electrons of channel layers corresponding to different transistors are different, a plurality of transistors with different threshold voltages can be formed on the same substrate, and the application flexibility of the semiconductor device structure is improved.
Drawings
Fig. 1 is a cross-sectional view of a first semiconductor device structure according to an embodiment of the present application;
Fig. 2 is a cross-sectional view of a second semiconductor device structure according to an embodiment of the present application;
Fig. 3 is a cross-sectional view of a second semiconductor device structure according to an embodiment of the present application;
fig. 4 is a schematic flow chart of a method for manufacturing a semiconductor device structure according to an embodiment of the present application;
fig. 5 is a schematic process diagram of a method for fabricating a semiconductor device structure according to an embodiment of the present application;
fig. 6 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
Detailed Description
A semiconductor device structure, a method for manufacturing the same, and a specific implementation of an electronic device according to embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that the described embodiments are only some embodiments of the present invention, and not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The structural composition of the lower semiconductor device structure is first described with reference to the accompanying drawings.
An embodiment of the present application provides a semiconductor device structure, shown in fig. 1, comprising a substrate 100.
The substrate 100 may be silicon, silicon carbide, sapphire, or the like, and is not particularly limited herein.
Referring to fig. 1, the semiconductor device structure further includes a buffer layer 200, a channel layer 300, a barrier layer 400, and a gate cap layer sequentially disposed on the substrate 100, where the gate cap layer includes a first transistor structure 501 and a second transistor structure 502, i.e., the first transistor structure 501 and the second transistor structure 502 are disposed on a side of the barrier layer facing away from the channel layer.
The buffer layer 200, the channel layer 300, the barrier layer 400, and the gate cap layer are epitaxially implemented on the substrate 100, wherein the buffer layer 200 may include a multi-layer structure, and a layer far from the substrate 100 in the multi-layer structure is typically the channel layer 300.
It should be noted that, the forbidden bandwidth of the barrier layer 400 is greater than that of the channel layer 300, the barrier layer 400 and the channel layer 300 form a heterostructure, and two-dimensional electron gas is induced on the surface of the channel layer 300 on the side far away from the substrate 100, so that the on-resistance of the transistor can be further reduced, and the reliability of the semiconductor device structure can be improved.
The material and thickness of the gate cap layer also change parameters between the gate and the channel layer 300, so that the threshold voltage of the device can be adjusted, and the device can be ensured to be stably switched in a designed voltage range.
In addition, in the epitaxy process, lattice mismatch may occur in the materials of the substrate 100 and the buffer layer 200 inevitably, that is, stress may occur at the interface between the substrate 100 and the buffer layer 200, and when the stress exceeds a critical value, dislocation may occur between the substrate 100 and the buffer layer 200 to release the stress, and based on this, a first insertion layer, for example, aluminum nitride, may be disposed between the substrate 100 and the buffer layer 200, and the disposition of the first insertion layer effectively alleviates the lattice mismatch.
In addition, a polarization phenomenon may occur between the channel layer 300 and the barrier layer 400, and a second insertion layer may be disposed between the channel layer 300 and the barrier layer 400, for example, the second insertion layer may be made of aluminum nitride, and the second insertion layer may be disposed to effectively enhance the polarization effect, so that the concentration of the two-dimensional electron gas may be increased.
In order to form a plurality of transistors with different threshold voltages on the same substrate 100, referring to fig. 1, the gate cap layer includes a first transistor structure 501 and a second transistor structure 502.
As shown in fig. 1, the first transistor structure 501 and the second transistor structure 502 are independently disposed in the barrier layer 400, and the first transistor structure 501 and the second transistor structure 502 may be disposed adjacent to each other or may be disposed separately.
The semiconductor device structure further includes a first transistor 600 and a second transistor 600'.
Referring to fig. 1, the first transistor structure 501 and the second transistor structure 502 correspond to different transistors, and illustratively, the first transistor structure 501 is a component of the first transistor 600, and the second transistor structure 502 is a component of the second transistor 600'.
In addition to the first transistor structure 501, the first transistor 600 further includes a gate 603 stacked on the first transistor structure 501, and a source 601 and a drain 602 disposed on the barrier layer 400. Similarly, in addition to the second transistor structure 502, the second transistor 600 'includes a gate 603' stacked over the second transistor structure 502, and a source 601 'and a drain 602' over the barrier layer 400. The source electrode 601 'and the drain electrode 602' may also form an ohmic contact with the two-dimensional electron gas, thereby providing a basis for the unimpeded transport of carriers between the metal and the semiconductor.
It should be noted that the number of the first transistor structures 501 and the second transistor structures 502 may be plural on the same substrate 100, so that two transistors with different threshold voltages, i.e., plural first transistors 600 and plural second transistors 600', may be fabricated on the same substrate 100.
The p-type doping element in the first transistor structure 501 has a first concentration and the p-type doping element in the second transistor structure 502 has a second concentration, the first concentration being greater than the second concentration.
The first transistor structure 501 and the second transistor structure 502 are doped with a p-type doping element, which illustratively includes magnesium, zinc, beryllium, or carbon. Among them, magnesium is a widely used p-type doping element.
The first transistor structure 501 and the second transistor structure 502 described above further comprise gallium nitride.
The first transistor 600 and the second transistor 600' having different threshold voltages can be manufactured by two embodiments in the present application.
In the first embodiment, the p-type doping elements with different concentrations are doped in the first transistor structure 501 and the second transistor structure 502, so that the p-type doping element in the first transistor structure 501 has a first concentration, and the p-type doping element in the second transistor structure 502 has a second concentration, so that the depletion degrees of electrons of the channel layers corresponding to different transistors are different, and thus the threshold voltages of the first transistor 600 and the second transistor 600' are different.
In the implementation process, the first concentration is greater than 110 18cm-3, And a first concentration of less than or equal to 11020cm-3。
In the case of fabricating two transistors having different threshold voltages on the same substrate 100, in order to achieve the first concentration of the p-type doping element in the first transistor structure 501, a Mg-doped p-GaN layer may be used in consideration of the larger value of the first concentration, so that the first concentration is 110 18 To 110 20cm-3.
The second concentration is greater than 0 and less than or equal to 11018cm-3。
In the case of forming two transistors with different threshold voltages on the same substrate 100, in order to achieve the second concentration of the p-type doping element in the second transistor structure 502, the second concentration may be 0 to 1 by using unintentionally doped u-GaN or lightly doped p-GaN to dope the second transistor structure 502 in consideration of the smaller value of the second concentration10 18cm-3.
Considering that the doped p-type doping element may form a magnesium hydrogen bond with elemental hydrogen and the like in the implementation process, the p-type doping element in the magnesium hydrogen bond is in an inactive state and cannot influence the concentration value, in the second implementation mode, high-temperature annealing treatment is required to break the magnesium hydrogen bond, so that magnesium in the magnesium hydrogen bond is in an effective active state, and the concentration of the p-type doping element is improved.
In the embodiment of the present application, in order to form a plurality of transistors with different threshold voltages on the same substrate 100, a manner of controlling the thickness may be adopted in addition to a manner of controlling the concentration of the p-type doping element, which will be described below.
In another embodiment, the first transistor structure 501 has a first thickness along a first direction.
The second transistor structure 502 has a second thickness in the first direction, the second thickness being different from the first thickness.
Wherein the first direction is a lamination direction of the buffer layer 200, the channel layer 300, and the barrier layer 400 on the substrate 100.
To facilitate process fabrication, it is also possible to fabricate multiple transistors with different threshold voltages on the same substrate 100 by controlling the thickness of the first transistor structure 501 and the second transistor structure 502.
Referring to fig. 2, in a lamination direction of the buffer layer 200, the channel layer 300, and the barrier layer 400 on the substrate 100, the first transistor structure 501 has a first thickness, and the second transistor structure 502 has a second thickness, which is different from the first thickness.
In the case where the doping concentrations of the p-type doping elements in the first transistor structure 501 and the second transistor structure 502 are the same, the first thickness is larger than the second thickness so that the threshold voltage of the first transistor 600 is larger than the threshold voltage of the second transistor 600', and the first thickness is smaller than the second thickness so that the threshold voltage of the first transistor 600 is smaller than the threshold voltage of the second transistor 600'.
In the case where the doping concentrations of the p-type doping elements in the first transistor structure 501 and the second transistor structure 502 are not the same, the threshold voltage of the first transistor 600 and the threshold voltage of the second transistor 600' may be determined by combining two factors of the doping concentration and the thickness. Illustratively, when the doping concentration of the p-type doping element in the first transistor structure 501 is greater than the doping concentration of the p-type doping element in the second transistor structure 502, if the first thickness of the first transistor structure 501 is equal to or greater than the second thickness of the second transistor structure 502, the threshold voltage of the first transistor 600 will be greater than the threshold voltage of the second transistor 600', and otherwise will not be described in detail herein.
In the embodiment of the present application, in addition to the transistors having different threshold voltages, three or more transistors having different threshold voltages can be formed on the same substrate 100, and the following description will be given by taking, as an example, the case where three or more transistors having different threshold voltages are formed on the same substrate 100, and of course, three or more transistors having different threshold voltages can be formed on the same substrate 100.
Referring to fig. 3, the semiconductor device structure further includes a third transistor 600″.
The gate cap layer further includes a third transistor structure.
Referring to fig. 3, the first transistor structure 501, the second transistor structure 502 and the third transistor structure respectively belong to different transistors, that is, the first transistor structure 501 belongs to a component of the first transistor 600, the second transistor structure 502 belongs to a component of the second transistor 600', and the third transistor structure belongs to a component of the third transistor 600″.
Similarly, in addition to the third transistor structure, the third transistor 600″ further includes a gate electrode 603″ stacked on the third transistor structure, and includes a source electrode 601″ and a drain electrode 602″ disposed on the barrier layer 400.
Similarly, the source 601″ and drain 602″ may also form an ohmic contact with the two-dimensional electron gas, thereby providing a basis for the unimpeded transport of carriers between the metal and semiconductor.
It should be noted that the number of the third transistor structures may be plural on the same substrate 100, so that three transistors with different threshold voltages may be fabricated on the same substrate 100, that is, the same substrate 100 includes plural first transistors 600, plural second transistors 600', and plural third transistors 600″.
The p-type doped element in the third transistor structure has a third concentration, and the second concentration is greater than the third concentration, that is, the first concentration is greater than the second concentration, and the second concentration is greater than the third concentration, which is described below by way of example.
Illustratively, the first concentration is greater than 110 19cm-3, And a first concentration of less than or equal to 11020cm-3。
In the case of forming three transistors having different threshold voltages on the same substrate 100, in order to achieve the first concentration of the p-type doping element in the first transistor structure 501, the p-type doping element may be doped into the first transistor structure 501 by using a Mg-doped p-GaN layer in consideration of the larger value of the first concentration, so that the first concentration is 110 19 To 110 20cm-3.
The second concentration is greater than 110 18cm-3, And a second concentration of less than or equal to 11019cm-3。
In the case of forming three transistors having different threshold voltages on the same substrate 100, in order to achieve the second concentration of the p-type doping element in the second transistor structure 502, the second concentration may be 1 by doping the p-type doping element in the second transistor structure 502 with lightly doped p-GaN, considering that the value of the second concentration is smaller10 18cm-3 To 110 19cm-3.
Considering that the doped p-type doping element possibly forms a magnesium hydrogen bond with elemental hydrogen and the like in the implementation process, the p-type doping element in the magnesium hydrogen bond is in an unactivated state and cannot influence the concentration value, in the second case, high-temperature annealing treatment is needed to break part of the magnesium hydrogen bond, so that the magnesium in part of the magnesium hydrogen bond is in an effective activated state, and the concentration of the p-type doping element is improved.
The third concentration is greater than 0 and less than or equal to 110 18cm-3.
In the case of forming three transistors having different threshold voltages on the same substrate 100, in order to achieve the third concentration of the p-type doping element in the third transistor structure, the p-type doping element may be doped in the third transistor structure in an unintentionally doped u-GaN manner so as to achieve the third concentration of 0 to 1, considering that the value of the third concentration is small10 18cm-3.
Considering that the doped p-type doping element may form a magnesium hydrogen bond with elemental hydrogen and the like in the implementation process, the p-type doping element in the magnesium hydrogen bond is in an inactive state and cannot influence the concentration value, in the third case, high-temperature annealing treatment is required, and the temperature of the high-temperature annealing treatment is higher than that of the second case, so that most of the magnesium hydrogen bond is broken, and most of magnesium in the magnesium hydrogen bond is in an effective active state, and the concentration of the p-type doping element is improved.
In addition, referring to fig. 3, the third transistor structure has a third thickness along the first direction, and the third thickness is different from the second thickness and the first thickness.
Similarly, for ease of process fabrication, it is also possible to fabricate a plurality of transistors having different threshold voltages on the same substrate 100 by controlling the thicknesses of the first transistor structure 501, the second transistor structure 502, and the third transistor structure.
Illustratively, referring to fig. 3, in the stacking direction of the buffer layer 200, the channel layer 300, and the barrier layer 400 on the substrate 100, the first transistor structure 501 has a first thickness, the second transistor structure 502 has a second thickness, and the third transistor structure has a third thickness that is different from both the second thickness and the first thickness.
In the case where the doping concentrations of the p-type doping elements in the first transistor structure 501, the second transistor structure 502, and the third transistor structure are the same, the first thickness is larger than the second thickness and the second thickness is larger than the third thickness in order to make the threshold voltage of the first transistor 600 larger than the threshold voltage of the second transistor 600 'and the threshold voltage of the second transistor 600' larger than the threshold voltage of the third transistor 600″ and the first thickness is smaller than the second thickness and the second thickness is smaller than the third thickness in order to make the threshold voltage of the first transistor 600 smaller than the threshold voltage of the second transistor 600 'and the threshold voltage of the second transistor 600' smaller than the threshold voltage of the third transistor 600″. Illustratively, the third thickness of the third transistor structure is 0.
In the case where the doping concentrations of the p-type doping elements in the first transistor structure 501, the second transistor structure 502, and the third transistor structure are different, the threshold voltage magnitudes of the first transistor 600, the second transistor 600', and the third transistor 600″ may be determined in combination of two factors of the doping concentration and the thickness. Illustratively, when the doping concentration of the p-type doping element in the first transistor structure 501 is greater than the doping concentration of the p-type doping element in the second transistor structure 502, and the doping concentration of the p-type doping element in the second transistor structure 502 is greater than the doping concentration of the p-type doping element in the third transistor structure, if the first thickness of the first transistor structure 501 is greater than the second thickness of the second transistor structure 502, the second thickness of the second transistor structure 502 is greater than the third thickness of the third transistor structure, the threshold voltage of the first transistor 600 will be greater than the threshold voltage of the second transistor 600', and the threshold voltage of the second transistor 600' will be greater than the threshold voltage of the third transistor 600″ and will not be repeated here.
Based on the same inventive concept, the embodiment of the present invention further provides a method for manufacturing a first semiconductor device structure, where the implementation principle of the manufacturing method is similar to that of the foregoing semiconductor device structure, and the specific implementation manner of the manufacturing method may refer to the foregoing embodiment of the semiconductor device structure, and the repetition is omitted.
The method for manufacturing the semiconductor device structure provided by the embodiment of the invention specifically includes the following steps, referring to fig. 4 and 5:
Step 201, forming a buffer layer 200, a channel layer 300 and a barrier layer 400 sequentially stacked on a substrate 100.
The process may include forming the buffer layer 200, the channel layer 300, and the barrier layer 400 sequentially stacked on the substrate 100 by using a chemical vapor deposition (Chemical Vapor Deposition, CVD) process, using methane or propane as a material growth gas, and using hydrogen as a carrier gas, but the buffer layer 200, the channel layer 300, and the barrier layer 400 may be obtained by other methods known to those skilled in the art, and is not limited thereto.
Step 202, forming a first transistor structure 501 over the barrier layer 400, the first transistor structure 501 having a first concentration of a p-type dopant element.
Considering that the first transistor structure 501 is a component of the first transistor 600, the threshold voltage of the first transistor 600 is relatively high, and in order to make the p-type doped element in the first transistor structure 501 have a relatively high first concentration, the first transistor structure 501 corresponding to the first transistor 600 needs to be fabricated first in the fabrication process. The forming the first transistor structure 501 on the barrier layer 400 specifically includes:
(1) A first initial structure is formed over the barrier layer 400.
The gate cap 5010 stacked on the barrier layer 400 in the present application is a first initial structure formed on the barrier layer 400. In the fabrication process, the first initial structure may be understood as a gate cap 5010 covering the entire surface of the barrier layer 400.
(2) The first initial structure is annealed at a first temperature such that the first initial structure is converted into a first transistor structure 501.
Doping the first initial structure by using the p-type doping element to ensure that the first concentration of the p-type doping element in the first initial structure is 110 18cm-3 To 110 20cm-3, Since a plurality of transistors with different threshold voltages need to be formed on the same substrate 100 in the present application, further annealing treatment is required to be performed on the first initial structure, so as to complete the doping treatment, so that the p-type doping element doped in the first initial structure has the first concentration.
Thereafter, a first mask region is defined by photolithography, and a gate cap layer other than the first transistor structure 501 is removed by using a mixed gas such as chlorine gas or boron trichloride, so that the first initial structure is converted into the first transistor structure 501.
Step 203, forming a second transistor structure 502 over the barrier layer 400, wherein the p-type doping element in the second transistor structure 502 has a second concentration, and the first concentration is greater than the second concentration.
It should be further noted that, in order to make the p-type doped element have the second lower concentration in the second transistor structure 502, the second transistor structure 502 is formed on the barrier layer 400, which specifically includes:
1) A second initial structure is formed over the barrier layer 400.
In the fabrication process, the entire growth of the mask medium, illustratively SiO2, is performed by plasma enhanced chemical Vapor Deposition (PLASMA ENHANCED CHEMICAL Vapor Deposition, PECVD), which is the second initial structure formed over the barrier layer 400.
Doping the second initial structure by using the p-type doping element to enable the second concentration of the p-type doping element in the second initial structure to be between 0 and 110 18cm-3.
2) The second initial structure is annealed at a second temperature such that the second initial structure is converted to a second transistor structure 502, wherein the second temperature is lower than the first temperature.
To form the second transistor structure 502, the second initial structure is annealed to complete the doping process such that the p-type doping element doped in the second initial structure has a second concentration. The second temperature of the anneal is lower than the first temperature, thereby resulting in a second transistor 600' having a threshold voltage that is less than the threshold voltage of the first transistor 600.
And then, photoetching to define a second mask region, and partially removing the mask layer by utilizing wet hydrogen chloride corrosion or by adopting CF 4/CHF3 dry etching.
The growth of the second transistor structure 502 is completed by Metal-organic chemical vapor deposition (Metal-organic Chemical Vapor Deposition, MOCVD), and the barrier layer 400 (mainly including nitride) does not grow in the region where the mask dielectric layer is located because of lattice mismatch between the mask dielectric and the gate cap layer, and poor adhesion between the mask dielectric and the gate cap layer.
After the second transistor structure 502 is formed, the mask medium is removed by a wet removal method, that is, an acidic solution such as hydrochloric acid is used to remove the mask medium.
After the second transistor structure 502 is formed, the second transistor structure 502 and the first transistor structure 501 are disposed adjacently or separately on the barrier layer 400, and the film layers where the first transistor structure 501 and the second transistor structure 502 are disposed are collectively referred to as a gate cap layer, and in some embodiments, the gate cap layer may further include the third transistor structure, a fourth structure corresponding to a transistor with a fourth threshold voltage, and so on, which are not described herein in detail.
The p-type doping element in the first transistor structure 501 has the first concentration. The p-type dopant element in the second transistor structure 502 has a second concentration, the first concentration being greater than the second concentration.
In order to form the source electrode 601 and the drain electrode 602 of the first transistor 600, a part of the barrier layer 400 is etched and removed by using a mixed gas such as chlorine or boron trichloride in a corresponding region of the first transistor structure 501, then holes are formed in the region corresponding to the source electrode 601 and the drain electrode 602 in the barrier layer 400, metals except the source and drain regions are removed by dry etching in a manner of growing source and drain metals (for example, ti/Al/Ti/TiN) by sputtering, and then annealing is completed in a nitrogen atmosphere, so that oxygen is isolated by using an inert environment of nitrogen, and oxidation of the metals at a high temperature is prevented.
Similarly, to form the gate 603 of the first transistor 600, a gate metal (e.g., tiN) is sputter grown on the first transistor structure 501, and the other portions of the metal are removed by dry etching.
The first transistor 600 is formed by the above steps such that the p-type doping element in the first transistor structure 501 has a first concentration.
In order to form the source electrode 601' and the drain electrode 602' of the second transistor 600', part of the barrier layer 400 is etched and removed by using a mixed gas such as chlorine or boron trichloride in a corresponding region of the second transistor structure 502, holes are formed in the region corresponding to the source electrode 601' and the drain electrode 602' in the barrier layer 400, metals outside the source drain region are removed by dry etching in a manner of sputtering and growing source drain metal (for example, ti/Al/Ti/TiN), and annealing is completed in a nitrogen atmosphere, so that oxygen is isolated by using an inert environment of nitrogen, and oxidation of the metals at a high temperature is prevented.
Similarly, to form the gate 603 'of the second transistor 600', a gate metal (e.g., tiN) is sputter grown on the second transistor structure 502, and the other portions of the metal are dry etched away.
The second transistor 600' is formed by the above steps such that the p-type doping element in the second transistor structure 502 has a second concentration.
Based on the same inventive concept, referring to fig. 6, an embodiment of the present application provides an electronic device including the semiconductor device structure described above.
Specific application scenarios of the electronic device include, but are not limited to, vehicle-mounted chips, high-voltage inverters, charging piles, high-voltage photovoltaics and the like.
It will be apparent to those skilled in the art that various modifications and variations can be made to the present application without departing from the spirit or scope of the application. Thus, it is intended that the present application also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.
Claims (10)
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20030081596A (en) * | 2002-04-12 | 2003-10-22 | 광주과학기술원 | STRUCTURE AND MANUFACTURING METHOD FOR MONOLITHICALLY INTEGRATED ENHANCEMENT/DEPLETION MODE (p-)HEMT DEVICES |
| CN115632068A (en) * | 2022-10-17 | 2023-01-20 | 深圳天狼芯半导体有限公司 | A P-type GaN High Electron Mobility Transistor |
| US20230335597A1 (en) * | 2020-12-20 | 2023-10-19 | Huawei Technologies Co., Ltd. | Gallium nitride power transistor |
| US20250031398A1 (en) * | 2022-07-07 | 2025-01-23 | Guangdong Institute of Semiconductor Micro-Nano Manufacturing Technology | Gan-based hemt structure having multi-threshold voltage, and preparation method and application therefor |
-
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- 2025-07-29 CN CN202511051606.2A patent/CN120547932A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20030081596A (en) * | 2002-04-12 | 2003-10-22 | 광주과학기술원 | STRUCTURE AND MANUFACTURING METHOD FOR MONOLITHICALLY INTEGRATED ENHANCEMENT/DEPLETION MODE (p-)HEMT DEVICES |
| US20230335597A1 (en) * | 2020-12-20 | 2023-10-19 | Huawei Technologies Co., Ltd. | Gallium nitride power transistor |
| US20250031398A1 (en) * | 2022-07-07 | 2025-01-23 | Guangdong Institute of Semiconductor Micro-Nano Manufacturing Technology | Gan-based hemt structure having multi-threshold voltage, and preparation method and application therefor |
| CN115632068A (en) * | 2022-10-17 | 2023-01-20 | 深圳天狼芯半导体有限公司 | A P-type GaN High Electron Mobility Transistor |
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