CN120567160B - Ring oscillator, chip and electronic device hardened by reverse clock compensation - Google Patents
Ring oscillator, chip and electronic device hardened by reverse clock compensationInfo
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- CN120567160B CN120567160B CN202511063052.8A CN202511063052A CN120567160B CN 120567160 B CN120567160 B CN 120567160B CN 202511063052 A CN202511063052 A CN 202511063052A CN 120567160 B CN120567160 B CN 120567160B
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- delay node
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Abstract
本发明公开了一种利用相反时钟补偿加固的环形振荡器、芯片及电子设备，本发明的环形振荡器包含用于对延迟节点的输出引脚OUT1利用相反时钟补偿加固的补偿加固电路，补偿加固电路包括2个PMOS晶体管M1和M2，2个NMOS晶体管M3和M4，PMOS晶体管M1的源极接电压VDD、漏极依次通过串联的PMOS晶体管M2、NMOS晶体管M3、M4接地，PMOS晶体管M1和NMOS晶体管M4的栅极连接到输出引脚OUT1，PMOS晶体管M2、NMOS晶体管M3的栅极均与输出引脚OUT1信号互补的输入引脚IN3相连。本发明旨在针对环形振荡器实现抗辐射加固，提高环形振荡器的抗单粒子效应干扰的性能。
The present invention discloses a ring oscillator, chip, and electronic device that utilizes reverse clock compensation for reinforcement. The ring oscillator includes a compensation reinforcement circuit for reinforcing the output pin OUT1 of a delay node using reverse clock compensation. The compensation reinforcement circuit includes two PMOS transistors M1 and M2, and two NMOS transistors M3 and M4. The source of the PMOS transistor M1 is connected to voltage VDD, and its drain is connected to ground via a series connection of PMOS transistors M2, M3, and M4. The gates of the PMOS transistors M1 and M4 are connected to the output pin OUT1, and the gates of the PMOS transistors M2 and NMOS transistors M3 are both connected to the input pin IN3, which has a complementary signal to the output pin OUT1. The present invention aims to provide radiation hardening for the ring oscillator and improve its resistance to single-event interference.
Description
Technical Field
The present invention relates to Ring oscillators (Ring OSCs), and more particularly to Ring oscillators, chips and electronic devices that are ruggedized with counter clock compensation.
Background
A Ring oscillator (Ring OSC) is an oscillator structure based on delay nodes, and is usually formed by a plurality of inverters or delay nodes connected in series, and the total delay time in the loop is used to determine the oscillation frequency. The ring oscillator has lower power consumption, does not need large-size elements such as inductors, occupies smaller area in the chip, and is suitable for application scenes with low power consumption and high integration level. Referring to fig. 1, the ring oscillator is formed by connecting 10 identical delay nodes Unit 0-Unit 9 end to end, outputting 10 phase clocks out_buf <0:9>, each delay node has a power pin V IN, two input pins IN1 and IN2, and two output pins Out1 and Out2, and the power pin V IN is connected with a control signal V OSC. Referring to fig. 2, the delay node in the ring oscillator is formed by a cascade of three stages of inverters, with the first two stages of inverters participating in forming a clock loop, and the last stage of inverters not being in the loop, but simply pushing out the clock signal. The control signal V OSC controls the ring oscillator operating frequency, the greater its value, the higher the operating frequency. The ring oscillator is shown in FIG. 3 with a 10-phase clock output out_buf <0:9> at 16 GHz. For the whole ring oscillator loop, it is equivalent to perform the double exponential current source injection at the three delay nodes IN1, IN2, OUT1, so only the OUT1 delay node IN delay node Unit0 is subjected to the current injection. The ring oscillator circuit works at 16GHz and performs double-exponential current injection at 0.2ns, wherein the current is positive to simulate bombarding the NMOS transistor, and the current is negative to simulate bombarding the PMOS transistor, and as a result, as shown in fig. 4, the output is affected by a single event effect, and disturbance is generated.
Disclosure of Invention
The invention aims to solve the technical problems in the prior art and provide a ring oscillator, a chip and electronic equipment which are reinforced by utilizing opposite clock compensation.
In order to solve the technical problems, the invention adopts the following technical scheme:
A ring oscillator reinforced by reverse clock compensation comprises a ring oscillator circuit body formed by connecting a plurality of delay nodes IN series, wherein the ring oscillator circuit body comprises a compensation reinforcing circuit for reinforcing an output pin OUT1 of the delay nodes by reverse clock compensation, the compensation reinforcing circuit comprises 2 PMOS transistors M1 and M2 and 2 NMOS transistors M3 and M4, the source electrode of the PMOS transistor M1 is connected with a voltage VDD, the drain electrode of the PMOS transistor M1 is connected with the ground through the PMOS transistor M2, the NMOS transistor M3 and the NMOS transistor M4 which are connected IN series, the grid electrodes of the PMOS transistor M1 and the NMOS transistor M4 are connected to an output pin OUT1 of the delay nodes so as to compensate the output pin OUT1 of the delay nodes, and the grid electrodes of the PMOS transistor M2 and the NMOS transistor M3 are connected with an input pin IN3 which is complementary with the output pin OUT1 signal IN the ring oscillator.
Optionally, the delay node includes cascaded three-stage inverters, each of which is composed of a PMOS transistor and an NMOS transistor connected IN series, wherein a source of the PMOS transistor is connected to the control signal V OSC, a source of the NMOS transistor is grounded, gates of the PMOS transistor and the NMOS transistor IN the first-stage inverter are connected to the input pin IN2 of the delay node, and drains of the PMOS transistor and the NMOS transistor are connected to the input pin IN1 of the delay node, gates of the PMOS transistor and the NMOS transistor IN the second-stage inverter are connected to the input pin IN1 of the delay node, and drains of the PMOS transistor and the NMOS transistor are connected to the output pin OUT1 of the delay node, and drains of the PMOS transistor and the NMOS transistor IN the third-stage inverter are connected to the output pin OUT2 of the delay node.
Optionally, the ring oscillator circuit body is a ring structure formed by 10 delay nodes connected in series.
In addition, the invention also provides a chip, which comprises a chip body and a circuit module arranged in the chip body, wherein the circuit module comprises the ring oscillator reinforced by reverse clock compensation.
In addition, the invention also provides electronic equipment, which comprises an equipment body and a circuit module arranged in the equipment body, wherein the circuit module comprises the ring oscillator reinforced by reverse clock compensation.
Compared with the prior art, the ring oscillator has the advantages that the ring oscillator comprises the compensation and reinforcement circuit for compensating and reinforcing the output pin OUT1 of the delay node by utilizing the reverse clock, the compensation and reinforcement circuit comprises 2 PMOS transistors M1 and M2 and 2 NMOS transistors M3 and M4, the source electrode of the PMOS transistor M1 is connected with the voltage VDD, the drain electrode of the PMOS transistor M1 is grounded through the PMOS transistor M2 and the NMOS transistors M3 and M4 which are connected IN series IN sequence, the grid electrodes of the PMOS transistor M1 and the NMOS transistor M4 are connected to the output pin OUT1, and the grid electrodes of the PMOS transistor M2 and the NMOS transistor M3 are connected with the input pin IN3 which is complementary with the output pin OUT1 signal.
Drawings
Fig. 1 is a schematic circuit diagram of a conventional ring oscillator.
Fig. 2 is a schematic diagram of a delay node in a conventional ring oscillator.
FIG. 3 shows a 10-phase clock output at 16GHz for a conventional ring oscillator, where (a) is the clock output for the first 5 phases (Out_buf <0> -Out_buf <4 >) and (b) is the clock output for the second 5 phases (Out_buf <5> -Out_buf <9 >).
Fig. 4 shows the output of a conventional ring oscillator under the influence of the single event effect, where (a) is the output of the output pin OUT1 when the current is positive to simulate the bombarding NMOS transistor, and (b) is the output of the output pin OUT1 when the current is negative to simulate the bombarding PMOS transistor.
FIG. 5 shows the results of a dual-exponential current simulation of a 10-phase output of a conventional ring oscillator under the influence of a single event effect, wherein (a) is the clock output of the first 5 phases (Out_buf <0> -Out_buf <4 >) and (b) is the clock output of the second 5 phases (Out_buf <5> -Out_buf <9 >).
Fig. 6 is a schematic circuit diagram of a delay node of a ring oscillator and its compensation reinforcement circuit according to an embodiment of the present invention.
Fig. 7 is a schematic diagram of a compensation principle of the compensation reinforcement circuit according to an embodiment of the present invention.
Fig. 8 is a schematic diagram of simulation experiment results of a ring oscillator according to an embodiment of the present invention.
Detailed Description
In order to enable those skilled in the art to better understand the technical solution of the present invention, the technical solution of the present invention will be further described in detail below with reference to the accompanying drawings in the embodiments of the present invention.
Fig. 5 shows the results of a double-exponential current simulation of the 10-phase output out_buf <0:9> of a conventional ring oscillator under the influence of the single event effect, and referring to fig. 5, it is found that the current impact on the output out_buf <0> of the delay node Unit 0 is the most serious in the 10-phase output, and the output out_buf <3> of the delay node Unit 9 logically connected with the current impact on the Unit 2-6 at a longer distance is less affected. According to the double-exponential current simulation result of fig. 5, it can be found that when the output pin OUT1 of the delay node Unit 0 is bombarded, the corresponding reverse clock is used, the output of the output pin OUT1 of the delay node Unit 5 is affected very little, and the output of the output pin OUT1 of the delay node Unit 5 can be input to the output pin OUT1 of the delay node Unit 0 after being reversed when single event occurs, so as to help the recovery of the normal working state.
Based on the above-described concept, the present embodiment provides a ring oscillator with inverse clock compensation and reinforcement, including a ring oscillator circuit body composed of a plurality of delay nodes connected IN series, as shown IN fig. 6, the ring oscillator circuit body includes a compensation and reinforcement circuit (shown by a dashed box IN the figure) for compensating and reinforcing an output pin OUT1 of the delay node with inverse clock, the compensation and reinforcement circuit includes 2 PMOS transistors M1 and M2, and 2 NMOS transistors M3 and M4, the source electrode of the PMOS transistor M1 is connected to a voltage VDD, the drain electrode is connected to ground through the PMOS transistor M2, the NMOS transistor M3, and the NMOS transistor M4 connected IN series IN order, and the gates of the PMOS transistor M1 and the NMOS transistor M4 are connected to an output pin OUT1 of the delay node to compensate the output pin OUT1 of the delay node, and the gates of the PMOS transistor M2 and the NMOS transistor M3 are connected to an input pin IN3 of the ring oscillator, which is complementary to the output pin OUT1 signal.
Taking the delay node Unit 0 as an example, the circuit added IN the dashed box includes 2 PMOS transistors and 2 NMOS transistors, IN3 is the output OUT1 of the delay node Unit 5, and fig. 7 is a schematic diagram of the compensation principle of the compensation reinforcement circuit according to the embodiment of the present invention, as it can be seen IN fig. 7, under normal conditions, the OUT1 and IN3 signals are complementary, one is 1, and the other is 0, so the circuit is not turned on, is IN an off-state, and does not affect the output clock (denoted as NONE IN fig. 7). When the OUT1 node is affected by a single event effect, the IN3 input keeps a normal state, the complementary state is damaged, the circuit starts to work and is IN an on-state (open) state, when the two data are the same, the data of the OUT1 are indicated to be overturned, the IN3 data are just correct data of the OUT1 after being reversed, and the OUT1 output can be compensated.
As shown IN fig. 6, the delay node IN this embodiment includes cascaded three-stage inverters, each of which is composed of a PMOS transistor and an NMOS transistor connected IN series, wherein the source of the PMOS transistor is connected to the control signal V OSC, the source of the NMOS transistor is grounded, the gates of the PMOS transistor and the NMOS transistor IN the first-stage inverter are connected to the input pin IN2 of the delay node, the drains of the PMOS transistor and the NMOS transistor are connected to the input pin IN1 of the delay node, the gates of the PMOS transistor and the NMOS transistor IN the second-stage inverter are connected to the input pin IN1 of the delay node, the drains of the PMOS transistor and the NMOS transistor are connected to the output pin OUT1 of the delay node, and the drains of the PMOS transistor and the NMOS transistor IN the third-stage inverter are connected to the output pin OUT2 of the delay node.
In this embodiment, the ring oscillator circuit body is a ring structure formed by connecting 10 delay nodes in series, and the 10 delay nodes form the ring structure by connecting the delay nodes end to end.
In order to verify the strengthening effect of the ring oscillator strengthened by the reverse clock compensation in the embodiment, simulation verification is performed on the ring oscillator strengthened by the reverse clock compensation, the working frequency of the ring oscillator is reduced from 16GHz to 11GHz under the same configuration after strengthening, which is caused by load change after adding transistors, and the final result is shown in fig. 8. As shown in fig. 8, the ring oscillator of the present embodiment, which is reinforced by reverse clock compensation, has a good recovery effect and an improved out_buf <0> signal quality compared to an unreinforced circuit after injecting the same double exponential current. Therefore, the ring oscillator with opposite clock compensation reinforcement can realize radiation resistance reinforcement for the ring oscillator, improve the performance of the ring oscillator for resisting single event effect interference, and have the advantage of low cost.
In addition, the embodiment also provides a chip, which comprises a chip body and a circuit module arranged in the chip body, wherein the circuit module comprises the ring oscillator reinforced by reverse clock compensation.
In addition, the embodiment also provides electronic equipment, which comprises an equipment body and a circuit module arranged in the equipment body, wherein the circuit module comprises the ring oscillator reinforced by reverse clock compensation.
The above description is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above examples, and all technical solutions belonging to the concept of the present invention belong to the protection scope of the present invention. It should be noted that modifications and adaptations to the present invention may occur to one skilled in the art without departing from the principles of the present invention and are intended to be within the scope of the present invention.
Claims (3)
1. A ring oscillator reinforced by reverse clock compensation, comprising a ring oscillator circuit body formed by serially connecting a plurality of delay nodes, characterized IN that the ring oscillator circuit body comprises a compensation reinforcing circuit reinforced by reverse clock compensation for an output pin OUT1 of the delay node, the compensation reinforcing circuit comprises 2 PMOS transistors M1 and M2 and 2 NMOS transistors M3 and M4, the source electrode of the PMOS transistor M1 is connected with a voltage VDD, the drain electrode is sequentially connected with a PMOS transistor M2, an NMOS transistor M3 and an NMOS transistor M4 IN series, the gates of the PMOS transistor M1 and the NMOS transistor M4 are connected to the output pin OUT1 of the delay node to compensate the output pin OUT1 of the delay node, the gates of the PMOS transistor M2 and the NMOS transistor M3 are connected with an input pin IN3 complementary to the output pin OUT1 signal IN the ring oscillator, the delay node comprises cascaded three-stage inverters each composed of a PMOS transistor and an NMOS transistor, wherein the source electrode of the PMOS transistor OSC is connected with a control signal V35, the drain electrode of the PMOS transistor is connected with the input pin OUT1 of the delay node, the output pin OUT1 of the delay node is connected with the output pin OUT1 of the delay node, the delay node is connected with the input pin OUT1 of the delay node, and the delay node is connected with the output pin OUT1 of the delay node is connected with the output of the delay node, and the delay node is connected with the output pin OUT 3 of the delay node is connected with the output node by the output node And the drains of the PMOS transistor and the NMOS transistor are connected to the output pin OUT2 of the delay node, and the ring oscillator circuit body is of a ring structure formed by 10 delay nodes connected in series.
2.A chip comprising a chip body and a circuit module disposed in the chip body, wherein the circuit module comprises the ring oscillator of claim 1 reinforced with counter clock compensation.
3. An electronic device comprising a device body and a circuit module disposed in the device body, wherein the circuit module comprises the ring oscillator of claim 1 reinforced with counter clock compensation.
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| CN202511063052.8A CN120567160B (en) | 2025-07-31 | 2025-07-31 | Ring oscillator, chip and electronic device hardened by reverse clock compensation |
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| CN202511063052.8A CN120567160B (en) | 2025-07-31 | 2025-07-31 | Ring oscillator, chip and electronic device hardened by reverse clock compensation |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105515577A (en) * | 2015-12-29 | 2016-04-20 | 中国科学院电子学研究所 | Anti-SET solidified ring oscillator |
| CN111091855A (en) * | 2018-10-24 | 2020-05-01 | 中国科学院上海微系统与信息技术研究所 | Single event upset detection circuit and method based on static random access memory cell array |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JPH0766715A (en) * | 1993-08-27 | 1995-03-10 | Fujitsu Ltd | Output buffer circuit |
| US5949292A (en) * | 1997-12-15 | 1999-09-07 | Texas Instruments Incorporated | Ring oscillator using current robbing for controlling delay period |
| US6075419A (en) * | 1999-01-29 | 2000-06-13 | Pmc-Sierra Ltd. | High speed wide tuning range multi-phase output ring oscillator |
| EP2107680B1 (en) * | 2004-02-04 | 2012-01-25 | Japan Aerospace Exploration Agency | Single-event-effect tolerant SOI-based data latch device |
| US8031809B2 (en) * | 2007-02-28 | 2011-10-04 | Seiko Epson Corporation | Template pulse generating circuit, communication device, and communication method |
| US8395455B1 (en) * | 2011-10-14 | 2013-03-12 | United Microelectronics Corp. | Ring oscillator |
| US12244312B2 (en) * | 2022-12-05 | 2025-03-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Low noise ring oscillator devices and methods |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105515577A (en) * | 2015-12-29 | 2016-04-20 | 中国科学院电子学研究所 | Anti-SET solidified ring oscillator |
| CN111091855A (en) * | 2018-10-24 | 2020-05-01 | 中国科学院上海微系统与信息技术研究所 | Single event upset detection circuit and method based on static random access memory cell array |
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