CN120710467A - PVT stable annular amplifier and electronic equipment - Google Patents

Abstract

The invention relates to the technical field of amplifiers, and discloses a PVT stable annular amplifier and electronic equipment. The first-stage structure and the second-stage structure of the standard annular amplifier are the first-stage structure and the second-stage structure, in the third-stage structure, the first PMOS tube and the first NMOS tube work in a subthreshold region when dead zone voltage is generated by the second-stage structure, the second PMOS tube and the second NMOS tube are respectively connected with common mode voltage from respective grid electrodes, so that the second PMOS tube and the second NMOS tube work in a linear region and are equivalent to a resistor, and the voltage difference between the source electrode of the first PMOS tube and the source electrode of the first NMOS tube is restrained through the voltage division effect of the resistor, so that when the dead zone voltage generated by the second-stage structure changes under the influence of PVT, the first PMOS tube and the first NMOS tube still work in the subthreshold region, and the PVT stable annular amplifier stably amplifies input signals.

Description

PVT stable annular amplifier and electronic equipment

Technical Field

The invention relates to the technical field of amplifiers, in particular to a PVT stable annular amplifier and electronic equipment.

Background

In ADCs of different architectures, such as Pipeline Analog-to-Digital Converter, PIPELINEADC, pipeline successive approximation Analog-to-digital converter PIPELINE SARADC, and Delta-Sigma ADC employing Delta-Sigma modulation techniques to achieve high precision signal sampling, switched capacitor amplifier circuits are an essential part, and operational amplifiers therein directly affect the performance of the overall ADC, generally requiring high gain and high bandwidth. However, the conventional folded cascode operational amplifier tends to have larger power consumption, and the difficulty of designing the conventional folded cascode operational amplifier under the condition of a deep micro sub-meter process with low power supply voltage is great, which limits the application range of the ADC with the above architecture.

In order to solve this problem, a ring amplifier is proposed, which meets the requirements of high gain, high bandwidth and low power consumption, and meanwhile, the difficulty of design is greatly reduced because of the fewer Metal-Oxide-semiconductor field-EffectTransistor, MOS transistors (Metal-Oxide-semiconductor field-EffectTransistor, MOS transistors) which are stacked. The annular amplifier is generally of a three-stage structure, and two MOS tubes of the output stage are enabled to enter a subthreshold region through setting dead zone voltage, so that larger output impedance is generated, an output pole is enabled to move left, the annular amplifier is enabled to have enough phase margin, finally the annular amplifier is enabled to be finally stabilized, and signals can be amplified stably.

It can be seen that the magnitude of the dead band voltage directly determines the operating state of the ring amplifier, but in practical situations, it is difficult to obtain an accurate dead band voltage due to the process, the supply voltage and the temperature (Process, supplyVoltage, temperature, PVT) conditions of the ring amplifier, and it is difficult to make the ring amplifier operate in a desired operating state, so that the ring amplifier is subject to a great PVT condition disturbance in practical applications.

Disclosure of Invention

The invention aims to provide a PVT stable annular amplifier and electronic equipment, which can improve PVT resistance of the annular amplifier.

In order to solve the technical problems, the embodiment of the invention provides a PVT stable annular amplifier, wherein a first stage structure and a second stage structure of the PVT stable annular amplifier are the first stage structure and the second stage structure of a standard annular amplifier, and a third stage structure of the PVT stable annular amplifier comprises a first PMOS tube, a first NMOS tube, a second PMOS tube and a second NMOS tube, wherein a source electrode of the first PMOS tube is connected with a drain electrode of the second PMOS tube, a source electrode of the first NMOS tube is connected with a drain electrode of the second NMOS tube, a source electrode of the second PMOS tube is connected with a power supply, and a source electrode of the second NMOS tube is grounded;

The first PMOS tube and the first NMOS tube work in a subthreshold region when dead zone voltage is generated in a second-stage structure of the annular amplifier, so that the PVT stable annular amplifier stably amplifies an input signal;

The second PMOS tube and the second NMOS tube are respectively connected into a preset common-mode voltage from respective grid electrodes, so that the second PMOS tube and the second NMOS tube both work in a linear region, the second PMOS tube and the second NMOS tube are respectively equivalent to a resistor, and the voltage difference between the source electrode of the first PMOS tube and the source electrode of the first NMOS tube is restrained through the voltage division effect of the resistor, so that when the dead zone voltage generated by the second-stage structure changes under the influence of PVT, the first PMOS tube and the first NMOS tube still keep working in a subthreshold region.

In some optional embodiments, the first stage structure of the PVT stabilized ring amplifier includes a third PMOS transistor and a third NMOS transistor, a gate of the third PMOS transistor is connected to a gate of the third NMOS transistor, a drain of the third PMOS transistor is connected to a drain of the third NMOS transistor, a source of the third PMOS transistor is connected to a power supply, and a source of the third NMOS transistor is grounded;

The second-stage structure of the PVT stable annular amplifier comprises a fourth PMOS tube, a fourth NMOS tube and a resistor, wherein the grid electrode of the fourth PMOS tube is connected with the grid electrode of the fourth NMOS tube, and the drain electrode of the fourth PMOS tube and the drain electrode of the fourth NMOS tube are respectively connected with two ends of the resistor.

In some alternative embodiments, the input signal of the PVT stabilized ring amplifier is input from the gates of the third PMOS and the third NMOS, and the amplified input signal is output from the drains of the first PMOS and the first NMOS of the PVT stabilized ring amplifier.

In some alternative embodiments, the third PMOS transistor and the third NMOS transistor both operate in a saturation region to amplify an input signal;

The fourth PMOS tube and the fourth NMOS tube also work in a saturation region, and dead zone voltage is obtained through voltage drop generated by current flowing through a resistor.

In some alternative embodiments, the first, second and third stage structures of the PVT stabilized ring amplifier are directly coupled by the following connection:

the drain electrode of the third PMOS tube is connected with the grid electrode of the fourth PMOS tube, the drain electrode of the third NMOS tube is connected with the grid electrode of the fourth NMOS tube, the drain electrode of the fourth PMOS tube is connected with the grid electrode of the first PMOS tube, and the drain electrode of the fourth NMOS tube is connected with the grid electrode of the first NMOS tube.

In some optional embodiments, the substrates of the first NMOS transistor, the second NMOS transistor, the third NMOS transistor, and the fourth NMOS transistor are all grounded, and the substrates of the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, and the fourth PMOS transistor are all connected to a power supply, so that a body effect is generated between the first PMOS transistor and the second NMOS transistor, and threshold voltages of the first PMOS transistor and the second NMOS transistor are increased.

In some alternative embodiments, the PVT stabilized ring amplifier is applied in a single-ended switched-capacitor amplification circuit, or in a pseudo-differential amplifier circuit constructed using two identical switched-capacitor amplifier circuits, or in a differential circuit.

The embodiment of the invention also provides electronic equipment, which comprises the PVT stable annular amplifier.

The PVT stable annular amplifier provided by the invention has at least the following beneficial effects:

The traditional annular amplifier (namely the standard annular amplifier) is improved, a PMOS tube and an NMOS tube (namely a second PMOS tube and a second NMOS tube) are added in the third-stage structure of the standard annular amplifier, so that the newly added PMOS tube and NMOS tube work in a linear region and respectively act as a resistor, the voltage division effect of the resistor can be used for inhibiting the power supply voltage (namely the voltage difference between the source electrode of the first PMOS tube and the source electrode of the first NMOS tube) seen by the original PMOS tube and NMOS tube (namely the first PMOS tube and the first NMOS tube) in the third-stage structure, and even if the dead zone voltage generated by the second-stage structure of the annular amplifier changes under the influence of PVT, the first PMOS tube and the first NMOS tube can still work in a subthreshold region, and therefore a larger output impedance is generated, so that the output main is shifted left, the annular amplifier has enough phase margin, and finally the amplifier can be stabilized to amplify signals. According to the invention, the variable range of dead zone voltage can be enlarged only through two MOS tubes, so that the annular amplifier has PVT resistance, cannot be interfered by the PVT resistance, and has low design difficulty.

Drawings

One or more embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings.

FIG. 1 is a schematic diagram of a conventional resistive self-biasing ring amplifier according to one embodiment of the present invention;

FIG. 2 is a schematic diagram of a PVT stabilized ring amplifier provided in accordance with one embodiment of the present invention;

FIG. 3 is a schematic diagram of the variation of the Bode plot of a ring amplifier at the transition from oscillation to steady state, according to one embodiment of the present invention;

fig. 4 is a schematic diagram of a residual amplifying circuit according to an embodiment of the present invention;

FIG. 5 is an enlarged plot of a conventional resistive self-biasing ring amplifier at a CSS process angle of 125, a CTT process angle of 27, and a FF process angle of-40, respectively, taking into account resistive manufacturing errors, in accordance with one embodiment of the present invention;

Wherein, (a) is an amplification curve in the case that the actual resistance value of the resistor is 80% of the design value, (b) is an amplification curve in the case that the actual resistance value of the resistor is 100% of the design value, and (c) is an amplification curve in the case that the actual resistance value of the resistor is 120% of the design value;

FIG. 6 is an enlarged plot of a PVT stabilized ring amplifier at a CSS process angle of 125, a CTT process angle of 27, and a FF process angle of-40, respectively, taking into account resistor fabrication errors, in accordance with one embodiment of the present invention;

wherein, (a) is an amplification curve in the case where the actual resistance value of the resistor is 80% of the design value, (b) is an amplification curve in the case where the actual resistance value of the resistor is 100% of the design value, and (c) is an amplification curve in the case where the actual resistance value of the resistor is 120% of the design value.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings. However, it will be understood by those of ordinary skill in the art that in various embodiments of the present invention, numerous specific details are set forth in order to provide a thorough understanding of the present invention. The claimed invention may be practiced without these specific details and with various changes and modifications based on the following embodiments. The following embodiments are divided for convenience of description, and should not be construed as limiting the specific implementation of the present invention, and the embodiments can be mutually combined and referred to without contradiction.

The most common ring amplifier is a resistor self-bias ring amplifier, which generates a dead zone voltage through a resistor connected to the second stage, and when the resistance value is determined, the magnitude of the dead zone voltage changes according to the current change of the second stage circuit, so that in the practical application process, the change of PVT conditions greatly affects the value of the dead zone voltage. Especially, the manufacturing error of the resistance value can reach +/-20%, which means that even if the current is kept stable, the dead zone voltage still has 20% error, and a high threshold value tube is generally required to be used in the output stage to enable the operational amplifier to have better PVT resistance and tolerance of the resistance manufacturing error. However, there are still problems that the high-threshold tube belongs to a special process and may not be supported by the process, and the impedance of the high-threshold tube is larger than that of a normal MOS tube in a subthreshold region, so that the pole is shifted leftwards, the bandwidth of the annular amplifier is limited, and the amplification of signals is difficult to complete in a short time, so that the high-threshold tube is difficult to be applied to a high-speed application scene.

The PVT stable type annular amplifier provided by the invention realizes the PVT stable type annular amplifier on the premise of not using a high-threshold pipe, so that the condition that the process is not supported is avoided, the bandwidth of the annular amplifier is not lost, and the PVT stable type annular amplifier can be applied to high-speed application scenes.

An embodiment of the present invention relates to a PVT stabilized ring amplifier, which is obtained by modifying a conventional ring amplifier (i.e., a standard ring amplifier), and the standard ring amplifier is specifically a resistor self-bias ring amplifier, and the structure of the standard ring amplifier is specifically shown in fig. 1, while the PVT stabilized ring amplifier of the present embodiment is modified by the resistor self-bias ring amplifier, and the specific structure of the PVT stabilized ring amplifier is shown in fig. 2.

The PVT stabilized ring amplifier of the present embodiment is a three-stage structure formed of a first-stage structure, a second-stage structure, and a third-stage structure, and the first-stage structure, the second-stage structure, and the third-stage structure are connected by direct coupling. The first stage structure is used for receiving an input signal to be amplified, the second stage structure is used for generating dead zone voltage, the first stage structure and the second stage structure are identical to the second stage structure, and the first stage structure and the third stage structure of the traditional annular amplifier are different from the third stage structure of the traditional annular amplifier, and the dead zone voltage generated by the second stage structure is used for enabling the annular amplifier to be in a stable state, so that the annular amplifier can stably amplify the input signal.

The specific structures of the first stage structure, the second stage structure, and the third stage structure of the PVT stabilized ring amplifier of the present embodiment are described below, respectively:

The PVT stabilized ring amplifier shown in fig. 2 is improved in a third stage structure compared with the conventional ring amplifier shown in fig. 1, and the third stage structure of the PVT stabilized ring amplifier specifically includes a first PMOS transistor M5, a first NMOS transistor M6, a second PMOS transistor M7, and a second NMOS transistor M8. The source electrode of the first PMOS tube is connected with the drain electrode of the second PMOS tube, the source electrode of the first NMOS tube is connected with the drain electrode of the second NMOS tube, the source electrode of the drain electrode of the second PMOS tube is connected with the power supply VDD, and the source electrode of the second NMOS tube is grounded GND.

The first stage structure of the PVT stabilized ring amplifier shown in fig. 2 is the same as the conventional ring amplifier shown in fig. 1, and specifically includes a third PMOS transistor M1 and a third NMOS transistor M2. The grid electrode of the third PMOS tube is connected with the grid electrode of the third NMOS tube, the drain electrode of the third PMOS tube is connected with the drain electrode of the third NMOS tube, the source electrode of the third PMOS tube is connected with a power supply, and the source electrode of the third NMOS tube is grounded.

The second stage structure of the PVT stabilized ring amplifier shown in fig. 2 is the same as that of the conventional ring amplifier shown in fig. 1, and specifically includes a fourth PMOS transistor M3, a fourth NMOS transistor M4, and a resistor R. The grid electrode of the fourth PMOS tube is connected with the grid electrode of the fourth NMOS tube, and the drain electrode of the fourth PMOS tube and the drain electrode of the fourth NMOS tube are respectively connected with two ends of the resistor.

In a specific implementation, under the specific structures of the first-stage structure, the second-stage structure and the third-stage structure, the first-stage structure, the second-stage structure and the third-stage structure are directly coupled through the following connection mode that a drain electrode of a third PMOS tube is connected with a grid electrode of a fourth PMOS tube, a drain electrode of a third NMOS tube is connected with the grid electrode of the fourth NMOS tube, a drain electrode of the fourth PMOS tube is connected with the grid electrode of the first PMOS tube, and a drain electrode of the fourth NMOS tube is connected with the grid electrode of the first NMOS tube.

The following describes the operation principle of the first stage structure, the second stage structure, and the third stage structure of the PVT stabilized ring amplifier of the present embodiment:

The input signals of the PVT stable annular amplifier are input from the grid electrodes of the third PMOS tube and the third NMOS tube of the first stage structure, and the third PMOS tube and the third NMOS tube work in a saturation region, so that the input signals are amplified. The fourth PMOS tube and the fourth NMOS tube of the second stage structure also work in a saturation region, and dead zone voltage is obtained through voltage drop generated by current flowing through a resistor. When the first PMOS tube and the first NMOS tube of the third stage structure generate dead zone voltage in the second stage structure, the first PMOS tube and the first NMOS tube both work in a subthreshold region so that the annular amplifier stably amplifies input signals, and the input signals amplified by the annular amplifier are output from the drains of the first PMOS tube and the first NMOS tube.

And the second PMOS tube and the second NMOS tube of the third stage structure are respectively connected with a preset common-mode voltage V _CM from respective grid electrodes, so that the second PMOS tube and the second NMOS tube are both operated in a linear region, the second PMOS tube and the second NMOS tube are respectively equivalent to a resistor, the voltage difference between the source electrode of the first PMOS tube and the source electrode of the first NMOS tube is restrained through the voltage division effect of the resistor, namely the voltage difference between the source electrode of the first PMOS tube and the source electrode of the first NMOS tube is restrained, and when the dead zone voltage generated by the second stage structure is changed under the influence of PVT, the first PMOS tube and the first NMOS tube still keep operating in a subthreshold region, so that the first stage structure can stably amplify an input signal.

The PVT stable annular amplifier of the embodiment is the same as the traditional resistor self-bias annular amplifier, dead zone voltage is generated through resistor self-bias, external bias is not needed, a bias circuit is omitted, the circuit structure is as simple as possible, and design difficulty is reduced. But compared with the traditional resistor self-bias type annular amplifier, the structure of the third stage is changed, a PMOS tube and an NMOS tube are connected to serve as variable resistors, a high-threshold tube is not used, the PVT stable type annular amplifier is realized, and meanwhile, the bandwidth of the annular amplifier is not lost.

The PMOS tube and the NMOS tube with the newly added third-stage structure can be biased in the subthreshold region through smaller dead zone voltage by inhibiting the power supply voltage seen by the two output MOS tubes of the third-stage structure, namely the first PMOS tube and the first NMOS tube, so that the variable range of the dead zone voltage is enlarged, and the two MOS tubes are only required to be connected and biased in the linear region technically, so that the design difficulty is small. Meanwhile, the PVT resistance of the annular amplifier is optimized under the condition that a high threshold value tube is not used, the impedance of the high threshold value tube in a subthreshold region is larger than that of a common MOS tube, the output impedance of the annular amplifier is increased, so that a main pole is too close to a low frequency region, the bandwidth of the annular amplifier is limited, the amplification speed of the annular amplifier for small signals is limited, in the embodiment, only a conventional MOS tube is used, and therefore, the output impedance of the annular amplifier is moderate, and the main pole is offset to generate enough phase margin to enable the amplifier to enter a steady state, and the bandwidth of the annular amplifier is not limited.

In one example, the substrates of the first NMOS transistor, the second NMOS transistor, the third NMOS transistor, and the fourth NMOS transistor of the present embodiment are all grounded, and the substrates of the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, and the fourth PMOS transistor are all connected to a power supply, so that a body effect is generated between the first PMOS transistor and the second NMOS transistor, and the threshold voltages of the first PMOS transistor and the second NMOS transistor are increased, thereby further optimizing the PVT characteristics of the ring amplifier.

In one example, the PVT stabilized ring amplifier of the present embodiment can be applied to a single-ended switched-capacitor amplifying circuit, or to a pseudo-differential amplifier circuit constructed using two identical switched-capacitor amplifier circuits, or to a differential circuit.

The following describes how the PVT stabilized ring amplifier of the present embodiment achieves the above effects in detail:

In actual integrated circuit production and use, there is a PVT influence, which causes the actual working state of the circuit to be different from the simulation result, and for the ring amplifier, the dead zone voltage is greatly influenced due to the PVT influence, so that the working state of the whole amplifier is influenced, and therefore, the ring amplifier is a PVT sensitive amplifier structure. The influence of PVT on the annular amplifier is mainly characterized in that firstly, the influence of resistor manufacturing errors is realized, in the actual circuit manufacturing process, the absolute value of the resistor tends to have larger errors, and even the absolute value of the resistor can reach +/-20%, so that the dead zone voltage can have +/-20% errors even if only the resistor manufacturing errors are considered. Secondly, under the influence of different temperatures, power supply voltages and process angles, the current flowing through the MOS tube also has larger change, so that dead zone voltage generated by the resistor is influenced. The invention aims to expand the variable range of the dead zone voltage of the annular amplifier, so that the annular amplifier can be stabilized and enter a normal working state under the condition of larger change of the dead zone voltage.

Taking the conventional resistive self-bias ring amplifier shown in fig. 1 as an example, if no dead-zone voltage is introduced, the ring amplifier is always in an oscillation state and cannot amplify a signal because enough phase margin cannot be generated, so that signal splitting is required to be completed through the dead-zone voltage, and the NMOS tube and the PMOS tube of the last stage (i.e., the third stage) are in subthreshold regions, so that the dominant pole moves to a low frequency position, the ring amplifier shown in fig. 3 changes the baud diagram when transitioning from oscillation to steady state, the abscissa in the diagram is frequency, the ordinate is the ratio of output to input, ω _ρ1 is the dominant pole, w _ρ2 is the minor pole, the red dotted line is the baud diagram when no dead-zone voltage is introduced, and the baud diagram when dead-zone voltage is introduced when the orange solid line is obviously introduced, and the dead-zone voltage is caused to move left by introducing the dead-zone voltage, so that enough phase margin is generated, and the oscillator becomes the amplifier to stably amplify the signal.

As shown in fig. 1, in the resistive self-bias structure, the dead-zone voltage V _OS may be expressed as V _OS＝I₂ ×r, where I2 is the leakage current of the second stage and R is the resistance value.

Obviously, if two MOS transistors of the last stage are required to work in the subthreshold region, V _THN+|V_THP|+V_OS is larger than or equal to VDD, wherein V _THN and V _THP are threshold voltages of the NMOS transistor and the PMOS transistor of the third stage.

In order to meet the above formula, the dead zone voltage is required to be as large as possible, but at the same time, the dead zone voltage is too large, which causes the NMOS tube and the PMOS tube of the second stage to enter the linear region, so that the whole annular amplifier cannot generate enough open-loop gain accurate amplified signals, therefore, the dead zone voltage also needs to meet the requirement that V _DSATN+|V_DSATP|+V_OS is less than or equal to VDD, wherein V _DSATN and V _DSATP are the saturated voltages of the NMOS tube and the PMOS tube of the second stage respectively.

The range of values from which the dead zone voltage can be obtained is as follows:

VDD-V_THN-|V_THP|≤V_OS≤VDD-V_DSATN-|V_DSATP|。

As long as the dead zone voltage is within the range, the annular amplifier can normally work, but the dead zone voltage tends to have larger fluctuation due to PVT change and resistance manufacturing error influence in the practical application process, and in addition, the upper limit and the lower limit of the dead zone voltage value can be changed due to the change of the MOS tube threshold voltage caused by the process angle, so that the stability of the annular amplifier in the practical application process is difficult to ensure.

To solve such problems to a certain extent, the conventional resistor self-bias ring amplifier generally adopts a high-threshold tube at the last stage, thereby increasing the value range of dead zone voltage and increasing the PVT stability of the structure. However, since the high threshold tube belongs to a special process, the conventional process is not supported, and in addition, when the high threshold tube works in a subthreshold region, the impedance is too large, so that the dominant pole moves to a low frequency too much, and the bandwidth of the ring amplifier is limited.

Compared with the traditional resistor self-bias type annular amplifier, as shown in fig. 2, the main modification of the embodiment is that an NMOS tube and a PMOS tube which work in a linear region are connected into a third stage, and the grid electrodes of the NMOS tube and the PMOS tube are connected into a common mode voltage V _CM to serve as resistors, so that a certain voltage drop is generated, the power supply voltage seen by an output tube of the third stage is restrained, in the structure, when the third stage is stable, two output MOS tubes need to enter a subthreshold region, and the dead zone voltage needs to be satisfied:

V _THN+|V_THP|+V_OS+V_DSN+|V_DSP |is equal to or greater than VDD, where V _DSN and V _DSP are the source-drain voltages of M5 and M8.

In this embodiment, the dead zone voltage is expressed as:

VDD-V_THN-|V_THP|-V_DSN-|V_DSP|≤V_OS≤VDD-V_DSATN-|V_DSATP|。

It can be seen that the range of dead zone voltage is also enlarged, and the sizes of V _DSN and V _DSP can be adjusted by adjusting the size of the MOS transistor, in addition, because the body effect exists in M6 and M7 in fig. 2, the threshold voltages of the MOS transistor and the M7 are slightly raised relative to the normal value, so that the PVT characteristics of the ring amplifier are further optimized.

Based on the PVT stabilized ring amplifier of this embodiment, the present invention further provides a residual amplifier circuit for verifying PVT characteristics of the PVT stabilized ring amplifier, where the specific structure of the residual amplifier circuit is as shown in fig. 4, and the residual amplifier circuit further includes a sampling capacitor C ₀, an offset storage switch C _c, a feedback capacitor C _f, a load capacitor C _L, a reset state stabilizing capacitor C ₁, and a plurality of clock control switches, where the circuit controls the circuit to switch the working states through two non-overlapping clocks, so as to realize normal amplification of signals.

The working state of the circuit is controlled by two non-overlapping clocks. In the sampling state, all switches controlled by the RESET clock (RST clock) signal are opened, and all switches controlled by the amplified clock (AMPLIFICATION clock, AMP clock) signal are closed, one end of C ₀ is connected with the common mode voltage V _CM, the other end is connected with the input signal V _in, and the input signal is collected. In addition, when sampling, the input offset of the annular amplifier is needed to be obtained by connecting the annular amplifier end to end and stored by the offset storage capacitor C _c, and the input offset of the annular amplifier can be eliminated in an amplifying state by the method, so that the annular amplifier can be biased at an optimal working point. In addition, when the ring amplifier is reset, the ring amplifier is in an end-to-end connection state, and at the moment, the ring amplifier works in a unit gain feedback state, and the feedback factor is approximately equal to 1, so that an additional stabilizing capacitor C1 is needed to be connected in the resetting process, and the ring amplifier is used for stabilizing the state of the ring amplifier in the resetting process, so that the ring amplifier is not in an oscillation state in the resetting process, and cannot work normally. In the amplified state, all switches controlled by the RST clock signal are turned on, the amplifier circuit begins to amplify the sampled signal, and the input signal is superimposed on the common mode signal, and the output signal is also superimposed on the common mode signal, for example, 910mV for the input signal, and 10mV for the common mode voltage of 900mV for the actually amplified signal.

In the invention, a TSMC180nm technology is adopted for verification, the voltage is 1.8V, the input signal is 940mV, namely a small signal of 40mV, the sampling capacitance C ₀ is 1.6pF, the feedback capacitance C _f is 200fF, the load capacitance C _L is 320fF, the stable capacitance C ₁ is 80pF, and the offset storage capacitance C _c is 300fF, namely the input signal is amplified by 8 times. Fig. 6 shows the amplification curves of the PVT stabilized ring amplifier according to the present invention in different PVT cases, wherein (a) is an amplification curve in the case where the actual resistance value of the resistor is 80% of the design value, (b) is an amplification curve in the case where the actual resistance value of the resistor is 100% of the design value, and (c) is an amplification curve in the case where the actual resistance value of the resistor is 120% of the design value. In contrast, fig. 5 shows the amplification curves of the conventional resistor self-biased ring amplifier under different PVT conditions, where (a) is the amplification curve when the actual resistance value of the resistor is 80% of the design value, (b) is the amplification curve when the actual resistance value of the resistor is 100% of the design value, and (c) is the amplification curve when the actual resistance value of the resistor is 120% of the design value.

By observing the corresponding amplification curves, it is obvious that the working states of the conventional resistive self-bias ring amplifier have larger differences under different process angles, as shown in fig. 5, under the condition of the same resistance and resistance value, the second-stage current is too small, the dead zone voltage becomes small, so that the ring amplifier needs longer time to oscillate to enter a stable state, and under the condition of the FF process angle (FsatNFET Corner & FastPFET Corner), the dead zone voltage is too large, and the amplification precision of the ring amplifier is reduced. If the resistor manufacturing error is not considered, a ring amplifier with relatively good performance can be designed, as shown in fig. 5 (b), but if the resistor manufacturing error is considered in practical situations, the dead zone voltage will change more, especially under the SS process angle in fig. 5 (a) and the FF process angle in fig. 5 (c), respectively, corresponding to the situation that the dead zone voltage is minimum and maximum, and the ring amplifier in both situations cannot amplify the signal correctly. The ring amplifier circuit provided by the invention can obviously improve the superposition ratio of the amplifying curves under different process angles, particularly the performances under SS and FF process angles are obviously optimized, the amplifying curves of the SS process angle in fig. 6 (a) and the FF amplifying curve in fig. 6 (c) are relatively obvious, and the ring amplifier can still realize the correct amplification of signals under the two worst conditions, thereby ensuring the stability of PVT characteristics of the structure. In addition, the overall amplification time can be seen to be somewhat reduced compared with the conventional structure.

In this embodiment, a conventional ring amplifier (i.e., a standard ring amplifier) is improved, and a PMOS tube and an NMOS tube (i.e., a second PMOS tube and a second NMOS tube) are added in a third stage structure of the standard ring amplifier, so that the newly added PMOS tube and NMOS tube each operate in a linear region, and each function as a resistor, so that a voltage division effect of the resistor can be used to suppress a power supply voltage (i.e., a voltage difference between a source of the first PMOS tube and a source of the first NMOS tube) seen by an original PMOS tube and NMOS tube (i.e., a first PMOS tube and a first NMOS tube) in the third stage structure, so that even when a dead zone voltage generated by a second stage structure of the ring amplifier changes under the influence of PVT, the first PMOS tube and the first NMOS tube can still operate in a subthreshold region, thereby generating a larger output impedance, so that an output main pole shifts left, and the ring amplifier has a sufficient phase margin, and finally the amplifier can stably amplify signals. In the embodiment, the variable range of the dead zone voltage can be enlarged only through two MOS tubes, so that the annular amplifier has PVT resistance, cannot be interfered by the PVT resistance, and has small design difficulty.

Another embodiment of the invention relates to an electronic device comprising a PVT stabilized ring amplifier as described in the previous embodiments.

The present embodiment is an apparatus embodiment corresponding to the above-described amplifier embodiment, and may be implemented in cooperation with the above-described amplifier embodiment. The related technical details and technical effects mentioned in the above embodiments are still valid in this embodiment, and in order to reduce repetition, they are not described here again. Accordingly, the related technical details mentioned in the present embodiment can also be applied to the above-described embodiments.

It will be understood by those of ordinary skill in the art that the foregoing embodiments are specific embodiments in which the invention may be practiced and that various changes in form and details may be made therein without departing from the spirit and scope of the embodiments of the invention. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the embodiments of the invention, and the scope of the embodiments of the invention should be assessed accordingly to that of the appended claims.

Claims (8)

1. The PVT stable annular amplifier is characterized in that a first stage structure and a second stage structure of the PVT stable annular amplifier are a first stage structure and a second stage structure of a standard annular amplifier, and a third stage structure of the PVT stable annular amplifier comprises a first PMOS tube, a first NMOS tube, a second PMOS tube and a second NMOS tube, wherein a source electrode of the first PMOS tube is connected with a drain electrode of the second PMOS tube, a source electrode of the first NMOS tube is connected with a drain electrode of the second NMOS tube, a source electrode of the second PMOS tube is connected with a power supply, and a source electrode of the second NMOS tube is grounded;

The first PMOS tube and the first NMOS tube work in a subthreshold region when dead zone voltage is generated in a second-stage structure of the annular amplifier, so that the PVT stable annular amplifier stably amplifies an input signal;

The second PMOS tube and the second NMOS tube are respectively connected into a preset common-mode voltage from respective grid electrodes, so that the second PMOS tube and the second NMOS tube both work in a linear region, the second PMOS tube and the second NMOS tube are respectively equivalent to a resistor, and the voltage difference between the source electrode of the first PMOS tube and the source electrode of the first NMOS tube is restrained through the voltage division effect of the resistor, so that when the dead zone voltage generated by the second-stage structure changes under the influence of PVT, the first PMOS tube and the first NMOS tube still keep working in a subthreshold region.

2. The PVT stabilized ring amplifier of claim 1, wherein the first stage structure of the PVT stabilized ring amplifier comprises a third PMOS transistor and a third NMOS transistor, a gate of the third PMOS transistor is connected to a gate of the third NMOS transistor, a drain of the third PMOS transistor is connected to a drain of the third NMOS transistor, a source of the third PMOS transistor is connected to a power supply, and a source of the third NMOS transistor is grounded;

The second-stage structure of the PVT stable annular amplifier comprises a fourth PMOS tube, a fourth NMOS tube and a resistor, wherein the grid electrode of the fourth PMOS tube is connected with the grid electrode of the fourth NMOS tube, and the drain electrode of the fourth PMOS tube and the drain electrode of the fourth NMOS tube are respectively connected with two ends of the resistor.

3. The PVT stabilized ring amplifier of claim 2, wherein the input signal of the PVT stabilized ring amplifier is input from gates of the third PMOS and third NMOS transistors, and the amplified input signal is output from drains of the first PMOS and first NMOS transistors of the PVT stabilized ring amplifier.

4. The PVT stable ring amplifier of claim 3 wherein the third PMOS and third NMOS both operate in a saturation region to amplify an input signal;

The fourth PMOS tube and the fourth NMOS tube also work in a saturation region, and dead zone voltage is obtained through voltage drop generated by current flowing through a resistor.

5. The PVT stabilized ring amplifier of claim 4, wherein the first, second, and third stage structures of the PVT stabilized ring amplifier are directly coupled by the following connections:

the drain electrode of the third PMOS tube is connected with the grid electrode of the fourth PMOS tube, the drain electrode of the third NMOS tube is connected with the grid electrode of the fourth NMOS tube, the drain electrode of the fourth PMOS tube is connected with the grid electrode of the first PMOS tube, and the drain electrode of the fourth NMOS tube is connected with the grid electrode of the first NMOS tube.

6. The PVT stabilized ring amplifier of claim 5, wherein the substrates of the first NMOS transistor, the second NMOS transistor, the third NMOS transistor, and the fourth NMOS transistor are all grounded, and the substrates of the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, and the fourth PMOS transistor are all connected to a power supply, so that a body effect is generated between the first PMOS transistor and the second NMOS transistor, and the threshold voltages of the first PMOS transistor and the second NMOS transistor are increased.

7. PVT stabilized ring amplifier according to claim 1, wherein the PVT stabilized ring amplifier is applied in a single ended switched capacitor amplifier circuit, or in a pseudo-differential amplifier circuit constructed using two identical switched capacitor amplifier circuits, or in a differential circuit.

8. An electronic device comprising the PVT-stabilized ring amplifier of any one of claims 1 to 7.