CN1216467C - Interface method between control layer and physical layer of orthogonal frequency-division multiplexing communication system - Google Patents

Abstract

A method for implementing the interface between the control layer and the physical layer of an OFDM communication system, using registers and dual-port random access memory as a data buffer unit, and performing chip selection and generating write addresses through the write control unit to complete the process of writing data into the buffer work, the data sorting unit performs the necessary sorting and encapsulation of the data in the cache, the read control unit performs chip selection and generates a read address to read the data, and read and write at the same time, the rate coordination problem is undertaken by the rate limit unit, the write rate If it is too fast, the write rate will be reduced through the signal line, and if the write rate is too slow, an interrupt signal will be sent to the control layer. At the same time, the control feedback unit is used for control and status feedback. The method of the invention has stable performance, is easy to implement in a system, and occupies less resources, and can be used in an OFDM wireless local area network system and other various systems based on OFDM.

Description

Implementation method of control layer and physical layer interface of OFDM communication system

Technical field:

The invention relates to a method for realizing the interface between the media access control layer (MAC layer) and the physical layer (PHY layer) of an orthogonal frequency division multiplexing communication system, which is a data framing realization method based on the IEEE802. The field of digital communication technology.

Background technique:

The IEEE802.11a standard was proposed in 1999, and it is an extension of the 802.11 standard. Since its encoding and mapping method can reach up to 64QAM, and its modulation method is Orthogonal Frequency Division Multiplexing (OFDM), it can provide a rate of up to 54Mbps. At the same time, it works in the 5GHz frequency band, which avoids some inevitable conflicts in the unregulated frequency band of 2.4GHz. So it is a very promising WLAN standard.

But in the system based on 802.11a, the data transmission rate is very high, and there are many difficulties in hardware implementation. The main content of the interface design between the media access control layer and the physical layer is the framing of data, including two tasks of rate matching and data reordering. The physical layer requires that the time interval between symbols is fixed during the transmission of a frame, and the data rate provided by the media access control layer to generate symbols is uncertain, so it is necessary to interface between the media access control layer and the physical layer The rate matching function is provided in . The purpose of data reordering is to reorder the data provided by the media access control layer according to the requirements of the physical layer.

In essence, the above two tasks are data reorganization problems, the former is time-based, while the latter is space-based. The traditional processing method is: put the data obtained from the media access control layer into the cache, and then take out the data in the order and rate required by the physical layer. However, when the data transmission rate of the media access control layer is too large or too small, there is no way to work normally with this traditional caching mechanism, because the cache space is limited, if the media access control layer writes data to the cache If the speed of the media access control layer is too fast, the effective data that has not been read will be overwritten, resulting in data loss; Reading data that has not been updated, the data is invalid.

Invention content:

The purpose of the present invention is to aim at the above technical difficulties, to provide a new OFDM communication system media access control layer and physical layer interface implementation method, which can still work normally when the transmission rate of the control layer is very large or small. Work, stable performance and simple implementation.

In the technical scheme of the present invention, a dual-port random access memory RAM (store data) and several registers (store parameters) are used as the data cache unit, and a write control unit is used to select the cache (select the random access memory or A certain register) and generate a write address (the address of the random access memory), complete the work of writing data into the cache, and the data sorting unit performs necessary sorting and packaging on the data in the cache to make it conform to the frame format. The sorted data is selected and the read address is generated, and a stable data stream that meets the specified rate of the parameter is output; the rate limit unit processes the illegal rate by comparing the read and write pointers, and the write rate is too fast to reduce the write rate through the signal line. If the write rate is too slow, an interrupt signal is sent to the control layer. In addition, a control feedback unit is used for control and state feedback.

Concrete operation of the present invention is carried out as follows:

1. Generate the chip select signal for write operation and the address of the cache

The data of the media access control layer is sent to the write control unit, which generates a chip select signal for the cache (dual-port random access memory and several registers) and generates the address of the random access memory. When the chip selection selects the dual-port random access memory, the enable terminal of the write address generator is set to a high level, and it is counted by one to continuously generate new addresses.

2. Data is stored in the cache

The data is stored in the data cache unit, and the data cache unit includes two vector registers and a dual-port random access memory. The register stores parameters from the media access control layer, and the dual-port RAM stores data. Each chip selection selects a register or random access memory, which can be read or written. Among them, the dual-port random access memory is recycled, and reading and writing are performed on two ports at the same time.

3. Sort the data

The data cache unit should lead to the data sorting unit, and the data sorting unit adjusts the order of the data in the cache. Usually, it is only necessary to adjust the order of the parameters, that is, logically combine the parameters in the vector register to obtain the signaling part of the frame. For the convenience of reading, the adjusted data is packaged into three independent data units, and the chip select lines can gate them separately.

4. Generate chip select signal for read operation and cache address

The sorted and encapsulated data meets the data format required by the physical layer and is waiting to be read out. Read chip selection and read address generation are completed by the read control unit. Chip selection objects include dual-port random access memory and three newly generated data units. When the random memory is selected by the chip selection, the write address generator enable terminal of the random memory is set to a high level, and it is counted by one to continuously generate a new random memory read address.

5. Check whether the rate is legal and deal with illegal rates

The rate limiting unit checks whether the rate is legal and handles illegal rates. In order to ensure the reliability of data transmission, a certain depth of unread data must always be kept in the cache. This depth can neither be too large nor too small. If the depth is too small, it is likely to cause data interruption due to insufficient data reserves. When the depth is too large, since the total capacity of the cache is limited (it is a fixed value), the writable space is too small, and it is easy to cause the result of overwriting valid data (that is, unread data). Judging whether the rate of the media access control layer is legal by comparing the read and write addresses: if the write address is less than A units ahead of the read address, an interrupt signal INT0 is sent to the media access control layer to interrupt the transmission process of this frame; if the write address When the leading read address is more than B units, the write enable end of the media access control layer is set to a low level to allow it to wait. Among them, A and B are parameters, which can be adjusted according to actual needs.

6. Control and feedback

Use the control feedback unit for control and status feedback. The media access control layer writes the control information into the control register to control the physical layer; the physical layer writes the state quantity into the status register, from which the media access control layer can read to obtain the state information of the physical layer.

The present invention divides the whole interface into 6 units, and the interaction among them constitutes the whole interface part. The data in the media access control layer is written into the data cache unit under the control of the write control unit, the data sorting unit performs necessary sorting on the data in the cache, and then the read control unit reads out the sorted data to form a The rate of the data flow is controlled by the rate limiting unit to avoid the situation that the rate is too fast or too slow. The control feedback unit enhances the interface function and makes it more operable.

Realize this interface in Field Programmable Gate Array (FPGA), the result shows, the present invention is applicable to the various rate data of media access control layer, performance is stable, and resource occupation is little, is to realize OFDM communication system media access control layer and physical A more desirable approach to layer interfaces.

The present invention can be used in OFDM wireless local area network system, and can also be applied in terrestrial digital video broadcasting (DVB-T), code division multiple access-orthogonal frequency division multiplexing communication system (CDMA-OFDM), frequency division multiple access communication system (OFDMA) and other OFDM-based systems.

Description of drawings:

Figure 1 is a block diagram of the interface between the media access control layer and the physical layer.

As shown in Figure 1, after the data flows out from the media access control layer, it passes through the write control unit, data cache unit, data sorting unit and read control unit in sequence to form the data format required by the physical layer. At the same time, the rate limiting unit is connected with the write control unit and the read control unit, and controls the read and write operations of the buffer as a whole to ensure the stability of the data flow. The control feedback unit performs control and state feedback. Among them, the control feedback unit is composed of several control registers and status registers. The bidirectional lines in the figure indicate that the work performed by this unit is interactive. The MAC layer controls the physical layer by writing control information into the control registers in this unit. The physical layer writes the state quantity into the state register in this unit, and the media access control layer can obtain the state information of the physical layer.

Figure 2 shows the structure of the data sorting unit.

As shown in Figure 2, when the chip selection selects the vector register, that is, when its enable terminal is high, write data to this register. Since the readable signal is always at a high level, the data in the register is always in a readable state. According to the structural requirements of the frame, the signaling part of the frame is obtained through logical combination of the parameters stored in the vector register. In order to facilitate reading, the combined data is packaged into three independent data units, which can be selected separately with the chip selection signal. The capacity of each independent data unit in the figure is 8 bits, and the capacity of the vector register is 16 bits.

Figure 3 shows the relationship between the read and write addresses of the dual-port random access memory.

Comparing the write address with the read address, the write address must be at least A unit ahead of the read address, otherwise it indicates that the write is too slow, and an interrupt signal INT0 is sent to the media access control layer to interrupt the transmission process of this frame, as shown in Figure 3.a At the same time, the write address is at most B units ahead of the read address, otherwise it indicates that the write is too fast, and the write enable terminal of the media access control layer is set to low level to let it wait, as shown in Figure 3.b. (The shaded part is the random memory area that has written new data but has not been read)

Detailed ways:

The technical solution of the present invention will be further described below through specific examples.

An embodiment is a wireless LAN IEEE802.11a system to which the present invention is applied. The capacity of dual-port RAM used in this example is 16K. In this example, the write address is at least 1K units ahead of the read address, that is, A=1K, and the write address is at most B units ahead of the read address, that is, B=1K. The concrete steps that the present invention is applied to IEEE802.11a system are:

1. Generate the chip select signal for write operation and the address of the cache

Decode the signal given by the media access control layer to obtain the buffered chip select signal. If the chip selection selects the dual-port random access memory, the enabling terminal of the random access memory write address generator is set to a high level, and it adds one count to generate a new random access memory write address. If the register is selected by the chip select, the enable terminal of the write address generator is set to low level, and the address generator does not need to work.

2. Data is stored in the cache

In this example, the data cache unit consists of two vector registers and a dual-port random access memory. The vector register stores the parameters from the media access control layer, which is stored once at the beginning of each frame; the random access memory stores data, which needs to be recycled. When the chip selection selects a vector register or random access memory, it can be read or written.

3. Data sorting and encapsulation

The signaling part of the physical layer frame needs to be processed by processing the parameters transmitted by the media access control layer. These parameters are stored in vector registers, so it is only necessary to logically combine the data in the vector registers, and then package the combined data to form three independent data units, which can be strobed and read separately.

4. Generate chip select signal for read operation and cache address

The data units that can be read include dual-port random access memory and three units after packaging, so four chip select signals must be generated to select them respectively. When the random access memory is selected by the chip selection, the enable terminal of the write address generator is set to a high level, and it is counted by one to generate a new read address. When the random access memory is not selected by the chip selection, the enable terminal of the write address generator is set to low level, and the address generator does not work.

5. Check whether the rate is legal and deal with illegal rates

Compare the read and write addresses to determine whether the rate of the media access control layer is legal: Case 1) The difference between the write address and the read address is less than A, indicating that the depth of unread data is too small, and it can be considered that the data transmission rate of the media access control layer cannot meet the requirements. Physical layer requirements, so an interrupt signal INT0 is issued. Case 2) The difference between the write address and the read address is greater than B, indicating that the depth of unread data is too large, and the available space of the cache is too small. Set the write enable terminal of the media access control layer to low level, and suspend writing to the cache Data, waiting for the data in the cache to be read to avoid overwriting unread data. Situation 3) The difference between the write address and the read address is between A and B, indicating that everything is normal, and both reading and writing are carried out normally.

6. Control and feedback

By writing the control information of the media access control layer into the control register, the physical layer can be controlled through this register; at the same time, the state quantity of the physical layer is written into the status register for access by the media access control layer. The control feedback unit better realizes the intercommunication between the media access control layer and the physical layer, and enhances the interface function.

Through the actual hardware implementation, this interface implementation method can not only handle various data rates of the media access control layer, and has stable performance, but also is relatively simple to implement and occupies less system resources. An ideal method for an interface.

Claims (1)

1, a kind of OFDM communication system control layer and physical layer interface realization method, it is characterized in that comprising the steps: 1) Send the data of the media access control layer to the write control unit, and generate the chip select signal and the address of the cache for the write operation; 2) Data is stored in the data cache unit, two vector registers store parameters from the media access control layer, a dual-port random access memory stores data, and each chip selection selects a register or random access memory, and reads or writes it, wherein , Dual-port random access memory recycling, reading and writing are performed on two ports at the same time; 3) The data sequence in the cache is adjusted by the data sorting unit, the parameters in the vector register are logically combined to obtain the signaling part of the frame, and the adjusted data is packaged into three independent data units; 4) The reading control unit completes the chip selection and the generation of the read address. The chip selection object has a dual-port random access memory and three newly generated data units. When the chip selection selects the random access memory, the write address generator of the random access memory is used Set the enable end of the write address generator to a high level, let it add a count, and continuously generate new random memory read addresses; The generator doesn't work; 5) The rate limiting unit checks whether the rate is legal, handles illegal rates, and always maintains a certain depth of unread data in the cache, and judges whether the rate of the media access control layer is legal by comparing the read and write addresses: if the write address is ahead of the read address When it is less than A units, send an interrupt signal INTO to the media access control layer to interrupt the transmission process of this frame. If the write address leads the read address by more than B units, set the write enable end of the media access control layer to low power Ping, let it wait, if the difference between the write address and the read address is between A and B, it means that everything is normal, and the reading and writing are going on normally, and the parameters of A and B are adjusted according to actual needs; 6) Carry out control and state feedback with the control feedback unit, the media access control layer writes the control information in the control register to control the physical layer; the physical layer writes the state quantity in the state register, and the media access control layer reads the following Get status information of the physical layer.

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