CN1492273A - Liquid crystal display array substrate and manufacturing method thereof - Google Patents

Abstract

An LCD array substrate, comprising: a plurality of gate lines arranged in a first direction; a plurality of data lines arranged in a second direction and intersecting with the plurality of gate lines; formed in the overlapping area of the gate lines and the data lines a semiconductor layer in the gate line extending from the overlapping region with a predetermined length on the gate line; a drain electrode which is spaced from the overlapping region of the gate line and the data line by a certain distance and is partially in contact with the semiconductor layer, the drain electrode having an end portion extending from the semiconductor layer and the gate line; and a pair of pixel electrodes disposed on opposite sides of the gate line and electrically connected to the drain.

Description

Liquid crystal display array substrate and manufacturing method thereof

technical field

The present invention relates to a liquid crystal display (LCD), and more particularly to an LCD array substrate in which a thin film transistor region is provided on a central side portion of a unit pixel, and a data line and a gate line instead of a source and a method for manufacturing the same. Pole and Grid.

Background technique

In general, liquid crystal displays operate by optical anisotropy and polarization of the liquid crystal material therein. Since the liquid crystal material includes liquid crystal molecules each having a thin and long structure, the liquid crystal material has directionality according to the alignment of the liquid crystal molecules. Therefore, the alignment direction of liquid crystal molecules can be controlled by applying an external electric field to the liquid crystal. As the alignment direction of liquid crystal molecules is changed by applying an electric field, light polarization caused by optical anisotropy of the liquid crystal material is modulated to display image information.

Liquid crystal materials can be classified into positive (+) liquid crystals with positive dielectric anisotropy and negative (-) liquid crystals with negative dielectric anisotropy, depending on their electrical properties. Liquid crystal molecules with positive dielectric anisotropy are aligned such that their long axes are parallel to the direction of the applied electric field, while liquid crystal molecules with negative dielectric anisotropy are aligned such that their long axes are parallel to the direction of the applied electric field. Direction is vertical.

Currently, an active matrix LCD in which thin film transistors and pixel electrodes connected to the thin film transistors are arranged in a matrix structure is widely used due to its high resolution and excellent reproducibility of moving images. Next, the structure of a liquid crystal panel, which is a main element of an LCD, will be reviewed.

FIG. 1 is a partially exploded perspective view of a conventional LCD. Referring to FIG. 1 , a general color LCD includes an upper substrate 5 and a lower substrate 22 . The upper substrate 5 includes a black matrix 6 , a color filter 7 including red (R), green (G) and blue (B) sub-color filters, and a transparent common electrode 18 formed on the color filter 7 . The lower substrate 22 includes a pixel region (P), a pixel electrode 17 formed on the pixel region (P), and an array interconnection line including switching elements (T). The liquid crystal layer 15 is interposed between the upper substrate 5 and the lower substrate 22, as described above.

The lower substrate 22 is called an "array substrate". On the lower substrate 22, a plurality of thin film transistors as switching elements are arranged in a matrix structure, and gate lines 13 and data lines 15 are formed to cross the plurality of thin film transistors. The pixel region (P) is determined by the gate line 13 and the data line 15 crossing the gate line 13 . The pixel electrode 17 formed on the pixel region (P) is composed of a transparent conductive material such as indium tin oxide (ITO) having excellent light transmittance. The LCD 11 configured as above displays an image when the liquid crystal molecules of the liquid crystal layer 14 on the pixel electrodes 17 are aligned according to the signal voltage applied from the thin film transistor to control the amount of light passing through the liquid crystal layer 14.

Moreover, the LCD array substrate 22 constituted above is formed by a deposition process, a photolithography process (hereinafter referred to as "optical process"), an etching process, and the like. Optical processes utilize the principle that when a photoresist ('PR') is exposed to light, a chemical reaction occurs to change the properties of the PR. In the optical process, light is selectively irradiated onto PR through a mask of a desired pattern, thereby forming the same pattern as the mask. The optical process includes a PR coating step on which a photoresist corresponding to a general image film is coated, an exposure step of selectively irradiating light onto the PR using a mask, and a development step of removing the exposed portion of the PR to form a pattern.

FIG. 2 is a partially enlarged plan view of a pixel of a conventional LCD array substrate. Referring to FIG. 2 , a pixel region (P) is determined by a pair of gate lines 13 and a pair of data lines 15 crossing the pair of gate lines 13 . Where the data line 15 and the gate line 13 intersect, a thin film transistor (T) having a gate 31 , a source 33 and a drain 35 is formed. The source 33 and the drain 35 are separated from each other by a predetermined interval on the gate 31 , and the active channel (semiconductor layer) 37 a is exposed between the source 33 and the drain 35 .

When the scan pulse is applied to the gate 31 of the thin film transistor (T) and the voltage of the gate 31 rises, the thin film transistor (T) is turned on. At this time, if a liquid crystal driving voltage is applied to the liquid crystal material from the data line 13 through the drain region and the source region of the thin film transistor (T), the pixel capacitance including the liquid crystal capacitance and the storage capacitance changes. By repeating the above operations, the voltage corresponding to the video signal per frame time is repeatedly applied to the pixel capacitances on the front surface of the LCD panel. Finally, if any pixel is turned on by the thin film transistor, the turned on pixel passes light from the lower light source.

3A-3D are plan views and cross-sectional views schematically showing the process flow of manufacturing the LCD array substrate of FIG. 2. In FIGS. 3A-3D, the cross-sectional views are taken along line I-I' of FIG. Here, although FIG. 3 shows that the array substrate is formed through a process using four masks, the array substrate may be formed through a process using five masks. If the array substrate is formed through a process using five masks, the semiconductor layer 37 may not be formed under the data line 15 .

FIG. 3A corresponds to a first masking step in which a metal such as copper or the like is deposited and patterned to form gate lines 13 and gates 31 . Next, a gate insulating film 32 and an amorphous semiconductor (silicon) layer 37', an impurity-doped amorphous semiconductor (silicon) layer 36' and a conductive metal layer 33 are deposited on the substrate on which the gate lines 13 and the like are formed. '.

3B corresponds to the second mask step, in which the conductive metal layer 33' is patterned to form the data line 15 crossing the gate line 13, the source electrode 33 protrudingly formed from the data line 15 with a predetermined area, and the source electrode 33 The drain electrodes 35 are separated at predetermined intervals. Next, use the patterned metal layer as an etching stop layer to etch the exposed impurity-doped amorphous silicon 36', so that the amorphous silicon layer 37' is exposed between the data line and the drain.

FIG. 3C corresponds to a third masking step in which a passivation layer 41 of electrically insulating material is formed on the substrate on which the data lines 15 etc. are formed. The passivation layer 41 is patterned to form a drain contact hole 43 for the drain electrode 35 . A portion of the passivation layer 41 is removed on the pixel region (P) except the upper portions of the gate 31 , the source 33 and the drain 35 , the gate line 13 , and the data line 15 . When the passivation layer 41 is patterned, the semiconductor layer 37 and the gate insulating film 32 under the passivation layer 41 are simultaneously patterned. Thus, under the patterned passivation layer 41 , the semiconductor layer 37 is etched into the same pattern as the passivation layer 41 .

FIG. 3D corresponds to a fourth masking step in which the pixel electrode 17 is formed in contact with the drain electrode 35 through the drain contact hole 43 .

In this way, a conventional array substrate is formed through the foregoing process, and the screen size of the array substrate is larger than that of an exposure mask used in an optical process. Then, during the exposure step, the screen of the array substrate is divided into a plurality of shots and exposed repeatedly, and this repetitive process is further popularized with the mass production of large-sized LCDs in recent years. However, the precision limitation of the exposure equipment degrades the image quality of the LCD due to stitch failures generated by misalignment between exposure areas.

Also, in the case of forming a data line defining a pixel region intersecting a gate line, a source electrode, and a drain electrode separated from the source electrode by a certain interval by patterning the conductive metal layer by using the mask step of FIG. 3B , exposure equipment, etc. Accuracy limitations cause the mask to not exactly conform to predetermined specifications and thus deviate somewhat from the exact position. As a result, a coverage defect in which a gate electrode and a source/drain electrode irregularly overlap each pixel region is generated, and thus image quality of the LCD is degraded.

Referring to FIG. 4, the phenomenon of image quality degradation in the LCD is explained in detail. 4A-4C illustrate seam/overlap defects according to the contact area of source/drain to gate.

In FIGS. 4A-4C , seam defects are problems that arise when the alignment between exposure areas on the same layer is not constant, and overlay defects are problems that arise due to misalignment of masks between different layers. However, since the results of seam defects are the same as those of misalignment defects, their descriptions refer to the same FIGS. 4B and 4C .

FIG. 4A is a plan view and a cross-sectional view of a thin film transistor region in which a stitch/overlay defect is not generated.

Referring to FIG. 4A , parasitic capacitances C _gs and C _gd are generated due to overlapping regions between the gate 31 and the source 33 and between the gate 31 and the drain 35 . When the thin film transistor is turned on, the parasitic capacitance changes the voltage of the liquid crystal by ΔV, thus creating a voltage difference between the initially applied voltage and the voltage applied to the liquid crystal. ΔV is approximately represented by Equation 1 below.

$\mathrm{<span\; class="notranslate">\; \&Delta;V</span>}<span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; gd</span>}}}{{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; gd</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; LC</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; ST</span>}}}\mathrm{<span\; class="notranslate">\; \&Delta;</span>}{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; g</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; )</span>$

where C _gd is the parasitic capacitance, C _LC is the liquid crystal capacitance, C _ST is the storage capacitance, and ΔV _g is the voltage difference between the gate voltage V _gh and V _gl for the on and off states.

Thus, due to the voltage difference ΔV, a phenomenon in which an image is disadvantageously darkened and brightened, ie, flicker, occurs when an image is displayed. Flicker can be overcome by shifting the common voltage by ΔV from the center of the data signal voltage so as to remove the direct current (dc) component while operating the LCD. In other words, if the ΔV generated in each pixel is constant, flicker can be overcome by shifting the common voltage by a constant amount.

As shown in FIG. 4A, this problem can be solved if the parasitic capacitance with respect to each thin film transistor area is constant in a plurality of pixels. However, flicker cannot be overcome by shifting the common voltage (V _com ) by a constant amount if the parasitic capacitances in multiple pixels are not constant with respect to the individual TFT regions due to seam and/or overlap defects.

4B and 4C are plan and cross-sectional views of thin film transistor regions where seam/overlap defects occur.

If a seam defect (i.e. misalignment between exposed regions) or an overlap defect (i.e. mask misalignment between different layers) occurs, the overlapping area between the gate 31 and the source 33 will be in contact with the gate 31 A difference is made between the overlapping area between the drain electrode 35 and the drain electrode 35 . A difference between the parasitic capacitances C _gs and C _gd is thus generated. In other words, as shown in FIG. 4B , in a state where the side of the drain 35 is misaligned toward the side of the source 33 , the capacitance C _gd between the gate and the drain becomes large. Meanwhile, as shown in FIG. 4C , in a state where the side of the source 33 is misaligned toward the drain 35 , the capacitance C _gd between the gate and the drain becomes small.

As described above, if a difference between the parasitic capacitances is generated in each pixel area, which means that the capacitance C _gd changes by ΔV, the value of ΔV becomes not constant, so only by shifting the common voltage (V _com ) as in the conventional technique A constant amount is unlikely to solve the flickering problem. Accordingly, array substrates manufactured by conventional manufacturing methods of LCD array substrates have difficulty in overcoming the image imbalance problem of LCDs generated by seam and/or overlapping defects.

Contents of the invention

Accordingly, the present invention relates to an LCD array substrate and method of manufacturing the same, which substantially solve one or more problems due to limitations and disadvantages of the related art.

An object of the present invention is to provide an LCD array substrate and a method of manufacturing the same, which remove changes in parasitic capacitance due to overlap and seam defects.

The additional features and advantages of the present invention are partly embodied in the following description, and others will be obvious to those of ordinary skill in the art who read the following description, or can be learned from the practice of the present invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described herein, an LCD array substrate includes: a plurality of gate lines disposed in a first direction; A plurality of data lines intersected by lines; a semiconductor layer formed in an overlapping region of the gate line and the data line, the semiconductor layer extending from the overlapping region on the gate line by a predetermined length; an overlapping region with the gate line and the data line a drain electrode spaced at a distance and partially in contact with the semiconductor layer, the drain electrode having an end portion extending out of the semiconductor layer and the gate line; and a pair of electrodes disposed on opposite sides of the gate line and electrically connected to the drain electrode pixel electrodes.

In another aspect, the LCD array substrate includes: a plurality of gate lines arranged in a first direction; a plurality of data lines arranged in a second direction to cross the plurality of gate lines; a semiconductor layer of an overlapping region from which the semiconductor layer extends at a predetermined length on the gate line; a drain electrode which is spaced from the overlapping region of the gate line and the data line by a certain distance and is partially in contact with the semiconductor layer, the drain The electrode has an end extending beyond a side of the gate line; and a pixel electrode electrically connected to the end of the drain and overlapping at least a portion of the gate line.

In another aspect of the present invention, the manufacturing method of the LCD array substrate includes the following steps: forming a plurality of gate lines on the substrate; sequentially forming a gate insulating film and a semiconductor layer on the substrate on which the gate lines are formed; A plurality of data lines and a drain are formed on the semiconductor layer; a passivation layer is formed on the entire surface of the substrate having the data lines, drains, gate lines and the semiconductor layer; the passivation layer is formed on both ends of the drain forming a contact hole; and forming a pair of pixel electrodes electrically connected to the drain through the contact hole.

In another aspect of the present invention, the manufacturing method of the LCD array substrate includes the following steps: forming a plurality of gate lines on the substrate; sequentially forming a gate insulating film and a semiconductor layer on the substrate on which the gate lines are formed; A plurality of data lines and a drain are formed on the layer; a passivation layer is formed on the entire surface of the substrate having the data lines, drains, gate lines and semiconductor layers; in the passivation layer formed on both ends of the drain forming a contact hole; and forming a pixel electrode electrically connected to the drain through the contact hole and overlapping with a corresponding one of the gate lines.

It is to be understood that both the foregoing general description and the following detailed description of the invention are schematic and explanatory and are intended to provide further explanation of the invention as claimed.

Description of drawings

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention.

In the attached picture:

FIG. 1 is a partially exploded perspective view of a conventional liquid crystal display;

2 is a partially enlarged plan view of a pixel of a conventional LCD array substrate;

3A-3D are plan and sectional views representing a process flow for manufacturing the LCD array substrate of FIG. 2, wherein the sectional view is taken along line I-I' of FIG. 2;

4A-4C show plan views and cross-sectional views of seam/overlap defects according to the contact area of the source/drain in contact with the gate in the LCD array substrate of FIG. 2, wherein the cross-sectional view is along the line II' intercepted;

5 is a partially enlarged plan view of an LCD array substrate according to an example embodiment of the present invention;

6A-6E is a plan view and a sectional view schematically showing a process flow for obtaining the LCD array substrate of FIG. 5, wherein the sectional view is taken along the lines II-II' and III-III' of FIG. 5;

7 is a partially enlarged plan view of an LCD array substrate according to another exemplary embodiment of the present invention;

8A-8E are schematic plan views and cross-sectional views for obtaining the process flow of the LCD array substrate of FIG. 7, wherein the cross-sectional views are taken along the lines V-V' and VI-VI' of FIG. 7;

9A and 9B are cross-sectional views taken along line V-V' of FIG. 5 and line VII-VII' of FIG. 7; and

10A-10E show enlarged plan views of thin film transistor structures that overcome seam/overlap defects according to the present invention.

Detailed ways

Preferred embodiments of the present invention will be described in detail below with reference to the examples in the accompanying drawings.

FIG. 5 is a partially enlarged plan view of an LCD array substrate according to an example embodiment of the present invention.

Referring to FIG. 5, the unit pixel of the LCD array substrate is formed in the upper area and the lower area defined by a pair of data lines 15, 15' adjacent to each other in the horizontal direction and a gate line 13 crossing the data line pair 15, 15'. in the pixel area (P). A thin film transistor (T) is formed at the intersection of the data line 15 and the gate line 13 . Here, the upper region and the lower region represent regions designed in such a way that the pixel region (P) defined by the gate line 13 is not separated from the gate line 13 adjacent to the gate line 13 in the upward and downward directions. The other pixel region P' defined by ' overlaps.

Also, the thin film transistor (T) includes the gate line 13 and the data line 15 at intersections, and the drain electrode 35 separated from the data line 15 by a predetermined distance. Between the gate line 13 and the data line 15 at the intersection, a semiconductor layer 37 is formed. The semiconductor layer 37 protrudes above the gate line 13 by a predetermined amount. The gate line 13 and the data line 15 at the intersection directly serve as the gate and source of the thin film transistor. Also, the data line 15 and the drain electrode 35 are separated from each other by a predetermined interval on the semiconductor layer 37 formed on the gate line 13 . A portion of the semiconductor layer 37 exposed between the data line 15 and the drain electrode 35 is used as a channel 37 a for transmitting a signal from the data line 15 to the drain electrode 35 .

The drain electrode 35 is formed such that both ends thereof are located outside the semiconductor layer 37 and connected to the pair of pixel electrodes 17, 17', respectively. The pixel electrode pair 17, 17' is formed in the above-mentioned pixel region (P) at predetermined intervals from the gate line 13 and the data lines 15, 15' adjacent to each other in the horizontal direction, thereby forming a single unit pixel.

In more detail, as the scan pulse is applied to the gate line 13 of the thin film transistor (T) and the thin film transistor (T) is turned on, the liquid crystal drive voltage is transferred from the data through the channel 37a and the drain electrode 35 of the thin film transistor (T). The line 13 is applied over the pair of pixel electrodes 17, 17'. At this time, the same liquid crystal driving voltage is applied to the pixel electrode pair 17, 17' respectively, which means that the pixel electrode pair 17, 17' is used as a unit pixel.

6A-6E are schematic plan views and cross-sectional views showing the manufacturing process of the LCD array substrate of FIG. 5 . Here, the sectional view is taken along line II-II' and line III-III' of FIG. 5 . FIG. 6 shows that the array substrate is formed by a process using five masks, but the array substrate can be formed by a process using four masks. Moreover, FIG. 6 shows that the semiconductor layer 37 is formed under the data lines 15, 15'. However, the semiconductor layer 37 may not be formed under the data lines 15, 15' where the thin film transistor (T) is not formed.

FIG. 6A corresponds to a first masking step in which a metal such as copper or the like is deposited and patterned to form gate lines 13 . Next, a gate insulating film 32 and an amorphous silicon layer 37' are formed on the substrate on which the gate line 13 is formed.

Figure 6B corresponds to the second masking step in which the amorphous silicon layer 37' is patterned to form active lines, i.e. the semiconductor layer 37. At this time, the semiconductor layer 37 is patterned so as to be formed at intersections of the gate lines 13 and the data lines 15 to be formed in a later step. Here, as shown in FIG. 6B , the semiconductor layer 37 protrudes above the gate line 13 by a predetermined amount in the vertical direction. Alternatively, the semiconductor layer 37 may be formed in the area under the data line 15 and in the patterning area in order to overcome the defect of decreased adhesion when the data line 15 is composed of molybdenum (Mo) or the like. Accordingly, in the case where the data line 15 is composed of chromium (Cr) or the like which does not cause problems in adhesiveness, it is not necessary to pattern the semiconductor layer 37 with respect to the area under the data line 15 . However, FIG. 6B shows that the semiconductor layer 37 is patterned with respect to the area below the data line 15. Referring to FIG.

FIG. 6C corresponds to a third mask step, in which a conductive metal layer is formed on the semiconductor layer 37 and patterned to form the data line 15 and the drain electrode 35 . The data line 15 is formed to vertically cross the gate line 13 , and the drain is formed to be spaced apart from the data line 15 by a certain distance. A semiconductor layer 37 is formed at intersections of the gate line 13 and the data line 15 and under the drain electrode 35 . Also, the semiconductor layer 37 exposed between the data line 15 and the drain forms a channel for transmitting a signal from the data line to the drain 35 . Furthermore, when the drain electrode 35 is formed, both ends of the drain electrode 35 are patterned so as not to overlap the semiconductor layer 37 but to be located outside the semiconductor layer 37 .

If a process using four masks is performed, the steps using the second mask and the third mask shown in FIGS. 6B and 6C can be combined into a single step. This method is carried out through the following steps: depositing a gate insulating film, an amorphous silicon layer, an amorphous silicon layer doped with impurities, and a conductive metal layer, and patterning the conductive metal layer to form a data line crossing the gate line , and the drain electrode separated from the data line at a certain interval, and use the patterned metal layer as an etching stop layer to etch the exposed amorphous silicon layer doped with impurities, so that the amorphous silicon layer is between the data line and the drain electrode exposed. According to the process of the above four masks, the semiconductor layer 37 is formed under the data lines 15, 15'.

Next, FIG. 6D corresponds to a fourth masking step in which a passivation layer 41 of an insulating material is formed on the substrate on which the data line 15 and the drain electrode 35 are formed. The passivation layer 41 is patterned to form a drain contact hole 43 at both ends of the drain electrode 35, and except for the upper portions of the gate line 13 and the drain electrode 35 and the upper portions of the gate line 13 and the data line 15, the pixel region is removed. Passivation layer 41 on (P).

Finally, Fig. 6E corresponds to a fifth masking step in which the pair of pixel electrodes 17, 17' contacting the drain 35 through the contact holes 43 at both ends of the drain 35 are formed. At this time, the pixel electrode pairs 17, 17' are respectively formed to be separated from the gate line 13 passing through the pixel region (P) by predetermined intervals in upward and downward directions, respectively, to form a single pixel with respect to the pixel region (P). In other words, the same liquid crystal driving voltage is applied to the pixel electrode pair 17, 17'.

FIG. 7 is a partially enlarged plan view of an LCD array substrate according to another example embodiment of the present invention.

Comparing the structure of FIG. 7 with the structure of FIG. 5, the difference can be seen. For example, the pixel electrode pair 17, 17' shown in FIG. 5 is formed at a certain interval from the gate line 13 passing through the pixel region (P), and the pixel electrode 19 in FIG. 7 is not separated from the gate line 13, but is overlapped by a predetermined portion with the upper portion of the gate line 13 passing through the pixel region (P). Thereby, a storage capacitor per unit pixel can be formed.

Referring to FIG. 7, the unit pixel of the LCD array substrate is formed in the upper area and the lower area defined by a pair of data lines 15, 15' adjacent to each other in the horizontal direction and a gate line 13 crossing the data line pair 15, 15'. in the pixel area (P). Thin film transistors (T) are formed at intersections of the data lines 15 and the gate lines 13 . Here, the upper area and the lower area represent areas designed in such a way that the pixel area (P) defined by the gate line 13 is not separated from the gate line 13 adjacent to the gate line 13 in the upward and downward directions. The other pixel region P' defined by ' overlaps.

The thin film transistor (T) includes the gate line 13 and the data line 15 at intersections, and the drain electrode 35 separated from the data line 15 by a predetermined distance. A semiconductor layer 37 is formed between the gate line 13 and the data line 15 at the intersection. The semiconductor layer 37 protrudes above the gate line 37 by a predetermined amount. Also, the data line 15 and the drain electrode 35 are separated from each other by a predetermined interval on the semiconductor layer 37 formed on the gate line 13 . The semiconductor layer 37 having an exposed portion between the data line 15 and the drain electrode 35 serves as a channel 37a for transmitting a signal from the data line 15 to the drain electrode. In addition, the drain electrode 35 is formed such that both ends thereof are located outside the semiconductor layer 37 and are electrically connected to both edge portions of the pixel electrode 19 , respectively.

The pixel electrode 19 is formed such that a predetermined portion overlaps the gate line 13 but does not overlap the semiconductor layer 37 in the pixel region (P). The gate line 13 and the pixel electrode 19 overlapping each other at a predetermined portion within the pixel region (P) serve as first and second electrodes of the storage capacitor.

Capacitances of storage capacitors formed in individual unit pixels are controllable in consideration of the size of unit pixel regions arranged in a matrix structure. In the case of the present invention, by controlling the overlapping area between the gate line 13 and the pixel electrode 19 in the pixel region (P), the capacitance of the storage capacitor can be properly controlled.

8A-8E are plan views and cross-sectional views schematically showing the manufacturing process of the LCD array substrate of FIG. 7, wherein the cross-sectional views are taken along lines V-V' and VI-VI' of FIG. Here, the array substrate is formed through a process using five masks, but the array substrate may be formed through a process using four masks. Also, FIG. 8 shows that the semiconductor layer 37 is formed under the data lines 15, 15'. However, the semiconductor layer 37 may not be formed under the data lines 15, 15' where the thin film transistor (T) is not formed. In addition, the process steps shown in FIGS. 8A-8E are similar to those shown in FIGS. 6A-6E , except that the pixel electrode pair ( FIG. 6E ) is not formed separately but the upper part of the pixel electrode 19 ( FIG. 8E ) and the gate line passing through the pixel region. to overlap outside of the predetermined portion. Accordingly, descriptions of FIGS. 8A-8E are omitted.

The differences between the exemplary embodiments shown in FIGS. 5 and 7 respectively are described in detail below with reference to FIG. 9 . 9A and 9B are sectional views taken along line IV-IV' of FIG. 5 and line VII-VII' of FIG. 7 . From Figures 9A and 9B, it is easy to distinguish the difference between these two embodiments.

For example, FIG. 9A shows a gate line 13 passing through the pixel region (P) and a pair of pixel electrodes 17, 17 spaced from the gate line 13 in the upward and downward directions in the exemplary embodiment shown in FIG. 'Section diagram. Since the pixel electrode pair 17, 17' connected to both ends of the drain receiving a signal from the data line is separated with respect to each unit pixel and receives the same signal, they form one signal pixel. For this reason, although one of the two ends of the drain is disconnected, the point defect can be overcome because the other end is still connected.

Next, FIG. 9B shows the pixel electrode 19 formed to overlap a part of the gate line 13 passing through the pixel region (P) but not to overlap the semiconductor layer in the pixel region (P) in an alternative embodiment of FIG. 7 sectional view. Here, the gate line 13 and the pixel electrode 19 overlapping each other by a predetermined amount within the pixel region (P) serve as the first and second electrodes of the storage capacitor. Accordingly, by changing the overlapping area between the gate line 13 and the pixel electrode 19 within the pixel region (P), the capacitance of the storage capacitor can be controlled.

In FIGS. 9A and 9B, numerals 32 and 41 denote a gate insulating film and a passivation film, respectively. The above-described embodiments are formed by the processes of FIGS. 6 and 8 . Then, according to the array substrate of the present invention manufactured through the above process, it is possible to overcome seam and/or overlapping defects caused by precision limitations in photolithography exposure equipment. Seam and overlap defects are described below.

Generally, the display size of the array substrate is larger than the size of the exposure mask used in the photolithography process. Therefore, during the exposing step, the entire area of the array substrate is divided into a plurality of exposure regions and exposed repeatedly. In this case, since the exposure equipment has its precision limitations, misalignment between exposure areas may occur. The phenomenon of seams indicates this misalignment. Also, when data lines and source/drain electrodes are formed on gate lines, the mask does not fit perfectly but is deformed due to precision limitations of exposure equipment and the like. Therefore, the gate line and the drain may overlap irregularly in each pixel area. This is called an overlap defect.

If a seam or overlap defect occurs in the prior art, it will make the parasitic capacitance of each pixel region different, and thus the image quality of the LCD will be degraded. However, according to the structure of an embodiment of the present invention, even if seam and/or overlap defects occur (for example, even if exposure regions and/or masks are misaligned), since parasitic There is sufficient margin for capacitance change, so this defect can be overcome.

In each of the embodiments shown in FIGS. 5 and 7, since the enlarged thin film transistor regions coincide with each other and the aforementioned seam and/or overlap defects are problematic in the thin film transistor regions, reference will be made to FIGS. 10A-10E through this chapter. The enlarged thin film transistor region in an embodiment of the invention introduces a process for overcoming seam and/or overlap defects. 10A-10E illustrate techniques for overcoming seam and/or overlap defects by thin film transistor structures according to the present invention.

Here, the seam defect is a problem generated when the alignment between exposure regions on the same layer is not constant, and the overlap defect is a problem generated due to misalignment of masks between different layers. However, since the result (such as the phenomenon that the parasitic capacitance in the thin film transistor region changes in each pixel region) is the same, it will not be described separately.

Fig. 10A is a plan view and a cross-sectional view (taken along line VIII-VIII') of a thin film transistor region.

Referring to FIG. 10A, since there is an overlapping portion (S1) between the gate line 13 and the data line 15 and an overlapping portion (S2) between the gate line 15 and the drain 35, a parasitic capacitance (C _gd ) is generated. When the thin film transistor is turned on, the parasitic capacitance changes the liquid crystal voltage by ΔV, thus generating a voltage difference between the initial applied voltage and the liquid crystal applied voltage. ΔV can be approximated by the following Equation 2:

$\mathrm{<span\; class="notranslate">\; \&Delta;V</span>}<span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; gd</span>}}}{{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; gd</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; LC</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; ST</span>}}}\mathrm{<span\; class="notranslate">\; \&Delta;</span>}{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; g</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; )</span>$

Among them, C _gd is the parasitic capacitance, C _LC is the liquid crystal capacitance, C _ST is the storage capacitance, ΔV _g is the voltage difference between the gate voltage V _gh and V _gl in the on and off states.

Thus, due to the voltage difference ΔV, a phenomenon in which an image becomes dark and bright unfavorably (ie, flicker) occurs. Flicker can be overcome by shifting the common voltage (Vcom) by ΔV from the center of the data signal voltage to eliminate the direct current (dc) component when the LCD is operating. In other words, in the case where ΔV generated in each pixel is constant, flicker can be overcome by adjusting the common voltage by a constant amount.

Thus, as shown in FIG. 10A, if the parasitic capacitance with respect to each thin film transistor area is constant in a plurality of pixels, this problem can be solved. However, if the parasitic capacitances in pixels are not constant with respect to the respective TFT regions due to seam and/or overlap defects, the flicker problem cannot be overcome by adjusting the common voltage (Vcom) by a constant amount. To overcome this problem, a sufficient margin is formed in the thin film transistor area of each pixel area so that the parasitic capacitance does not change even if seam and/or overlap defects, ie exposure area and/or mask misalignment, occur.

Figures 10B and 10C show that due to seam and/or overlapping defects, the data lines 15 and drain electrodes 35 are patterned to be biased to the left and right, and Figures 10D and 10E show that due to seam and/or overlapping defects, the data lines 15 and drain 35 are patterned to be biased in both upward and downward directions.

10B-10E, according to the structure of the present invention, although seams and/or overlapping defects and exposure regions and/or mask misalignment occur, between the gate line 13 and the data line 15 and between the gate line 13 and the drain There is also no difference in the overlapping region ( S1 , S2 ) between the poles 35 , so there is also no difference in parasitic capacitance with respect to the pixel region (P).

According to the thin film transistor structure of the present invention, since there is no difference in parasitic capacitance of each pixel region due to seam and/or overlap defects, the flicker problem can be overcome only by adjusting the common voltage (Vcom) by a constant amount. Therefore, the array substrate manufactured by the manufacturing process of the LCD array substrate can solve the problem of LCD image imbalance caused by seams and/or overlapping defects.

As described above, in the LCD array substrate and its manufacturing method according to the present invention, the difference in parasitic capacitance that may be formed in the thin film transistor region of each pixel due to seam and/or overlap defects is eliminated, so that it can be compared with LCD dot-related image quality defects are minimized. Furthermore, seam and/or overlap defects can be overcome without any additional process when manufacturing large-sized LCDs.

Various modifications and changes to the present invention will occur to those skilled in the art. Thus, it is intended that the present invention cover the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.

Claims (22)

1, a kind of LCD array base palte comprises:

A plurality of select liness in the first direction setting;

At second direction setting and a plurality of data lines of intersecting with a plurality of select liness;

Be formed on the semiconductor layer in the overlapping region of select lines and data line, this semiconductor layer extends at select lines with predetermined length from the overlapping region;

With the drain electrode spaced apart and that partly contact with semiconductor layer of the overlapping region of select lines and data line, this drain electrode has the end of extending semiconductor layer and select lines; With

Be arranged on the relative both sides of select lines and a pair of pixel electrode that is electrically connected with drain electrode.

2, according to the LCD array base palte of claim 1, wherein pixel electrode is to being connected to the end of drain electrode.

3, according to the LCD array base palte of claim 1, wherein each pixel electrode is formed in the pixel region that a select lines adjacent areas of intersecting is limited by a pair of adjacent data line and with this data line.

4, according to the LCD array base palte of claim 1, wherein pixel electrode separates predetermined space to forming respectively with select lines by pixel region, and pixel electrode is to limiting a unit pixel with respect to pixel region.

5, according to the LCD array base palte of claim 1, wherein the semiconductor layer between data line and the drain electrode partly limits a raceway groove, and this raceway groove allows from data line to the drain electrode transmission signals according to the signal from select lines.

6, a kind of LCD array base palte comprises:

A plurality of select liness in the first direction setting;

At second direction setting and a plurality of data lines of intersecting with a plurality of select liness;

Be formed on the semiconductor layer in the overlapping region of select lines and data line, this semiconductor layer extends at select lines with predetermined length from the overlapping region;

With the drain electrode spaced apart and that partly contact with semiconductor layer of the overlapping region of select lines and data line, this drain electrode has the end of extending the select lines sidepiece; With

Be electrically connected and the pixel electrode overlapping with the end of drain electrode with at least a portion of select lines.

7. according to the LCD array base palte of claim 6, wherein the semiconductor layer zone is extended in Lou Ji end.

8, according to the LCD array base palte of claim 6, wherein pixel region limits a select lines adjacent areas of intersecting by a pair of adjacent data line and with this data line.

9, according to the LCD array base palte of claim 6, wherein pixel region is restricted to the select lines by pixel region overlappingly, makes pixel electrode extend on the select lines but do not extend on semiconductor layer.

10, according to the LCD array base palte of claim 6, wherein select lines and pixel electrode are used as first and second electrodes of a holding capacitor.

11, according to the LCD array base palte of claim 6, wherein the semiconductor layer between data line and the drain electrode partly limits a raceway groove, and this raceway groove allows from data line to the drain electrode transmission signals according to the signal from select lines.

12, a kind of manufacture method of LCD array base palte may further comprise the steps:

On substrate, form a plurality of select liness;

Formed thereon on the substrate of select lines and formed gate insulating film and semiconductor layer successively;

On semiconductor layer, form a plurality of data lines and a drain electrode;

On the whole surface of substrate, form passivation layer with data line, drain electrode, select lines and semiconductor layer;

In the passivation layer that is formed on the drain electrode two ends, form contact hole; With

The a pair of pixel electrode that formation is electrically connected with drain electrode by contact hole.

13, according to the manufacture method of claim 12, wherein semiconductor layer is patterned so that be formed in the overlapping region of select lines and data line, and further extends at select lines from data line.

14, according to the manufacture method of claim 12, wherein pixel electrode is to being formed in the pixel region that a select lines adjacent areas of intersecting is limited by a pair of adjacent data line and with this data line.

15, according to the manufacture method of claim 14, wherein pixel electrode is separating predetermined space on the direction up and down to forming with select lines by pixel region.

16, according to the manufacture method of claim 12, wherein semiconductor layer is extended at Lou Ji two ends.

17, a kind of manufacture method of LCD array base palte may further comprise the steps:

On substrate, form a plurality of select liness;

Formed thereon on the substrate of select lines and formed gate insulating film and semiconductor layer successively;

On semiconductor layer, form a plurality of data lines and a drain electrode;

On the whole surface of substrate, form passivation layer with data line, drain electrode, select lines and semiconductor layer;

In the passivation layer that is formed on the drain electrode two ends, form contact hole; With

Formation be electrically connected with drain electrode by contact hole and with a pixel electrode that corresponding select lines is overlapping.

18, according to the manufacture method of claim 17, wherein semiconductor layer is patterned so that be formed in the overlapping region of select lines and data line, and further extends on the select lines from data line.

19, according to the manufacture method of claim 17, wherein pixel region limits a select lines adjacent areas of intersecting by a pair of adjacent data line and with this data line.

20, according to the manufacture method of claim 17, wherein pixel region is restricted to the select lines by pixel region overlappingly, makes pixel electrode extend on the select lines but does not extend on the semiconductor layer.

21, according to the manufacture method of claim 17, wherein semiconductor layer is extended at Lou Ji two ends.

22. according to the LCD array base palte of claim 1, wherein a plurality of data lines and a plurality of select lines are basically with crossing at right angle.

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