CN1412947A - Buffer with adjustable duty cycle and method of operation thereof - Google Patents
Buffer with adjustable duty cycle and method of operation thereof Download PDFInfo
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- CN1412947A CN1412947A CN 02148108 CN02148108A CN1412947A CN 1412947 A CN1412947 A CN 1412947A CN 02148108 CN02148108 CN 02148108 CN 02148108 A CN02148108 A CN 02148108A CN 1412947 A CN1412947 A CN 1412947A
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- 230000005669 field effect Effects 0.000 claims description 183
- 230000000630 rising effect Effects 0.000 abstract description 6
- 230000000737 periodic effect Effects 0.000 description 4
- 230000000295 complement effect Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
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Abstract
The invention relates to a buffer capable of adjusting a working period and an operation method thereof, wherein the method is implemented on inverters connected in series, each inverter is provided with a plurality of charging current paths and a plurality of discharging current paths, and when the working period of a clock signal is reduced, the number of the discharging current paths and the number of the charging current paths are reduced; the invention is applied to a buffer which is used for providing an adjustable working period on a clock path circuit, and is used for dynamically adjusting the time of a rising edge and a falling edge of a clock signal so as to dynamically change the working period of the clock signal.
Description
Technical field
The present invention relates to a kind of buffer and method of operation thereof, and particularly relevant for a kind of buffer and method of operation thereof that is used among the clock path circuit in order to the control clock signal work period.
Background technology
Generally speaking, in present IC design system, all need the different clock signal of a kind of even multiple frequency (Clock Signal), and the action sequence of integrated circuit (IC) system and operating rate, all depend on clock signal on this integrated circuit (IC) system as benchmark, when the clock signal frequency on the Circuits System is fast more, usually also relative fast more of the operating rate of this Circuits System, therefore, the quality of clock signal is considerable for Circuits System, if the quality of clock signal is not given special heed to and handled on the Circuits System, the lighter may make the speed of Circuits System to increase, and weight person will cause the entire circuit system to move.
And during the clock signal quality in the processing integrated circuit system, except the accuracy of clock signal frequency will be paid special attention to, also have the work period (Duty Cycle) of clock signal also to need to give special heed to.Be illustrated in figure 1 as a desirable clock signal 100, the work period of this ideal clock signal is 50 percent, and also the high levle of real-time clock (RTC) signal is identical with the time that low level is occurred.
Along with the integrated circuit (IC) design development of technology, circuit design becomes and becomes increasingly complex, Circuits System is also in the past more and more huger, the clock signal that is used on the integrated circuit (IC) system then must be by pluralize branch of difference, this clock signal is sent to each position that needs on the integrated circuit (IC) system, as the foundation of this Circuits System action sequence.But the difference circuit of these a plurality of clock signals is as if being simple quilt and connecing difference, and the energy of clock signal itself also will be divided equally, and the clock signal after this may lead to divergence can't promote the situation of next stage circuit.Therefore, as shown in Figure 2, in known method, can add a plurality of buffers 205 on circuit usually becomes clock path (Clock Tree), can effectively strengthen fan-out (Fan Out) ability of clock signal.
Be illustrated in figure 3 as the buffer of a known clock path circuit.This buffer is made up of two inverters 300,300 of each inverters are made up of a p type field effect transistor 305 and a n type field effect transistor 310, the one source pole of this p type field effect transistor 305 is connected to power supply 315, one drain electrode end is connected in series the drain electrode end of this n type field effect transistor 310, this node is the output 330 of this inverter 300, the one source pole end of this n type field effect transistor 310 is connected to earth point 320, this p type field effect transistor 305 is connected to each other with the grid of this n type field effect transistor 310, and this node is the input 325 of this inverter.When these inverter 300 input logic meanings are the signal of " 1 ", p type field effect transistor 305 is failure to actuate, n type field effect transistor 310 actions, therefore, it is the signal of " 0 " that output 330 produces a logical meaning, on the contrary, when these inverter 300 input logic meanings were the signal of " 0 ", it was the signal of " 1 " that 330 of outputs produce a logical meaning.
Please refer to Fig. 3, when two inverters, 300 serial connections, form buffer, when input 325 inputs one logical meaning is the signal of " 1 ", producing a logical meaning 335 of outputs also is the signal of " 1 ", opposite, when input 325 inputs one logical meaning was " 0 " signal, producing a logical meaning 335 of outputs also was the signal of " 0 ".In addition, this clock path circuit also can be strengthened its fan out capability by the energy that inverter 300 is provided, and makes this clock signal have the buffer that enough energy promote next stage.
Please refer to Fig. 2, owing to above-mentioned reason, clock signal in the Circuits System must utilize a plurality of buffers 205 with pluralize branch thereby form the clock path circuit of its difference, but these buffers 205 are actually known buffer as shown in Figure 3, it is a CMOS (Complementary Metal Oxide Semiconductor) (Complementary Metal-Oxide-Semiconductor abbreviates CMOS an as) transistor.On the circuit of reality, because the p type field effect transistor in this CMOS is different with the opering characteristic of electric apparatus of n type field effect transistor, and transistorized size difference, add parasitic capacitance (Parasitic Capacitor) or other all effect that clock path circuit itself is produced, in Fig. 2, importing a work period when the input of clock path circuit is 50 percent desirable clock signal 200, after plural time difference, output can't produce an identical desirable clock signal, but produce shown in the 4th figure work period greater than 50 percent clock signal 405 or work period less than 50 percent clock signal 410.
Therefore, in technique known, a desirable clock signal is after through difference repeatedly, and the quality of clock signal will be suffered destruction in a way, this may cause the speed of Circuits System to increase, even will cause the entire circuit system to move normally.
Summary of the invention
The objective of the invention is for the buffer in a kind of adjustable full employment cycle is provided, clock signal is during through the buffer in the adjustable full employment cycle of clock path circuit, then can be by suitable control, and keep its work period and remain 50 percent, make its signal quality be unlikely to variation.
Another object of the present invention is the method for operation for the buffer that a kind of adjustable full employment cycle is provided, in the time of can making clock signal through the buffer in the adjustable full employment cycle of clock path circuit by this method, then can be by suitable control, and keep its work period and remain 50 percent, make its signal quality be unlikely to variation.
Purpose of the present invention can realize by following measure:
The buffer in a kind of adjustable full employment cycle comprises:
One first inverter, this first inverter have a plurality of controlled current flow charge paths and a plurality of controlled current flow discharge paths; And
One second inverter, this second inverter have a plurality of controlled current flow charge paths and a plurality of controlled current flow discharge paths; Wherein this first inverter is connected in series mutually with this second inverter, and this first inverter has at least one controlled current flow charge path and at least one controlled current flow discharge path to move, and this second inverter has at least one controlled current flow charge path and at least one controlled current flow discharge path to move.
These controlled current flow charge paths in the above-mentioned buffer are composed in parallel by a plurality of p type field effect transistors, and the action of bringing in these p type field effect transistors of control out of the ordinary with the grid of these p type field effect transistors be failure to actuate.
These controlled current flow discharge paths in the above-mentioned buffer are composed in parallel by a plurality of n type field effect transistors, and the action of bringing in these n type field effect transistors of control out of the ordinary with the grid of these n type field effect transistors be failure to actuate.
The buffer in a kind of adjustable full employment cycle comprises:
One first inverter, this first inverter is connected to a supply voltage and an earthed voltage respectively via one first p type field effect transistor group and one first n type field effect transistor group; And
One second inverter is serially connected with this first inverter, and this second inverter is connected to this supply voltage and this earthed voltage respectively via one second p type field effect transistor group and one second n type field effect transistor group.
This first p type field effect transistor group and this second p type field effect transistor group are composed in parallel by a plurality of p type field effect transistor group respectively, the gate terminal of these p type field effect transistors in order to the action of controlling those p type field effect transistors be failure to actuate, and at least one p type field effect transistor is arranged in this first p type field effect transistor group and this second p type field effect transistor group respectively for moving.
This first n type field effect transistor group and this second n type field effect transistor group are composed in parallel by a plurality of n type field effect transistor group respectively, the gate terminal of these n type field effect transistors in order to the action of controlling these n type field effect transistors be failure to actuate, and at least one n type field effect transistor is arranged in this first n type field effect transistor group and this second n type field effect transistor group respectively for moving.
Another object of the present invention can realize by following measure:
The method of operation in a kind of adjustable full employment cycle, in order to be implemented on the inverter of serial connection, each this inverter has a plurality of charging current paths and a plurality of discharge current paths, comprises the following steps:
When reducing the work period of a clock signal, optionally increase the action number in these charging current paths of prime inverter, with the action number of these discharge current paths that optionally increase back level inverter; And
When increasing the work period of this clock signal, optionally increase the action number of these discharge current paths of prime inverter, with the action number in those charging current paths that optionally increase back level inverter.
Said method also comprises when reducing the work period of this clock signal, optionally reduces the action number of these discharge current paths of prime inverter, with the action number in these charging current paths of optionally reducing back level inverter.
Said method also comprises when increasing the work period of this clock signal, optionally reduces the action number in these charging current paths of prime inverter, with the action number of these discharge current paths that optionally reduce back level inverter.
The method of operation in a kind of adjustable full employment cycle, in order to be implemented on the inverter of serial connection, each this inverter has a plurality of charging current paths and a plurality of discharge current paths, comprises the following steps;
When reducing the work period of a clock signal, optionally reduce the action number of these discharge current paths of prime inverter, with the action number in these charging current paths of optionally reducing back level inverter; And
When increasing the work period of this clock signal, optionally reduce the action number in these charging current paths of prime inverter, with the action number of these discharge current paths that optionally reduce back level inverter.
Description of drawings
Fig. 1 is the clock signal of a work period 50 percent;
Fig. 2 is a kind of clock path circuit;
Fig. 3 is a known buffer;
Fig. 4 be a work period greater than 50 percent clock signal and a work period less than 50 percent clock signal;
Fig. 5 is the circuit diagram that a programmable is adjusted the buffer of clock signal work period; And
But Fig. 6 is the buffer with the formed adjustable full employment cycle of program inverter of serial connection.
Embodiment
Because known buffer can cause clock signal to have problems on quality, make clock signal can't keep its work period and be fixed as 50 percent, in view of this, the invention provides the buffer and the method for operation thereof in a kind of adjustable full employment cycle, be used in the clock path circuit, the clock signal of feasible this clock path circuit of input, can have the identical work period with the clock signal of output, and can keep the voltage level of clock signal, make clock signal after, still have the circuit that certain voltage level promotes next stage through a plurality of differences path.Below be illustrated as one embodiment of the invention, basically, but this kind is used in the buffer in adjustable full employment cycle to be made up of two program inverter serial connections as shown in Figure 5, please refer to Fig. 5, this circuit is made up of p type field effect transistor group 500, p type field effect transistor group 502, n type field effect transistor group 510, n type field effect transistor group 512 and one first inverter 505.
P type field effect transistor group 500 comprises first p type field effect transistor 515, second p type field effect transistor 520 and the 3rd p type field effect transistor 525, first p type field effect transistor, 515 gate terminal directly connect earth terminal, the gate terminal of second p type field effect transistor 520 and the 3rd p type field effect transistor 525 is control end, respectively connection control signal A and B.P type field effect transistor group 502 comprises the 4th p type field effect transistor 546, the 5th p type field effect transistor 551 and the 6th p type field effect transistor 555, the gate terminal of the 4th p type field effect transistor 546 directly connects earth terminal, the gate terminal of the 5th p type field effect transistor 551 and the 6th p type field effect transistor 555 is control end, respectively connection control signal C and D.
Wherein, first inverter 505 also is connected to the drain electrode end of these three p type field effect transistors of p type field effect transistor group 500, and the source terminal of three p type field effect transistors is connected to power supply 545.First p type field effect transistor 515 must keep the state of action in this circuit, therefore the grid of first p type field effect transistor 515 is connected to earth terminal 550.In preferred embodiment of the present invention, the channel width of second p type field effect transistor 520 (Channel Width) is greater than the channel width of the 3rd p type field effect transistor 525.
N type field effect transistor group 510 comprises first n type field effect transistor 530, second n type field effect transistor 535 and the 3rd n type field effect transistor 540, the gate terminal of second n type field effect transistor 535 and the 3rd n type field effect transistor 540 is control end, accepts control signal C and D respectively.N type field effect transistor group 512 comprises the 4th n type field effect transistor 560, the 5th n type field effect transistor 565 and the 6th n type field effect transistor 570, the gate terminal of the 5th n type field effect transistor 565 and the 6th n type field effect transistor 570 is control end, accepts control signal A and B respectively.
See also Fig. 5, output E connects the input of second inverter 507, promptly is connected to the p type field effect transistor of second inverter 507 and the grid of n type field effect transistor.The source terminal and the drain electrode end of the 4th p type field effect transistor 546, the 5th p type field effect transistor 551, the 6th p type field effect transistor 555 are connected to the power supply 545 and second inverter 507 respectively.Wherein, the grid of the 4th p type field effect transistor 546 is connected to earth terminal, the grid connection control signal C of the 5th p type field effect transistor 551, the grid connection control signal D of the 6th p type field effect transistor 555.
See also Fig. 5, the source terminal of the 4th n type field effect transistor 560, the 5th n type field effect transistor 565 and the 6th n type field effect transistor 570 and n type field effect transistor and the earth terminal 550 that drain electrode end is connected to second inverter 507 respectively.Wherein, the grid of the 4th n type field effect transistor 560 connects the grid connection control signal A of power supply 545, the five n type field effect transistors 565, the grid connection control signal B of the 6th n type field effect transistor 570.The source electrode of the p type field effect transistor of second inverter 507 connects the drain electrode of n type field effect transistor, and with this output D as second inverter 507
Out
Therefore, adjustment p type field effect transistor 520,525,551 that can be suitable and 555 and the unlatching or the closed condition of n type field effect transistor 535,540,565 and 570, that is change control signal A, B, C, D, A, B, C and D, but and then the length of adjustment program work periodic Control inverter output rising edge charging interval or falling edge discharge time.
According to the above, control signal A, B, C and D are inversion signal with control signal A, B, C and D respectively.
First inverter 505 also is connected to the drain electrode end of three n type field effect transistors of N type field effect transistor group 510, and the source terminal of three n type field effect transistors is connected to earth terminal 550 again.First n type field effect transistor 530 must keep the state of action in circuit, therefore the grid of first n type field effect transistor 530 is connected to power supply 545.Among preferred embodiment of the present invention, the channel width of second n type field effect transistor 535 is greater than the channel width of the 3rd n type field effect transistor 540.
As first inverter, 505 input D
InInput one is converted to rising edge (Rising Edge) signal of " 1 " by " 0 ", and first inverter, 505 output E then export falling edge (Falling Edge) signal that is converted to " 0 " by " 1 ".At this moment, the action that output must discharge, be the action of guaranteeing that output can discharge, therefore, the state that first n type field effect transistor 530 must be held open in this circuit, if second n type field effect transistor 535 or the 3rd n type field effect transistor 540 are the state of unlatching at this moment, the electric current during discharge then can increase, and will make shorten discharge time.Because second n type field effect transistor, 535 channel widths are greater than the 3rd n type field effect transistor 540 channel widths, this discharge time, order was in regular turn from long to short: (I) second n type field effect transistor 535 is not opened and the 3rd n type field effect transistor 540 is not opened; (II) second n type field effect transistor 535 is not opened and 540 unlatchings of the 3rd n type field effect transistor; (III) 535 unlatchings of second n type field effect transistor and the 3rd n type field effect transistor 540 are not opened; (IV) second n type field effect transistor 535 is opened and 540 unlatchings of the 3rd n type field effect transistor.
As first inverter, 505 input D
InInput is converted to the falling edge signal of " 0 " by " 1 ", and first inverter, 505 output E then export the rising edge signal that is converted to " 1 " by " 0 ".At this moment, the action that output E must charge, be the action of guaranteeing that output E can charge, therefore, the state that first p type field effect transistor 515 must be held open in this circuit, if second p type field effect transistor 520 or the 3rd p type field effect transistor 525 are for opening at this moment, electric current during charging then can increase, to make the charging interval shorten, because second p type field effect transistor, 520 channel widths are greater than the 3rd p type field effect transistor 525 channel widths, this charging interval from long to short order be in regular turn: (I) second p type field effect transistor 520 is not opened and the 3rd p type field effect transistor 525 is not opened; (II) second p type field effect transistor 520 is not opened and 525 unlatchings of the 3rd p type field effect transistor; (III) 520 unlatchings of second p type field effect transistor and the 3rd p type field effect transistor 525 are not opened; (IV) second p type field effect transistor 520 is opened and 525 unlatchings of the 3rd p type field effect transistor.
See also Fig. 5, as input D
InThe signal of being imported is 1 o'clock, and behind first inverter 505, the output signal of output E is 0, at this moment, open the n type field effect transistor of first inverter 505, and n type field effect transistor group 510 will be held open, reduce electric current and flow to the required time of earth terminal 550.Because the grid of n type field effect transistor 530 is connected to power supply 545, so be held open state always, if control signal C or D are for enabling (enable) state, then second n type field effect transistor 535 or the 3rd n type field effect transistor 540 will be held open state, will further reduce electric current and flow to the required time of earth terminal 550 via n type field effect transistor group 510.
See also Fig. 5, as input D
InThe signal of being imported is 0 o'clock, and behind first inverter 505, the output signal of output E is 1, at this moment, open the p type field effect transistor of first inverter 505, and p type field effect transistor group 500 will be held open, reduce the required time of the voltage level rising of output.Because the grid of p type field effect transistor 515 is connected to earth terminal, so be held open state always, if control signal A or B are enabled state, then second p type field effect transistor 520 or the 3rd p type field effect transistor 525 will be held open state, will further reduce the required time of the voltage level rising of output E.
See also Fig. 5, when the signal of being exported as output E is 0, output D then
OutOutput signal be 1, then p type field effect transistor group 502 keeps enabling, and reduces output D
OutThe required time that rises of voltage level, if control signal C or D remain on low level, then p type field effect transistor 551 and 555 will be held open, and further reduces D
OutThe required time that rises of voltage level.
See also Fig. 5, when the signal of being exported as output E is 1, output D then
OutOutput signal be 0, then n type field effect transistor group 512 keeps enabling, and reduces output D
OutThe required time that descends of voltage level, if control signal A or B remain on high level, then n type field effect transistor 565 and 570 will be held open, and further reduces D
OutThe required time that descends of voltage level.
Because control signal A, B, C, D are anti-phase in control signal A, B, C, D, so input D
InInput signal is 1 o'clock, and n type field effect transistor group 510 will shorten the low level time of delay of clock signal at output E, and p type field effect transistor 502 will be at output D
OutIncrease the high level time of delay of clock signal.As input D
InInput signal is 0 o'clock, and p type field effect transistor group 500 will shorten the high level time of delay of clock signal at output E, and n type field effect transistor 512 will be at output D
OutIncrease the low level time of delay of clock signal.
Please refer to Fig. 6, this figure is depicted as the buffer in adjustable full employment cycle, but but this circuit by the first program inverter 600 be connected in series with the second program inverter 620 institute form.But when the input of the first program work periodic Control inverter 600 just like Fig. 4 in work period during greater than 50 percent clock signal 405, for making the work period of its convergence 50 percent, but during through the first program inverter 600, must shorten its charging interval, increase its discharge time, but during through the second program work periodic Control inverter 620, must it increase the charging interval, shorten its discharge time.Therefore, field-effect transistor in the first p type field effect transistor group 605 and the second n type field effect transistor group 635 can be suitable action, what the field-effect transistor in the first n type field effect transistor group 615 and the second p type field effect transistor group 625 can be suitable is failure to actuate.
In like manner, but when the input of the first program work periodic Control inverter 600 just like Fig. 4 in work period during less than 50 percent clock signal 410, for making the work period of its convergence 50 percent, but during through the first program inverter 600, must increase its charging interval, shorten its discharge time, but during through the second program inverter 620, its charging interval must be shortened, increase its discharge time, therefore, field-effect transistor in the first p type field effect transistor group 605 and the second n type field effect transistor group 635 can be suitable be failure to actuate the action that the field-effect transistor in the first n type field effect transistor group 615 and the second p type field effect transistor group 625 can be suitable.
Utilize this embodiment, clock signal is during through the buffer in the adjustable full employment cycle of clock path circuit, then can be by suitable control, and keep its work period and remain 50 percent, make its signal quality be unlikely to variation.
Claims (10)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02148108 CN1209875C (en) | 2002-10-30 | 2002-10-30 | Buffer with adjustable duty cycle and method of operation thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02148108 CN1209875C (en) | 2002-10-30 | 2002-10-30 | Buffer with adjustable duty cycle and method of operation thereof |
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| Publication Number | Publication Date |
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| CN1412947A true CN1412947A (en) | 2003-04-23 |
| CN1209875C CN1209875C (en) | 2005-07-06 |
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| CN 02148108 Expired - Lifetime CN1209875C (en) | 2002-10-30 | 2002-10-30 | Buffer with adjustable duty cycle and method of operation thereof |
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| CN111847320B (en) * | 2020-08-26 | 2022-01-28 | 合肥工业大学 | Self-calibration system and method for material handling tool |
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