CN1516463A - System and method for realizing dynamic cascading of lines - Google Patents
System and method for realizing dynamic cascading of lines Download PDFInfo
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- CN1516463A CN1516463A CNA031013406A CN03101340A CN1516463A CN 1516463 A CN1516463 A CN 1516463A CN A031013406 A CNA031013406 A CN A031013406A CN 03101340 A CN03101340 A CN 03101340A CN 1516463 A CN1516463 A CN 1516463A
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Abstract
本发明提供了实现线路动态级联的系统和方法，该系统至少包括第一多点控制单元、第二多点控制单元以及时隙处理装置，该时隙处理装置用于选择空闲时隙、分离空闲时隙、并将空闲时隙组合成数据通道、通过所述数据通道进行数据传输。通过线路使用时隙复用方式为多点控制单元提供多对级联端口，该方法包括：选择线路的时隙中的空闲时隙；分离出空闲时隙；将所述分离出来的时隙分配给级联端口；使用所述级联端口进行数据传输。和现有技术相比有如下优点：通过多点控制单元之间的一路线路为多点控制单元提供多对级联端口；无需添加其它设备，降低了成本；实时为各种速率的级联会议提供级联端口，提高了灵活性；充分利用了宝贵的线路带宽。
The present invention provides a system and method for realizing dynamic cascading of lines. The system at least includes a first multipoint control unit, a second multipoint control unit, and a time slot processing device. The time slot processing device is used for selecting idle time slots, separating idle time slots, and combine the idle time slots into data channels, and perform data transmission through the data channels. Multiple pairs of cascaded ports are provided for the multipoint control unit through the line using the time slot multiplexing method, the method includes: selecting a free time slot in the time slots of the line; separating the free time slots; allocating the separated time slots to the cascade port; use said cascade port for data transfer. Compared with the existing technology, it has the following advantages: provide multiple pairs of cascading ports for the multi-point control unit through one line between the multi-point control units; no need to add other equipment, which reduces the cost; Provide cascading ports to improve flexibility; make full use of valuable line bandwidth.
Description
Technical field
The present invention relates to the multimedia conferencing TV domain, specifically refer to a kind of system and method for realizing the circuit dynamic cascading.
Background technology
In the practical application of video conferencing, between two MCU (Multi-point Control Unit), adopt the user of E1 (a kind of transmission rate is the circuit of 2M) circuit cascade for the overwhelming majority, when needs are held a subtended conference of striding two MCU, how much speed of the subtended conference of no matter holding is, all will take the E1 circuit cascade port of each MCU.But because 32 time slots of E1 circuit can only be unified to use in the prior art, occupied other a time slot all can not use, thereby causes the waste of line resource.
Object lesson when holding the subtended conference of 128K between MCU1 and MCU2, need take the whole 2M bandwidth of E1 as shown in Figure 1a.Bandwidth usage is shown in Fig. 1 b, and therefore the bandwidth of the speed that this means meeting what are all needs to take 2M, has caused great bandwidth waste.
In addition, also have the method for the equipment that extracts at E1 circuit two ends configuration time slot in the prior art, this method is passed through passage technology, take N time slot simultaneously, to obtain the speed of N * 64kbps, this method need be extracted equipment at E1 circuit two ends configuration time slot, has increased operation cost.
Summary of the invention
The invention provides a kind of system and method for realizing the circuit dynamic cascading, to solve the high shortcoming of waste bandwidth, cost that exists in the prior art.
For achieving the above object, the present invention adopts following technical scheme:
Realize the system of circuit dynamic cascading, this system comprises first multipoint control unit, second multipoint control unit at least, also comprise the time slot processing unit, this time slot processing unit is used to select idle time slot, separate idle time slot, and idle time slot is combined into data channel, carry out transfer of data by data channel.
This time slot processing unit comprises:
Time slot selection device is used for selecting the idle time slot of circuit;
The time slot separator is used to receive the idle time slot that this time slot selection device transmits,
And idle time slot separated;
The time slot composite set is used to receive that this time slot separator transmits separates
Idle time slot, and the idle time slot that this is separated is combined as data channel; And
Data transmission device is used to make the cascade port to carry out data by this data channel and passes
Defeated.
Above-mentioned time slot processing unit is used to multipoint control unit that the cascade port dynamically is provided.
The present invention also provides the method that realizes the circuit dynamic cascading, and this method may further comprise the steps:
Idle time slot in the time slot of selection circuit;
Idle time slot is separated;
The time slot of separating is combined into data channel; And
The cascade port carries out transfer of data by this data channel.
The method of above-mentioned realization circuit dynamic cascading is used to multipoint control unit that the cascade port dynamically is provided.
The method of above-mentioned realization circuit dynamic cascading also comprises corresponding port is configured to virtual PRI (PRI) port; Be the corresponding port assignment numbers; Adopt the mode of virtual main speed PRI cascade to realize the dynamic cascading of line port.Time slot in the circuit is divided at least one B passage and at least one D passage, preferably 30 B passages and two D passages, one of them D passage is used for command transmitting as signalling path; This signaling adopts Q.931 agreement, and at least two MCU are configured to network side and user side respectively; When holding subtended conference, made a call to other MCU by a MCU, per call takies at least one B channel; When meeting adjourned, discharge this B passage.Also can use the time gas exchange device from the time slot of circuit, directly to extract idle time slot.
System and method provided by the invention can be used for E1 circuit and T1 line.
The present invention uses the mode of timeslot multiplex to provide many to the cascade port as MCU, though between MCU, adopt circuit to connect, but the corresponding port type configuration is become virtual PRI port, and be that corresponding port distributes virtual phone number, or use the time gas exchange device to extract idle time slot, realize the circuit dynamic cascading, compared following advantage with prior art:
1, provides many by the route road between the MCU for MCU to the cascade port;
2, need not to add miscellaneous equipment, reduced cost, improved stability;
3, real-time subtended conference for various speed provides the cascade port, has improved flexibility; And
4, made full use of valuable line bandwidth.
Brief Description Of Drawings
Fig. 1 a is existing concatenation technology implementation schematic diagram;
Fig. 1 b is the schematic diagram of existing concatenation technology implementation bandwidth usage;
Fig. 2 is the operation principle schematic diagram of time slot processing unit of the present invention;
Fig. 3 is the structure chart of time slot processing unit of the present invention;
Fig. 4 is the schematic diagram that the present invention realizes the method for E1 circuit dynamic cascading;
Fig. 5 is the flow chart that the present invention realizes the method for E1 circuit dynamic cascading;
Fig. 6 a adopts virtual PRI port mode to realize the schematic diagram that the E1 line port dynamically connects;
Fig. 6 b adopts virtual PRI port mode to realize the schematic diagram of the bandwidth usage that the E1 line port dynamically connects; And
Fig. 7 adopts the time gas exchange device to realize the schematic diagram that the E1 line port dynamically connects.
Embodiment
The core concept of the method for time slot processing unit provided by the invention and the dynamic cascading of realization circuit is to provide many to the cascade port by the mode of circuit being carried out timeslot multiplex.
Fig. 2 is the operation principle schematic diagram of time slot processing unit of the present invention.MCU1 22 is connected by the E1 circuit with MCU2 24, time slot processing unit 10 is connected with MCU1 22 and MCU2 24, the idle time slot of from the E1 circuit, selecting, should separate by the free time time slot, and idle time slot is combined into data channel, the data channel that MCU1 22 and MCU2 24 are formed by idle time slot communicates.
Fig. 3 is the structure chart of time slot processing unit of the present invention.This time slot processing unit 10 comprises time slot selection device 12, time slot separator 14, time slot composite set 16 and data transmission device 18, and this time slot selection device 12 is used for selecting the idle time slot of E1 circuit; This time slot separator 14 is used for the idle time slot that the receiving slot choice device transmits, and idle time slot is separated; This time slot composite set 16 is used to receive the idle time slot of separating that this time slot separator 14 transmits, and the idle time slot that will separate is combined as data channel; This data transmission device 18 is used to make the cascade port to carry out transfer of data by this data channel.Time slot selection device 12, time slot separator 14 and time slot composite set 16 can use the correlation module in the communication circuit chip (model of producing as MITEL company is the chip of MT8985AP), and data transmission device 18 can use the LIM in the E16 veneer of the television system VIEWPOINT8620 of Huawei.
Fig. 4 is the schematic diagram that the present invention realizes the method for E1 circuit dynamic cascading.Meeting 1 takies time slot 32, time slot 34, time slot 36 and time slot 38, and wherein time slot 36 is idle time slots.By the E1 circuit being carried out timeslot multiplex, the idle time slot 36 that meeting 2 is used in the time slot that meeting 1 is taken.In like manner, meeting 4 also can be used the idle time slot 39 of the time slot that meeting 3 occupied, and the process of timeslot multiplex can use time slot processing unit shown in Figure 3 to finish, and also can use time gas exchange device shown in Figure 6 to finish.
Fig. 5 is the flow chart that the present invention realizes the method for E1 circuit dynamic cascading.
The present invention realizes that the method for E1 circuit dynamic cascading comprises the steps: to use time slot selection device to select idle time slot in the time slot of circuit; Use the time slot separator that idle time slot is separated; Use the time slot composite set that the time slot of separating is combined into data channel; And use data transmission device to carry out transfer of data by this data channel.Above-mentioned selection time slot step, the step of separating time slot step and combination time slot can use the correlation module in the communication circuit chip (model of producing as MITEL company is the chip of MT8985AP) to realize, the step of transfer of data can use the LIM in the E16 veneer of the television system VIEWPOINT8620 of Huawei to realize.
Fig. 6 a adopts virtual PRI port mode to realize the schematic diagram that the E1 line port dynamically connects.Though also adopt the E1 circuit to connect between multipoint control unit MCU1 and the MCU2, but the e1 port of corresponding port type is configured to virtual PRI port type, e1 port assignment numbers for correspondence, the telephone number that this number is preferably virtual, the mode of employing PRI cascade has realized the dynamic cascading of E1 line port.When on MCU, holding subtended conference, take the speed of cascade circuit according to the speed of meeting, other speed that does not take can be taken by other meeting.The mode that adopts PRI to call out realizes active channel.32 time slots of an E1 circuit are divided into 30 B passages and two other passage.One in these two passages is used as signalling path, and another one is stayed and used it for anything else.Signaling adopts Q.931 agreement, and the MCU on both sides is configured to network side and user side respectively.When holding subtended conference, a MCU makes a call to other MCU on the cascade circuit, and calling can be initiated by either party MCU.Per call takies a B channel, and the speed of a B channel is 64K.When meeting adjourned, send disconnecting signal, discharge this B passage.Bottom compares the technical scheme shown in Fig. 6 a with the existing concatenation technology implementation shown in Fig. 1 a, MCU1 among Fig. 1 a is connected by the E1 circuit with the e1 port of MCU2, even the subtended conference of holding 128K also will take the bandwidth of 2M, and adopt the technical scheme among Fig. 6 a to address this problem, use virtual PRI port by the E1 line traffic between MCU1 22 and the MCU2 24, realized the dynamic cascading of E1 circuit, the subtended conference of holding 128K only takies the bandwidth of 128K.
Fig. 6 b adopts virtual PRI port mode to realize the schematic diagram of the bandwidth usage that the E1 line port dynamically connects.The 52nd, the bandwidth that meeting 1 takies, the 54th, the bandwidth that meeting 2 takies, the 56th, the bandwidth that meeting 3 takies, the 58th, the bandwidth that meeting 4 takies, as can be seen, when holding subtended conference, how many bandwidth are how many bandwidth the actual use of meeting just take from Fig. 6 b, having overcome does not have problem that the bandwidth used can not take by other meeting and Fig. 1 b to compare can to see obviously that bandwidth utilization has obtained large increase.
Fig. 7 adopts the time gas exchange device to realize the schematic diagram that the E1 line port dynamically connects.Except such scheme, can also use the related time-slot in the time gas exchange device 60 direct 2M of the extraction time slots, and it is combined into each road cascade port, realize that the E1 line port dynamically connects, this time gas exchange device can be commercial time gas exchange chip.
Although embodiments of the invention point to the E1 circuit, to those skilled in the art, obvious system and method provided by the invention can be applicable to T1 line and other similar circuit.
System and method of the present invention has been successfully applied among the TV conference system VIEWPOINT8620 of Huawei, and it has improved the utilance of E1 cascade port greatly, for operator has saved line cost.
The above is the preferred embodiments of the present invention only, is not limited to the present invention, and for a person skilled in the art, the present invention can have various changes and variation.Within the spirit and principles in the present invention all, any modification of being done, be equal to replacement, improvement etc., all should be included within the claim scope of the present invention.
Claims (14)
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| CN 03101340 CN1279759C (en) | 2003-01-03 | 2003-01-03 | System and method for realizing dynamic cascading of lines |
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| CN 03101340 CN1279759C (en) | 2003-01-03 | 2003-01-03 | System and method for realizing dynamic cascading of lines |
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Cited By (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2008092390A1 (en) * | 2007-01-26 | 2008-08-07 | Huawei Technologies Co., Ltd. | Bandwidth reuse in multiplexed data stream |
| CN100454820C (en) * | 2006-07-04 | 2009-01-21 | 华为技术有限公司 | MCU cascade system and its creation and communication method |
| US7675945B2 (en) | 2006-09-25 | 2010-03-09 | Futurewei Technologies, Inc. | Multi-component compatible data architecture |
| US7787498B2 (en) | 2007-01-26 | 2010-08-31 | Futurewei Technologies, Inc. | Closed-loop clock synchronization |
| US7809027B2 (en) | 2006-09-25 | 2010-10-05 | Futurewei Technologies, Inc. | Network clock synchronization floating window and window delineation |
| US7813271B2 (en) | 2006-09-25 | 2010-10-12 | Futurewei Technologies, Inc. | Aggregated link traffic protection |
| CN101895407A (en) * | 2010-08-09 | 2010-11-24 | 北京佳讯飞鸿电气股份有限公司 | Method for realizing conference cascade in dispatching communication system |
| US7961751B2 (en) | 2006-09-25 | 2011-06-14 | Futurewei Technologies, Inc. | Multiplexed data stream timeslot map |
| US7986700B2 (en) | 2006-09-25 | 2011-07-26 | Futurewei Technologies, Inc. | Multiplexed data stream circuit architecture |
| WO2012051887A1 (en) * | 2010-10-20 | 2012-04-26 | 中兴通讯股份有限公司 | Distant view presenting system and cascading method therefor |
| CN101540872B (en) * | 2009-02-23 | 2012-07-04 | 华为终端有限公司 | Control method of multichannel cascade connection of media control server, device and system thereof |
| US8295310B2 (en) | 2006-09-25 | 2012-10-23 | Futurewei Technologies, Inc. | Inter-packet gap network clock synchronization |
| US8340101B2 (en) | 2006-09-25 | 2012-12-25 | Futurewei Technologies, Inc. | Multiplexed data stream payload format |
| US8494009B2 (en) | 2006-09-25 | 2013-07-23 | Futurewei Technologies, Inc. | Network clock synchronization timestamp |
| US8532094B2 (en) | 2006-09-25 | 2013-09-10 | Futurewei Technologies, Inc. | Multi-network compatible data architecture |
| CN103354557A (en) * | 2009-08-31 | 2013-10-16 | 华为终端有限公司 | Media control server cascade system, multimedia code stream control method and apparatus thereof |
| US8660152B2 (en) | 2006-09-25 | 2014-02-25 | Futurewei Technologies, Inc. | Multi-frame network clock synchronization |
| US8872886B2 (en) | 2012-02-06 | 2014-10-28 | Huawei Technologies Co., Ltd. | Method, apparatus, and system for establishing multi-cascade channel |
| CN107844451A (en) * | 2017-10-23 | 2018-03-27 | 复旦大学 | " butterfly " transmission method of streamline between a kind of subtending board |
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2003
- 2003-01-03 CN CN 03101340 patent/CN1279759C/en not_active Expired - Fee Related
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| CN100454820C (en) * | 2006-07-04 | 2009-01-21 | 华为技术有限公司 | MCU cascade system and its creation and communication method |
| US8660152B2 (en) | 2006-09-25 | 2014-02-25 | Futurewei Technologies, Inc. | Multi-frame network clock synchronization |
| US8494009B2 (en) | 2006-09-25 | 2013-07-23 | Futurewei Technologies, Inc. | Network clock synchronization timestamp |
| US8982912B2 (en) | 2006-09-25 | 2015-03-17 | Futurewei Technologies, Inc. | Inter-packet gap network clock synchronization |
| US7809027B2 (en) | 2006-09-25 | 2010-10-05 | Futurewei Technologies, Inc. | Network clock synchronization floating window and window delineation |
| US7813271B2 (en) | 2006-09-25 | 2010-10-12 | Futurewei Technologies, Inc. | Aggregated link traffic protection |
| US8976796B2 (en) | 2006-09-25 | 2015-03-10 | Futurewei Technologies, Inc. | Bandwidth reuse in multiplexed data stream |
| US7961751B2 (en) | 2006-09-25 | 2011-06-14 | Futurewei Technologies, Inc. | Multiplexed data stream timeslot map |
| US7986700B2 (en) | 2006-09-25 | 2011-07-26 | Futurewei Technologies, Inc. | Multiplexed data stream circuit architecture |
| US8532094B2 (en) | 2006-09-25 | 2013-09-10 | Futurewei Technologies, Inc. | Multi-network compatible data architecture |
| US9106439B2 (en) | 2006-09-25 | 2015-08-11 | Futurewei Technologies, Inc. | System for TDM data transport over Ethernet interfaces |
| US8289962B2 (en) | 2006-09-25 | 2012-10-16 | Futurewei Technologies, Inc. | Multi-component compatible data architecture |
| US8295310B2 (en) | 2006-09-25 | 2012-10-23 | Futurewei Technologies, Inc. | Inter-packet gap network clock synchronization |
| US8340101B2 (en) | 2006-09-25 | 2012-12-25 | Futurewei Technologies, Inc. | Multiplexed data stream payload format |
| US8837492B2 (en) | 2006-09-25 | 2014-09-16 | Futurewei Technologies, Inc. | Multiplexed data stream circuit architecture |
| US7675945B2 (en) | 2006-09-25 | 2010-03-09 | Futurewei Technologies, Inc. | Multi-component compatible data architecture |
| US9019996B2 (en) | 2006-09-25 | 2015-04-28 | Futurewei Technologies, Inc. | Network clock synchronization floating window and window delineation |
| US8401010B2 (en) | 2006-09-25 | 2013-03-19 | Futurewei Technologies, Inc. | Multi-component compatible data architecture |
| US8588209B2 (en) | 2006-09-25 | 2013-11-19 | Futurewei Technologies, Inc. | Multi-network compatible data architecture |
| US8605757B2 (en) | 2007-01-26 | 2013-12-10 | Futurewei Technologies, Inc. | Closed-loop clock synchronization |
| WO2008092390A1 (en) * | 2007-01-26 | 2008-08-07 | Huawei Technologies Co., Ltd. | Bandwidth reuse in multiplexed data stream |
| US7787498B2 (en) | 2007-01-26 | 2010-08-31 | Futurewei Technologies, Inc. | Closed-loop clock synchronization |
| US8392535B2 (en) | 2009-02-23 | 2013-03-05 | Huawei Device Co., Ltd. | Method, device and system for controlling multichannel cascade between two media control servers |
| CN101540872B (en) * | 2009-02-23 | 2012-07-04 | 华为终端有限公司 | Control method of multichannel cascade connection of media control server, device and system thereof |
| CN103354557A (en) * | 2009-08-31 | 2013-10-16 | 华为终端有限公司 | Media control server cascade system, multimedia code stream control method and apparatus thereof |
| CN101895407A (en) * | 2010-08-09 | 2010-11-24 | 北京佳讯飞鸿电气股份有限公司 | Method for realizing conference cascade in dispatching communication system |
| WO2012051887A1 (en) * | 2010-10-20 | 2012-04-26 | 中兴通讯股份有限公司 | Distant view presenting system and cascading method therefor |
| US8872886B2 (en) | 2012-02-06 | 2014-10-28 | Huawei Technologies Co., Ltd. | Method, apparatus, and system for establishing multi-cascade channel |
| CN107844451A (en) * | 2017-10-23 | 2018-03-27 | 复旦大学 | " butterfly " transmission method of streamline between a kind of subtending board |
| CN107844451B (en) * | 2017-10-23 | 2020-11-20 | 复旦大学 | A "Butterfly" Transmission Method for Cascading Inter-Board Pipelines |
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Effective date of registration: 20170929 Address after: Shuang Hou Zhen 276300 Shandong province Linyi city Yinan County Buddha village group 235 Patentee after: Fang Zhongchen Address before: 518057 Guangdong city of Shenzhen province Nanshan District Science Park Branch Road No. 1 HUAWEI service building Patentee before: Huawei Technologies Co., Ltd. |
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