CN1527302A - Jitter signal detecting device and method for jitter phase synchronizing phase-locked loop - Google Patents
Jitter signal detecting device and method for jitter phase synchronizing phase-locked loop Download PDFInfo
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Abstract
The present invention is the jitter signal detecting device and method for jitter phase synchronizing phase-locked loop. In the jitter phase synchronizing phase-locked loop, the analog jitter signal of CD is first filtered in the band pass filter and converted in the A/D converter, and its slope is then detected and its top point is determined for detection. The higher and lower rectangular wave jitter signals are converted, and with the density of the record tracks in the optical record medium, the amplitude variation of the analog jitter signal, the low frequency components and DC offset component of the jitter signal, the amplitude variation of the phase-locked signal and the stable jitter signal are detected so as to perform the phase error compensation of jitter synchronizing phase-locked loop.
Description
(1) technical field
The invention relates to record or play the CD that to write down or the field of CD such as DVD, refer in particular to according to generating the recording impulse frequency WRITE CLOCK of output with master phase synchronous phase-locked loop MAINPLL or playing dither signal pick-up unit and method in the shake phase-locking phase-locked loop that pulsed frequency READ CLOCK is synchronized with the dither signal of being read by CD.
(2) background technology
At first, Fig. 1 is the summary pie graph of common shake phase-locking phase-locked loop.Comprise among the figure: the shake synchronous phase-locked loop 100 (with call in the following text ' WOBBLE PLL '), dither signal chopper 12, phase error detector 13, loop filter 14, and numerically-controlled oscillator DCO (Digital ControlledOscillator) 15).
In addition, the optical recording media that can write down, for example the dither signal of reading as the CD of DVD-RW (DVD-Rewritable) is push-pull (PUSH-PULL) signal, by bandpass filter (BPF) 10 filtering, dispel high frequency noise, dc offset (DC Off set) becomes to grade, and carries out A/D by A/D converter (ADC) 11 afterwards and converts digital signal to.
In addition, in the dither signal of above-mentioned shake synchronous phase-locked loop WOBBLE PLL100, the dither signal that above-mentioned A/D is changed is with the reference grade of prior setting, for example zero ZERO rank is a benchmark, carry out copped wave (SLICE), as shown in Figure 2, detect output with square wave form dither signal, contrast in above-mentioned phase error detector 13, measure from the PLL pulsed frequency of above-mentioned numerically-controlled oscillator 15 outputs and from the mistake between the dither signal of above-mentioned dither signal chopper 12 outputs, with above-mentioned loop filter 14 outputs.
In addition, in above-mentioned loop filter 14, with the phase error from above-mentioned phase error detector 13 outputs is benchmark, above-mentioned numerically-controlled oscillator 15 produces the phase-locking compensation value of PLL pulse, above-mentioned loop filter 14 is to play the effect of a kind of low territory by filtering LPF, make from the PLL pulse of above-mentioned numerically-controlled oscillator 15 outputs, make it be synchronized with above-mentioned dither signal.
In addition, in above-mentioned numerically-controlled oscillator 15, generate the phase compensation value of output, compensation existing P LL pulse along with above-mentioned shake filtering.The dither signal of above-mentioned A/D conversion and PLL pulse are input in the bit instrument 16, utilize above-mentioned PLL frequency, the dither signal of A/D conversion are transformed to 1 or 0 bit data flow.
In addition, in above-mentioned device, comprise that also the data stream that forms in the bit instrument 16 detects the synchroscope 17 that is carried in the synchronous images in the dither signal, generate and export synchronizing signal corresponding to synchronous images, the address decoder 18 of the physical address of the data stream decoding CD from above-mentioned bit instrument 16, synchronizing signal with above-mentioned synchroscope is a benchmark, decodes, with the input of the physical address of CD output as main synchronous phase-locked loop 300.
In addition, in the phase error detector 13 of existing as mentioned above shake synchronous phase-locked loop WOBBIE PLL100, as shown in Figure 3, the dither signal of A/D conversion from just when negative 0 intersects (NZCP) for measuring phase error.Determine the Time Calculation value of the oscillation frequency of above-mentioned numerically-controlled oscillator 15, for example freely reduce the Time Calculation value, can be compensated by the phase error that above-mentioned NZCP initial point detects.
At this moment, the PLL impulse phase that produces from above-mentioned numerically-controlled oscillator 15 in advance when the dither signal phase place of A/D conversion, as shown in Figure 3, detects and generates plus phase error and output to loop filter 14 in above-mentioned phase error detector 13.The Time Calculation value of decision numerically-controlled oscillator 15 frequency cycles produces compensation in a small amount according to above-mentioned plus phase error value in above-mentioned loop filter 14.
In addition, the PLL impulse phase that generates from above-mentioned numerically-controlled oscillator 15 when the dither signal phase place of A/D conversion, as shown in Figure 3, detects and generates negative phase error in above-mentioned phase error detector 13 in advance, outputs to loop filter 14.The Time Calculation value of decision numerically-controlled oscillator 15 frequency cycles produces a large amount of compensation according to above-mentioned negative phase error value in above-mentioned loop filter.
Therefore, among the above-mentioned shake synchronous phase-locked loop WOBBIE PLL100, at above-mentioned NZCP initial point detected phase error amount, the Time Calculation value of the above-mentioned numerically-controlled oscillator 15 frequency cycles of decision compensation continues the phase error compensation action that makes the PLL pulsed frequency be synchronized with dither signal.
But, nearest raising along with video disc recording density, track record is also denser, the influence of therefore facing the dither signal that integrates with becomes big, dither signal signal to noise ratio (S/N ratio) S/N (SIGNAL TONOISE RATIO) through above-mentioned bandpass filter 10 outputs diminishes, so existing mode can not form stable dither signal detection.
Tracking servo and focus servo are unstable or when the vibrations etc. of cd side take place in addition, in vibration signal, flow into low frequency fluctuation (FLUCTUATION) composition and the direct current offset composition or the variable amplitude of dither signal, such as shown in Figure 4 through above-mentioned bandpass filtering output.The stable dither signal 1 that a certain size possesses amplitude of holding through the dither signal output of above-mentioned bandpass filtering output, above-mentioned dither signal chopper normally detects stable dither signal 2 but when flowing into low frequency fluctuation composition and direct current offset composition 3 in the dither signal of above-mentioned bandpass filtering output or dither signal variable amplitude and direct current offset composition flow at 5 o'clock, detect improper dither signal 4 with above-mentioned dither signal chopper, the problem that result 6 has the phase error compensation program in the shake phase-locking loop normally not carry out occurred.
(3) summary of the invention
The present invention creates for addressing the above problem, and behind the flating signal of shake synchronous phase-locked loop by bandpass filtering and A/D conversion CD, detects the pulsed frequency of its A/D conversion dither signal, and decision detects the summit of dither signal.On its summit, detect the dither signal of moving into high-level or low-level square wave form, in order to stablize dither signal and a kind of dither signal pick-up unit and method of shaking in the phase-locking phase-locked loop of shaking phase place normally.
The object of the present invention is achieved like this:
A kind of dither signal pick-up unit of shaking in the phase-locking phase-locked loop, comprise: the dither signal of reading from the optical recording media of DVD-RW, by band-pass filter, afterwards, carry out A/D by A/D converter and convert digital signal to, via the dither signal chopper, phase error detector, loop filter, and the shake synchronous phase-locked loop that numerically-controlled oscillator is formed carries out phase error compensation and exports the PLL pulsating wave, pass through the bit instrument again, synchroscope, address decoder, the actual address of optical recording media is outputed to main locking phase phase-locked loop, and wherein said shake synchronous phase-locked loop also comprises:
Slope detector: detect by described A/D converter and carry out the device that A/D converts the slope of digital dither signal changing value to; And
Dither signal detecting device: described dither signal chopper is designed to the dither signal detecting device, utilize the above-mentioned dither signal slope that is detected, detecting behind the summit of above-mentioned dither signal with its summit is benchmark, detects the dither signal pick-up unit of dither signal of the square wave form of the high-level or low level migration of output.
A kind of dither signal detection method of shaking in the phase-locking phase-locked loop comprises:
The 1st step: by band-pass filter, reach the analog dither signal that A/D converter convert light recording medium is read, detect the dither signal slope of its A/D conversion;
The 2nd step: utilize above-mentioned detected dither signal slope, detect above-mentioned dither signal summit; And
The 3rd step: with above-mentioned detected dither signal summit is benchmark, detects the dither signal of output with high-level or low-level square wave form
Effect of the present invention:
As dither signal pick-up unit and the method in the shake phase-locking phase-locked loop of the present invention of above-mentioned formation and formation, be to shake the phase-locking phase-locked loop with the analog dither signal of CD by bandpass filtering and A/D conversion after, detect the dither signal frequency of its A/D conversion, determine and detect the summit of dither signal, detect the dither signal of moving into high-level or low-level square wave form on its summit, dense along with the video disc recording track, diminished by the analog dither signal amplitude of above-mentioned bandpass filtering or dither signal on when flowing into low frequency fluctuation composition and direct current offset composition, or when the dither signal variable amplitude, can detect stable dither signal, therefore the action that can normally shake the phase error compensation in the phase-locking phase-locked loop.
For further specifying above-mentioned purpose of the present invention, design feature and effect, the present invention is described in detail below with reference to accompanying drawing.
(4) description of drawings
Fig. 1 is the pie graph of existing shake synchronous phase-locked loop Wobble PLL;
The waveform synoptic diagram of Fig. 2 for being carried out the PLL pulse of phase error compensation by existing shake synchronous phase-locked loop;
Fig. 3 is at the phase error Phase of existing shake synchronous phase-locked loop Error, the time of PLL pulse and numerically-controlled oscillator control calculated value synoptic diagram;
Fig. 4 is the synoptic diagram of detected improper dither signal oscillogram in the existing shake synchronous phase-locked loop;
Fig. 5 is the formation synoptic diagram of the shake synchronous phase-locked loop of the dither signal pick-up unit that is suitable for according to the present invention and method;
Fig. 6 is slope (SLOPE) the testing process synoptic diagram of dither signal in the present invention;
Fig. 7 is the synoptic diagram of slope (SLOPE) the detection waveform figure of dither signal in the present invention;
Fig. 8 is the summit testing process synoptic diagram of dither signal in the present invention;
Fig. 9 is the synoptic diagram of the summit detection waveform figure of dither signal in the present invention;
Figure 10 is in the present invention by the oscillogram synoptic diagram of the normal dither signal that detects of dither signal pick-up unit and method.
The symbol description of major part in the accompanying drawing:
10: bandpass filter (BPF) 11:A/D converter
12,22: dither signal pick-up unit 13: phase error detector
14: loop filter 15: numerically-controlled oscillator
16: bit instrument 17: synchroscope
18: address decoder 21: slope detector
100,200: shake synchronous phase-locked loop 300: main synchronous phase-locked loop
(5) embodiment
Below, for the dither signal pick-up unit in the shake synchronous phase-locked loop of the present invention and the embodiment of method, be elaborated with reference to the accompanying drawings.
Fig. 5 is in the present invention, and the shake synchronous phase-locked loop that is suitable for dither signal pick-up unit and method constitutes synoptic diagram, comprises;
Bandpass filter (BPF) 10 filtering, A/D converter (ADC) 11, shake synchronous phase-locked loop (WOBBLEPLL) 200, comprise: constitute slope detector 21, dither signal detecting device 22, phase error detector 23, loop filter 24 and numerically-controlled oscillator (DCP) 25, write as Fig. 1 in the above-mentioned slope detector 21, detect anodal slope and negative pole slope to the dither signal of A/D conversion, in above-mentioned dither signal detecting device 22, determine the summit of above-mentioned dither signal to detect the dither signal that other high-level or low-level square wave form of each grade is moved in output on this summit according to above-mentioned anodal slope and negative pole slope detection.
In addition, in above-mentioned phase error detector 23, PLL frequency and the phase error of contrast output between the dither signal of the square wave form of above-mentioned summit grade migration from above-mentioned numerically-controlled oscillator 25 outputs, in above-mentioned loop filter 24 outputs, in above-mentioned loop filter 24, be benchmark with phase error from 23 outputs of above-mentioned phase error detector, generation is for the phase compensation value of the PLL frequency of above-mentioned numerically-controlled oscillator 25, with above-mentioned numerically-controlled oscillator 25 outputs.
So in above-mentioned numerically-controlled oscillator 25, according to the phase compensation value that generates and export from above-mentioned loop filter 24, compensation existing P LL pulsed frequency cycle generates the PLL frequency that also output is synchronized with dither signal.The PLL frequency that is generated and export by above-mentioned shake synchronous phase-locked loop WOBBLE PLL200 is to confirm with the bit instrument of the oscillator signal output of above-mentioned A/D conversion, in above-mentioned bit instrument 16, utilize above-mentioned PLL frequency, the dither signal of A/D conversion is detected and be transformed to the data stream of holding 1 or 0 value.
In addition, synchroscope 17 is to detect from above-mentioned data stream is loaded on the data stream of synchronous image of dither signal to generate and export corresponding its visual synchronizing signal.In addition from above-mentioned bit instrument 16 data stream, remove the address decoder 18 of decoding CD physical address, be benchmark with the synchronizing signal of above-mentioned synchroscope 17, carry out decoding program, the CD physical address is outputed to main synchronous phase-locked loop 300.The result continues to make the PLL pulsed frequency to be synchronized with the phase error compensation program that dither signal one links up.Form according to above-mentioned slope detector 21 and dither signal detecting device 22.For the program of dither signal detecting device 22 following detailed description.
Fig. 6 and Fig. 7 be, in the dither signal slope detection process of the present invention, and the slope detection oscillogram of dither signal, as shown in Figure 6, through the analog dither signal of bandpass filter 1010 outputs, by the A/D conversion.When above-mentioned slope detector 21 is imported, in above-mentioned slope detector 21, be mixed in the high frequency interference component of A/D conversion dither signal for releasing, at the certain hour of the digital dither signal of A/D conversion before this, relatively big or small mutually again such as the dither signal data of A/D conversion before the dither signal cycle 10%.
In addition, its fiducial value is in the reference value of setting (THRESHOLD) in advance, when differing such as 2 bits, detect the dither signal slope, as shown in Figure 6, dither signal at one-period is sampled as under (70sample) state of 70 shake data, and the digital dither signal data of A/D variation now are the data that were sampled as digital dither signal before the dither signal cycle 10%.That is, the shake data-signal (7sample) of sampling is that 111101XX`XX is under the uncared-for situation before 7, and ' the 1` value differs more than 2 bits its fiducial value 1101 10XX-1111 01XX one-tenth.Determine the slope of dither signal this moment, above-mentioned situation detects the negative pole slope.
In addition, above-mentioned fiducial value differ 2 bits above for "+" value the time because the dither signal slope detection is positive plate slope, in above-mentioned slope detector 21, as shown in Figure 6, each comfortable detection is also exported.Above-mentioned fiducial value becomes other negative pole slope of level when being "-".Detection signal and above-mentioned fiducial value become the anodal slope detection signal of rank when being "+".
Then, at the anodal slope detection signal and the negative pole slope detection signal of above-mentioned dither signal detecting device 22 and input, shown in 7, hold mutual different waveform separately.
In addition, Fig. 8 and Fig. 9 are dither signal of the present invention summit testing process and dither signal summit detection waveform figure, at above-mentioned dither signal detecting device 22, and as described in forwardly, the certain-length when anodal slope detection signal and the input of negative pole slope detection signal.Accumulate the 1/2 value T/2 that is present in 1 cycle 1T of its signal such as produce vacation from above-mentioned anodal slope detection signal to negative pole slope detection signal separately as window.
In addition, the more above-mentioned mutually value of accumulation separately, at the accumulating value of the above-mentioned anodal slope accumulating value greater than above-mentioned negative pole slope, output high (HIGH) at the accumulating value of the above-mentioned anodal slope accumulating value less than above-mentioned negative pole slope, is exported low (LOW).
Next in the above-mentioned dither signal detecting device 22, according to above-mentioned anodal slope detection signal and negative pole slope detection signal, detect and determine the summit of analog dither signal, on its summit, detect and export and move into high-level or low-level square wave form dither signal, so analog dither signal, anodal slope, the negative pole slope also has the dither signal that is detected output by above-mentioned dither signal detecting device 22, holds waveform as shown in Figure 9 separately.
Then, as shown in figure 10, through the dither signal of above-mentioned bandpass filter (10) filtering output be output as the stable dither signal 1 of a certain size amplitude ', in the above-mentioned dither signal detecting device 22, do the stable dither signal 2 of grade migration ' can normally check out on the dither signal summit, pass through in addition and flow into low frequency fluctuation composition and 3 ' time of direct current composition on the dither signal of above-mentioned bandpass filter (10) filtering output, or flow into the variable amplitude and the 5 ' time of direct current offset composition of dither signal, in above-mentioned dither signal inspection side device 22, the stable dither signal 4 that detection output is moved by dither signal summit grade ', 6 '.
Please refer to, utilize by the detected dither signal of said process, a series of actions of compensation PLL pulsed frequency, can replace by other various fact Examples, put down in writing on Fig. 4 and Figure 10 in addition ' MSK ' is by a common dither signal that Minimum Shift Keying modified tone mode modifies tone in various dither signal modified tone mode, shows with this.
The foregoing description is that the purpose of prerun is enlightened above-mentioned slope detector 21 and dither signal detecting device 22, and phase error detector 23 integrated formation.
Those of ordinary skill in the art will be appreciated that, above embodiment is used for illustrating the present invention, and be not to be used as limitation of the invention, as long as in connotation scope of the present invention, all will drop in the scope of claims of the present invention variation, the modification of the above embodiment.
Claims (9)
1, a kind of dither signal pick-up unit of shaking in the phase-locking phase-locked loop, comprise: the dither signal of reading from the optical recording media of DVD-RW, through band-pass filter, afterwards, carry out A/D by A/D converter and convert digital signal to, via the dither signal chopper, phase error detector, loop filter, and the shake synchronous phase-locked loop that numerically-controlled oscillator is formed carries out phase error compensation and exports the PLL pulsating wave, pass through the bit instrument again, synchroscope, address decoder, the actual address of optical recording media is outputed to main locking phase phase-locked loop, it is characterized in that described shake synchronous phase-locked loop also comprises:
Slope detector: detect by described A/D converter and carry out the device that A/D converts the slope of digital dither signal changing value to; And
Dither signal detecting device: described dither signal chopper is designed to the dither signal detecting device, utilize the above-mentioned dither signal slope that is detected, detecting behind the summit of above-mentioned dither signal with its summit is benchmark, detects the dither signal pick-up unit of dither signal of the square wave form of the high-level or low level migration of output.
2, the dither signal pick-up unit in the shake phase-locking phase-locked loop as claimed in claim 1, it is characterized in that described slope detector is, according to the changing value between the dither signal of the existing dither signal of described A/D converter conversion and the A/D converter conversion before of fixing time, detect the anodal slope and the negative pole slope of the above-mentioned dither signal of output separately, and output to described dither signal detecting device.
3, the dither signal pick-up unit in the shake phase-locking phase-locked loop as claimed in claim 2, it is characterized in that described dither signal detecting device is, between the anodal slope of the detected dither signal of described slope detector and negative pole slope, generate imaginary window, to in its window, exist. after anodal slope value and negative pole slope value are accumulated separately, according to its accumulated value contrast phase difference, detect above-mentioned dither signal summit.
4, a kind of dither signal detection method of shaking in the phase-locking phase-locked loop is characterized in that described method comprises:
The 1st step: by band-pass filter, reach the analog dither signal that A/D converter convert light recording medium is read, detect the dither signal slope of its A/D converter conversion;
The 2nd step: utilize above-mentioned detected dither signal slope, detect above-mentioned dither signal summit; And
The 3rd step: with above-mentioned detected dither signal summit is benchmark, detects the dither signal of output with high-level or low-level square wave form.
5, the dither signal detection method in the shake phase-locking phase-locked loop as claimed in claim 4, size before the existing dither signal data that it is characterized in that detected A/D converter conversion in described the 1st step are fixed time with institute between the dither signal data of A/D converter conversion is poor, when the reference value of setting is above before being worse than mutually with detection output jitter signal slope.
6, as the dither signal detection method in claim 4, the 5 described shake phase-locking phase-locked loops, the size that it is characterized in that the present dither signal data of A/D converter conversion in described the 1st step and the dither signal data that dither signal one-period 10% former A/D changes is poor, when differing above its difference of 2 bits for " one " value, detect the negative level slope of output separately with the low level migration, when being " ten " value, with the anodal slope of high-level migration with its difference.
7, the dither signal detection method in the shake phase-locking phase-locked loop as claimed in claim 6, generate vacation as window between the anodal slope of dither signal that it is characterized in that described detection and negative pole slope, after anodal slope value that exists in its window and negative pole slope value are accumulated separately, compare difference according to its accumulated value and detect the dither signal summit.
8, as claim 4, dither signal detection method in the 7 described shake phase-locking phase-locked loops, it is characterized in that with described detected dither signal summit be benchmark, detect the dither signal of output with high-level or low-level square wave form, when the accumulated value of the anodal slope in the above-mentioned window during greater than above-mentioned negative pole slope accumulated value output high-level, above-mentioned anode slope accumulated value is the output low level during less than above-mentioned negative pole slope accumulated value, more than, the dither signal summit of above-mentioned detection is a benchmark, detects the dither signal of the square wave form of exporting high-level or low level migration.
9, the dither signal detection method in the shake phase-locking phase-locked loop as claimed in claim 7, the length that it is characterized in that described window be equivalent to dither signal one-period T 1/2.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101552011B (en) * | 2008-03-31 | 2012-05-02 | 索尼株式会社 | Laser driving circuit, its recording compensation method and optical-disk apparatus |
| CN101578527B (en) * | 2007-01-11 | 2013-01-09 | 国际商业机器公司 | Method and apparatus for on-chip phase error measurement to determine jitter in phase-locked loops |
| CN111190089A (en) * | 2018-11-14 | 2020-05-22 | 长鑫存储技术有限公司 | Method and device for determining jitter time, storage medium and electronic equipment |
-
2003
- 2003-03-05 CN CNA031153518A patent/CN1527302A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101578527B (en) * | 2007-01-11 | 2013-01-09 | 国际商业机器公司 | Method and apparatus for on-chip phase error measurement to determine jitter in phase-locked loops |
| CN101552011B (en) * | 2008-03-31 | 2012-05-02 | 索尼株式会社 | Laser driving circuit, its recording compensation method and optical-disk apparatus |
| CN111190089A (en) * | 2018-11-14 | 2020-05-22 | 长鑫存储技术有限公司 | Method and device for determining jitter time, storage medium and electronic equipment |
| CN111190089B (en) * | 2018-11-14 | 2022-01-11 | 长鑫存储技术有限公司 | Method and device for determining jitter time, storage medium and electronic equipment |
| US11733293B2 (en) | 2018-11-14 | 2023-08-22 | Changxin Memory Technologies, Inc. | Method and apparatus for determining jitter, storage medium and electronic device |
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