CN1534509A - Flash memory algorithm with fast and improper operation prevention function and control system thereof - Google Patents

Abstract

The present invention relates to a flash memory algorithm, and more particularly, to a flash memory algorithm and a control system thereof capable of fast table establishment and preventing data corruption due to abnormal power failure, it mainly stores the link relation mapping table data of the logical block address and the corresponding physical block address value data in a data physical block paging of the memory and is protected by an ECC data, when the computer host is normally started up, the control device directly transfers and registers the mapping table data in a register of the control device to be read by the control device, the establishment of the mapping table is immediate and fast, the system not only can quickly establish the mapping table without the need of scanning procedure to save the startup time and operation procedure, if the mapping table is wrong due to abnormal operation of the system, the system connection can be recovered to normal by backtracking the last mapping table.

Description

Flash Memory Algorithm and Control System with Fast and Improper Operation Prevention

technical field

The present invention relates to a flash memory algorithm, in particular to a flash memory algorithm and its control system which can quickly build a table and prevent data confusion caused by abnormal power failure.

Background technique

The rapid development of the information industry, affected by the faster and faster CPU speed and the rise of IA products, high-speed data storage devices (memory) will also play an extremely important role. Among various data storage devices, flash memory is widely expected by users because of its non-volatile and easy-to-change data access characteristics.

Press, as shown in Figure 1A, be the structure schematic diagram of general data storage system; At least one data storage device (such as Smart Media memory card, Memory Stick memory card etc. various flash memories) 11～19 is mainly by a control device 20 and connected with a host computer 29 (certainly, the control device 20 can also be built in a subsystem of the computer host 29), the control device 20 includes a microprocessor 25, which can be controlled by a PCMCIA, IDE, ATA, MMC, SD, Compact Flash or the host interface controller 24 of its combined specification agreement and is connected with the host computer 29, and one end of the microprocessor 25 can be connected to the data via a storage control logic circuit 26 Storage device 11～19; Microprocessor 25 also can be connected with a temporary storage area controller 22, and this temporary storage area controller 22 can control host computer 29 to want to access data to temporarily store in a data storage area 21 (the first temporary storage area 21). register 211, the second register 213 and the Nth register 219). In addition, an ECC logic circuit 23 is respectively connected to the microprocessor 25, the temporary register controller 22 and the storage control logic circuit 26, which is controlled by the microprocessor 25 and gives corresponding control to the data magnetic area to be accessed. Error Correction Code ECC data. In addition, the microprocessor 25 can be connected to a lookup table (Lookup Table) 255, which can be used to record the logical block addresses (L ₀ ˜L _m+1 ) and all data storage devices 11 corresponding thereto. Physical block address data value (PDA).

Please refer to FIG. 1B, the memory used by the search list 255, such as random access memory (RAM), is mainly based on a character (WORD) as an access unit, and is divided into a plurality of character addresses (logical block bits) address) L ₀ , L ₁ , ..., L _m , L _m+1 , ..., each logical block address contains a data value PBA ( B ₃ , B ₂ , . . . , B _m+1 , B _m , . . . ). The flash memory 11 is mainly divided into a plurality of physical block addresses B ₀ ~B _n based on a block (block) as an access unit, and each physical block address B ₀ ~B _X is a physical area Each block (Data ₀ ~ Data _n ) contains a plurality of block pages, and each page is equivalent to a minimum storage unit sector (sector) on the host side. After each page, a record can be added for each phase in the block. Error-correcting code column ECC (E ₀ ~E _n ; error-correcting code) corresponding to the page, and record the logical block address of the corresponding logical block (L ₂ , L ₃ , L ₁ .., L _m+1 ) column LBA, wherein the PDA column of the search list 255 is corresponding to the LBA column of the memory 11, for example, the logical address data value of the stored data Data ₀ in the memory data entity block B ₀ points to the search list 255 Therefore, it is registered as _L2 in its LBA column (this data will be stored without disappearing even after a power failure), and the PBA column of the magnetic zone _L2 in the _search list 255 is registered as _B0 (this The data will disappear after power off), as shown by the double arrows in the solid line, and so on, as shown in Figure 1B.

When the system is turned on, the PBA column of the search list 255 does not exist, and the microprocessor 25 will scan each physical block address and block logical address data value LBA of the flash memory 11-19, and perform the logical block according to the logical block The address fills the corresponding relationship into the physical block address column PBA of the search list 255 , thereby establishing a complete search list 255 . However, this operation method of scanning and then building a search list is not only inconvenient but also a waste of operation time.

Also, due to the structure of the flash memory 11, block 5 is used as a unit when erasing or accessing data, so when there is a physical block modification (such as B ₂ ), the block B to be changed must be changed. The originally stored data Data ₂ in ₂ is first transferred to a clean physical block (B _m+1 ) that is available but has not yet stored data, and registered in the LBA column after this physical block B _m+1 Logical address L1, and then erase the data Data ₂ in the block B ₂ to be changed into a clean block or record unused. However, if the clean block (such as B _m+1 ) has completed data transfer and filled in logical address data value procedures, but the block B ₂ to be changed has not yet completed the erasing operation, such as a sudden power failure Or crash and other abnormal shutdown conditions, and when restarting and the microprocessor 25 scans the logic address data program of each physical block of each memory 11 again, two data blocks B ₂ and B _m may occur ₊₁ is registered in the logical block address value L1 and points to the same corresponding search list 255 address (as shown by the dotted double arrow), or some blocks may not be connected, which is not only easy to cause data errors links, and even cause data damage.

Therefore, how to use another more novel flash memory mapping table and its construction method can not only directly and quickly establish the mapping table when the system is turned on, but also prevent various abnormal operating conditions such as sudden or power failures. , to ensure the accuracy of data linking, has long been a difficult point that users have longed for and that the present invention intends to solve, and the inventor is based on many years of practical experience in research, development, and sales of information products. Thinking about the idea of improvement, relying on personal professional knowledge, after many designs, discussions, and numerous trial samples and improvements, we can finally create a flash memory of the present invention that is fast and prevents improper operation. Algorithm and its control system.

Contents of the invention

The main purpose of the present invention is to provide a flash memory algorithm and its control system with fast and improper operation prevention functions. Block paging is reproduced in a temporary register for fast switching, without the need for the microprocessor to scan the logical address data of each memory entity block with a scanning program, so it not only simplifies the working time of the microprocessor, but also can Great time saver.

The secondary purpose of the present invention is to provide a flash memory algorithm and its control system with fast and improper operation prevention functions. It is a pity that the data is not properly linked due to the operation.

Another object of the present invention is to provide a flash memory algorithm and its control system with fast and preventive effects of improper operation. The mapping table data can be protected by a set of ECC data to improve the accuracy of the data.

Another object of the present invention is to provide a fast and preventive flash memory algorithm and its control system, which can allocate all memory blocks according to the temporary register or block paging memory capacity It is divided into a plurality of segment areas, and each segment area has a corresponding register mapping table to establish a data mapping relationship. When there is a block data change, only the relevant mapping table data will be affected, so it can be effectively Reduce the operating time for changing the mapping table, and effectively reduce the occurrence of data error link situations.

Another object of the present invention is to provide a fast and preventive flash memory algorithm and its control system, which can divide all physical blocks into multiple partitions, so that the size of the mapping table can be reduced to Exactly one magnetic sector (256Words), so that this mapping table can also be stored in the flash memory as general data, so it can greatly save the memory capacity of the physical address data of the registration block, and is suitable for linking multiple fast in flash memory storage systems.

The object of the present invention is achieved in this way: a control system of flash memory, which is mainly connected to a host computer and at least one flash memory respectively by a control device, and a plurality of temporary storage devices are arranged in the control device. device, and part of the temporary register can be used to load the mapping table data of the logical block address and the corresponding physical block address data value, and the mapping table data can be stored in a part of the physical block of the flash memory .

The number of physical blocks in the flash memory can be segmented into a plurality of partition groups in order to match the storage capacity of the register.

Each partition group has a corresponding page mapping table data, and the page mapping table data can be stored in the corresponding memory physical block page.

The storage capacity of the mapping table is one of 256bytes and 512bytes.

The number of memory physical blocks that can be mapped by a mapping table is one of 128 and 256 selectable.

A character number in the mapping table can be registered to map a corresponding memory block.

The register for registering the mapping table can be a data storage device.

The physical memory block storing the mapping table data is provided with a special mark.

The algorithm of a kind of flash memory described in the present invention, it mainly stores in a flash memory a mapping that records the address data values of each physical block of the memory and its corresponding logical block address When the system is turned on, the mapping table data can be directly transferred to a temporary register of the control device under the control of a control device.

The above-mentioned algorithm also includes the following steps: when it is desired to change the data stored in a physical block, first the data that does not need to be changed in the block to be changed will be reprinted to a clean entity that is available but has not yet stored other data Afterwards, all the data in the block to be changed will be erased, and the address data of the relevant physical block will be directly changed in the mapping table of the temporary register, and the changed data will be changed later The mapping table data is stored in another physical block of the memory.

The above-mentioned algorithm can also include the following steps: after the data in the block to be changed has been erased, if abnormal operation occurs and the computer is restarted, the control device will store the data stored in the physical block of the memory before. The mapping table data will be reproduced in the scratchpad.

The above-mentioned algorithm further includes the following steps: identifying whether there is abnormal operation from the ECC data of the physical block storing the mapping table data.

The above-mentioned algorithm also includes the following steps: the mapping table data recorded with the relevant link addresses of each physical block of the memory is stored in a partial page of a physical block of the memory, and the address of the partial page includes a special The mark is useful for the system to immediately search for the page mapping table data and reprint it in the temporary register when the system is turned on.

The number of physical blocks in the flash memory can be segmented into a plurality of segment groups in order to match the storage capacity of the register.

There is a corresponding partition mapping table for each physical block in the segment area.

A character number in the mapping table can be recorded to map a corresponding memory block.

The number of memory physical blocks that can be mapped by a mapping table is one of 128 and 256 selectable.

The modified mapping table data can also be directly stored in a fixed mapping table data entity block page.

Description of drawings

1A is a schematic diagram of the structure of a general flash memory storage system;

FIG. 1B is a schematic diagram of the structure of a mapping table of a conventional flash memory;

FIG. 2A is a structural schematic diagram of a flash memory storage system of the present invention;

Fig. 2B is a schematic diagram of the mapping table structure of the flash memory of the present invention;

FIG. 2C is a structural schematic diagram of partial paging of the physical block of the flash memory according to the present invention;

Fig. 3 is the action flow diagram of flash memory of the present invention when accessing data: and

Fig. 4 is a flow chart of the present invention when constructing a mapping table.

Description of figure number:

11～19 Flash memory 20 Control device

21 Data Temporary Storage Area 211 First Temporary Storage

213 The second register 219 The Nth register

22 Temporary storage area controller 23 ECC logic circuit

24 Host Interface Controller 25 Microprocessor

26 Storage control logic circuit 29 Computer host

255 Mapping table 31～39 Flash memory

311 Partial pagination 40 Control device

41 Data temporary storage area 411 First temporary storage

413 Second register 419 Mapping table

42 Temporary storage area controller 43 ECC logic circuit

44 Host Interface Controller 45 Microprocessor

46 Storage control logic circuit 49 Computer host

Detailed ways

Please refer to FIG. 2A, which is a structural schematic view of the flash memory storage system of the present invention; at least one flash memory 31-39 is mainly connected with a computer host 49 by a control device 40 (of course, the control device 40 can also be Built in a subsystem of the host computer 49), the control device 40 includes a microprocessor 45, which can be controlled by a host interface that meets PCMCIA, IDE, ATA, MMC, SD, Compact Flash or its combined specification agreement The controller 44 is connected to the host computer 49, and one end of the microprocessor 45 can be connected to the data storage devices 31-39 through a storage control logic circuit 46; the microprocessor 45 can also be connected to a temporary storage area Controller 42, the temporary storage area controller 42 can control the host computer 49 to temporarily store the data to be accessed in a data storage area 41 (the first temporary register 411, the second temporary register 413 and the Nth temporary register 419 ). In addition, an ECC logic circuit 43 is respectively connected to the microprocessor 45, the temporary register controller 42 and the storage control logic circuit 46, which is controlled by the microprocessor 45 and gives a corresponding data magnetic area to be accessed. Error Correction Code ECC data. Wherein, part of the temporary register 419 of the data storage area 41 can be used as a mapping table 419 (mapping table) for storing data values PBA related to physical block addresses of each memory physical block.

Please refer to FIG. 2B. In the embodiment of the present invention, the mapping table 419 that records the corresponding memory physical block address data value PBA is registered in the partial register 419 added to the control device, which is a collocation register 419 or the paging (page) memory storage capacity of the physical block (B ₀ ) is 256bytes or 512bytes (that is, 128 or 256 characters) each character number W ₀ , W ₁ , ... W _m of the mapping table 419 All contain address values representing a corresponding block B ₀ , B ₁ , ... B _m , so a mapping table 419 can correspond to 128 or less than 256 memory physical blocks (B ₀ ), so the memory The total number of physical blocks can be divided into multiple partition groups (Seg ₀ ~ Seg _n ) in a timely manner, and the number of blocks (Block) contained in each segmented segemnet will be limited to 256 ( or within 128), of course, each segment has a special reserved block for recording mapping update (Mapping update) (as indicated by * in FIG. 2B or shown in FIG. 2C).

Each segment area Segement has a corresponding special reserved block for mapping update (the initial value of the mapping block is established when the system is initialized) to establish the data mapping relationship, when the computer When the host 49 wants to access the file data, the microprocessor 45 of the control device 40 will divide the LBA value imported by the host computer 49 by the value of the physical block contained in the partition, and then divide it by the magnetic area contained in the block (sector) number to obtain the mapping table in the segment segment that needs to be read in, and this partition mapping table is transferred to the mapping temporary register 419 by the latest update page of the special reserved block of the mapping update (Mapping update) , so as to facilitate the system to find out the address of the physical block that this LBA needs to map. In addition, each segment area Segement has a corresponding special reserved block for mapping update (Mapping update) to store the newly established data mapping relationship. When there is a block mapping data change, only this partition mapping update (Mapping update) will be updated ) specially reserves the latest page of the block, so it can effectively reduce the modification operation time of the entire mapping table, and can effectively reduce the occurrence of data error connection situations.

Since the mapping table 419 itself of the present invention is a storable data, when the registration data in the mapping table 419 is changed, this data can be stored in the entity area of a special reserved block for mapping update (Mapping update) Part of the block page 311, and this part of the page 311 is a data block marked with a special mark "*" that is not mapped, wherein the part of the page 311 is divided into a plurality of partition pages MT ₀ , MT ₁ , MT ₂ ... ..., MT _m , where m is the number of pages contained in the Block, please refer to Figure 2C, when the registration data in the mapping table 419 is changed, this data can be stored in a mapping update (Mapping update ) in the MT _n of the entity page 311 of the special reserved block, when updating again, the new mapping relationship will be stored in MT _n+1 , and when adding new login data, the new update mapping will be written down until When it is full, Erase this mapping update (Mapping update) special reserved block and start updating from page 0 again, so as to be the data that can be immediately reprinted in a temporary register 419 when the computer is turned on next time, so the present invention does not need to be stored as already used Generally, the system requires the host computer 49 to scan the logical address data of each block (L value in FIG. 1B ) to rebuild the search list. Therefore, not only the operating program of the host computer 49 can be omitted, but also the time for constructing the search list can be greatly saved.

Of course, the key point of the present invention is that the mapping table data can be stored in the paging of a physical block, so that it can be directly and quickly transferred to the mapping table memory when the system is turned on.

Furthermore, please refer to FIG. 3, which is a flow chart of the flash memory of the present invention when constructing a mapping table under a write (or read) operation: as shown in the figure, its main steps include:

Step 301, after the host computer or the control device is turned on or powered, the entire system is in a standby state;

Step 302, waiting for the host to issue a write command;

Step 303, the host computer needs to access the file data, the microprocessor of the control device processes the LBA data imported by the host computer to obtain which segment area the specified physical block address exists in, and The data of the partition mapping table of the segment area is transferred from a page of a physical block to a mapping register;

Step 304, the microprocessor finds the memory physical block corresponding to the file data that the computer host wants to access from the partition mapping table data, and transfers the data that the host side wants to write to the sector Buffer (magnetic sector temporary register) middle;

Step 305: Detect whether the write command is an overwrite condition from the written page in the old block compared to the address to be written, if not, write directly to the old block without updating the mapping relationship Get back to the standby state; if so, then perform step 305:

Step 306, indicating that a certain paging data in a physical block will be overwritten, first write the new data into a clean block reserved by the system;

Step 307, move the data previously stored in the old block and not changed into this clean block;

Step 308, erasing all the data in the original old block to become another clean memory physical block reserved by the system, and become a clean block to be used next time:

Step 309, changing the data value of the logical address of the above-mentioned related block in the corresponding mapping table, so as to establish a correct connection relationship between the two;

Step 310, updating the mapping table data of the temporary register to the next page in the special reserved block for mapping update, so that the control device can conveniently search and reprint the mapping table data when the computer is turned on next time.

Finally, please refer to Fig. 4, which is an action flow chart of the system of the present invention when the mapping table is to be constructed; as shown in the figure:

In step 401, the system obtains the address of the page mapping table that must be loaded through conversion through the processing of the control device; of course, in another embodiment, the control device can also directly find the address of the mapping table from a special mark;

Step 402, read the specified paging mapping table from a block specially reserved for unmapping:

Step 403, whether the ECC in the mapping table is wrong, if yes, it means that the last operation has experienced abnormal power failure or improper operation, and 404 needs to be executed; if not, it means that the operation is normal, then execute step 405;

Step 404, it means that an abnormal operation situation occurs, and it is necessary to look back on the response relationship of the previous mapping table, as long as the latest previous mapping page in the special reserved block of the mapping update (Mapping update) is re-read and stored in the memory;

Step 405, continue to execute system actions.

To sum up, it should be known that the present invention is related to a flash memory algorithm, especially a flash memory algorithm and its control that can quickly build tables and prevent data confusion derived from abnormal power failures. system. Therefore, the present invention is indeed novel, progressive, and can be used by the industry. It should undoubtedly meet the requirements of the invention patent application. I file an invention patent application in accordance with the law. I pray that the Bureau will grant the patent as soon as possible. I am very grateful.

However, what is described above is only a preferred embodiment of the present invention, and is not intended to limit the implementation scope of the present invention. That is, all equivalent changes and modifications made according to the shape, structure, characteristics and spirit described in the scope of the patent application of the present invention shall be included in the scope of the patent application of the present invention.

Claims (18)

1. A control system of a flash memory, which is mainly connected to a host computer and at least one flash memory by a control device, characterized in that the control device is provided with a plurality of temporary registers, and Part of the register can be used to load the mapping table data of the logical block address and the corresponding physical block address data value, and the mapping table data can be stored in a part of the physical block of the flash memory. 2. The control system according to claim 1, wherein the number of physical blocks in the flash memory can be segmented into a plurality of partition groups in order to match the storage capacity of the temporary register. 3. The control system according to claim 2, wherein each partition group has a corresponding page mapping table data, and the page mapping table data can be stored in the corresponding memory physical block page. 4. The control system according to claim 1, wherein the storage capacity of the mapping table is one of 256 bytes and 512 bytes. 5. The control system according to claim 4, wherein the number of memory physical blocks that can be mapped by a mapping table is one of 128 and 256 selectable. 6. The control system as claimed in claim 1, wherein a character number in the mapping table can be registered to map a corresponding memory block. 7. The control system as claimed in claim 1, wherein the register in which the mapping table can be registered is a data storage device. 8. The control system as claimed in claim 1, wherein the physical memory block storing the mapping table data is provided with a special mark. 9. An algorithm for a flash memory, which mainly stores a mapping table data that records the address data values of each physical block of the memory and the address of the corresponding logical block in a flash memory, When the system is turned on, the mapping table data can be directly transferred to a temporary register of the control device under the control of a control device. 10. The algorithm according to claim 9, further comprising the following steps: When you want to change the data stored in a physical block, you will first reprint the data that does not need to be changed in the block you want to change to a clean physical block that is available but has not yet stored other data, and then you will change it All the data in the block will be erased, and the relevant physical block address data will be directly changed in the mapping table of the temporary register, and the changed mapping table data will be stored in another part of the memory later in a physical block. 11. The algorithm according to claim 10, further comprising the following steps: after the data in the block to be changed has been erased, if abnormal operation occurs and the computer is restarted, control The device will reload the mapping table data previously stored in the physical memory block into the temporary register. 12. The algorithm according to claim 9, further comprising the following steps: Whether abnormal operation occurs is identified by the ECC data of the physical block storing the mapping table data. 13. The algorithm according to claim 9, further comprising the following steps: The mapping table data that records the link addresses of each physical block of the memory is stored in a partial page of a physical block of the memory, and the address of this partial page includes a special mark so that the system can immediately Search the page mapping table data and reprint it in the register. 14. The algorithm of claim 9, wherein the number of physical blocks in the flash memory can be segmented into a plurality of segment groups to match the storage capacity of the register. 15. The algorithm according to claim 13, wherein there is a partition mapping table corresponding to the physical block of each segment area. 16. The algorithm of claim 9, wherein a number of characters in the mapping table can be recorded to map a corresponding memory block. 17. The algorithm according to claim 9, wherein the number of memory physical blocks that can be mapped by a mapping table is one of 128 and 256 selectable. 18. The algorithm according to claim 9, wherein the modified mapping table data can also be directly stored in a fixed mapping table data entity block page.

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