CN1738206B - Non-inverting domino register and method for generating non-inverting output - Google Patents

Abstract

A domino register includes an arithmetic circuit, a write circuit, an inverter, a hold circuit, and an output logic circuit. The operation circuit precharges the first node and operates to control a logic function of a state of the first node when the clock signal goes high. During operation, the write circuit drives the second node high if the first node is low, and drives the second node low if the first node remains high. The inverter inverts the second node to control the state of the third node. The keeper circuit keeps the second node at a high level when the third node and the clock signal are both at a low level, and keeps the second node at a low level when the third node and the first node are both at a high level. Otherwise, the high and low paths of the keeper circuit are disabled, including when the write circuit changes state. Thus, the write circuit does not have to overcome a keeper element.

Description

Non-inverting domino register and method of generating non-inverting output

technical field

The present invention relates to the field of dynamic logic circuit and buffer function, and in particular to a non-inverting domino (domino) buffer, which can solve the output temporary storage problem of complex logic circuits whose speed and size are important factors.

Background technique

This application claims priority from US Provisional Application Serial No. 60/553805, filed March 17, 2004; which application is incorporated by reference. Claim of priority to this application is also based on US Patent Application Serial No. 11/023,145, filed 12/27/2004.

This application is a continuation of the following United States Patent Application, which has a common assignee and at least one common inventor with the present application, which application is also incorporated by reference.

serial number Application date Invention name 10/640369 (CNTR.2200) 8/13/2003 Non-inverting domino register Non-inverting domino register

Integrated circuits use a large number of registers, especially those with synchronous pipeline architectures. Temporary logic circuits are used to maintain the outputs of devices and circuits for a period of time so that they can be received by other devices and circuits. In a frequency system (such as a pipelined microprocessor), the register is used to latch the output signal of a given pipeline stage circuit, and at the same time maintain the output signal for one frequency cycle, so that the input circuit in the subsequent stage circuit A previous output signal may be received while the given pipeline stage circuit is simultaneously generating a new output.

In the past, before and after complex logic operation circuits, such as multiple-input multiplexers (muxes), multi-bit encoders, etc., buffers were often used to maintain the input signals to enter the evaluation circuits and the signals from the evaluation circuits. output signal. Generally, these registers have associated set-up time and hold-time requirements, and both of these requirements can limit the arithmetic circuits in the front-end circuit. In addition, the register also has a corresponding data-to-output time characteristic, which can limit the operation circuit in the subsequent circuit. The "speed" of a typical register is determined based on its data-output time, that is, its setting time plus frequency-output time.

The use of conventional register circuits before and after logic operation circuits creates delays in the pipeline system, the cumulative result of which will significantly slow down the operation speed. More particularly, among these delays, the significant source is the time requirement from the data terminal to the output terminal, which needs to satisfy the logic operation circuit to ensure stable temporary storage output. Therefore, the object of the present invention is how to reduce these delays so that extra time is added to each stage of the circuit, thereby increasing the speed of the entire pipeline system.

A known and related disclosure called "Non-Inverting Domino Registers," document number CNTR.2200, which is hereby incorporated by reference, addresses the above-mentioned problems. In this prior art, the non-inverting domino registers are described as The logic operation function will be combined with the corresponding register, and the frequency-output time of the traditional method without compromising the output stability can be achieved. Compared with the slower transition response of the traditional non-inverting domino register In contrast, the transitions of the output signal of the non-inverting domino registers disclosed herein appear to be very fast in response to the transitions of the frequency signal. However, the known non-inverting domino registers are not particularly useful for arithmetic logic circuits. flexibility, which must be an N-channel logic circuit. Furthermore, when implemented in a high-leakage or high-noise process such as 90 nanometer (nm) silicon-on-insulator (SOI)), Known non-inverting domino registers may have leakage current effects.

What would like to be proposed is an improved domino register which yields all the advantages of the known non-inverting domino registers and which will be more resilient to domino stages and which can be optimally used in high leakage current or high noise environments middle.

Contents of the invention

A non-inverting domino register according to an embodiment of the present invention includes a domino stage circuit, a write stage circuit, an inverter, a high level and a low level sustain path, and an output stage circuit. The domino stage circuit is used for executing a domino stage, and the domino stage operates a logic function based on at least one input data signal and a frequency signal. When the frequency signal is low, the domino stage will precharge the precharge node to high level, if it performs calculations, it will pull the precharge node to low level, and if it cannot operate, it will Keep the precharge node high. If the precharge node goes low, the write stage pulls the first preliminary output node high, and if the precharge node remains high, it pulls the first preliminary output node high. output node pulled low. The inverter inverts the first preliminary output node and generates a second preliminary output node. The high hold path, when enabled, keeps the first preliminary output node high, and the low hold path, when enabled, keeps the first preliminary output node low. flat. When both the frequency signal and the second primary output node are at low level, the high level maintaining path is enabled, otherwise it is not enabled. When the second preliminary output node and the pre-charge node are both high, the low-level sustain path is enabled, otherwise it is disabled. The output stage circuit is used to implement an output stage, and the output stage generates an output signal based on the states of the precharge node and the second preliminary output node.

The frequency-to-output time of the non-inverting domino register is faster than conventional methods without compromising the stability of its output. And further, the write stage circuit does not have to overcome the low or high sustain path to drive the first preliminary output node to the opposite state. For example, when the frequency signal becomes high level, if the first preliminary output node is high level and the domino stage circuit cannot operate, the writing stage circuit will operate, and the first preliminary output node will be pulled to low level. In this case, since the clock signal is high and the high sustain path is disabled, the write stage circuit does not have to overcome the high sustain path to drive the first preliminary output node to low level. In a specific embodiment, the clock signal drives a gate of a P-channel device in the high sustain path, wherein when the clock signal is high, the P-channel device is turned off. And further, the inverter will switch the second preliminary output node to high level in response to the switching of the first preliminary output node to low level, so as to enable the low level maintaining path, so as to During the remaining cycles, the states of the first preliminary output node and the second preliminary output node are maintained.

On the other hand, when the frequency signal becomes high level and the domino stage circuit operates, if the first preliminary output node is low level, the write stage circuit will operate, and the first preliminary output node node is pulled high. In this case, the write stage does not have to overcome the low sustain path because the precharge node will go low, disabling the low sustain path, And drive the first preliminary output node to a high level. In a specific embodiment, the pre-charge node will drive the gate of the N-channel element in the low-level sustain path, wherein when the pre-charge node is low level, the N-channel element will be turned off. Further, the inverter will respond to the first preliminary output node switching to a high level, and switch the second preliminary output node to a low level. In this case , when the frequency signal is high, the precharge node is low, which keeps the first preliminary output node high. When the frequency signal then goes low, the low level remains The path is enabled, which maintains the state of the first preliminary output node and the second preliminary output node during the remainder of the cycle.

The non-inverting domino circuit can be implemented in high leakage current environments using smaller and faster components than would otherwise have to overcome strong sustaining components. For example, the non-inverting domino stage circuit can use scaled 90nm silicon-on-insulator process or any other without compromising speed and requiring large components. Miniaturization process and integration.

The domino stage circuit can be implemented with a P-channel element, an N-channel element and arithmetic logic circuits. The P-channel device has a gate for receiving the frequency signal, and a drain and a source coupled between the source voltage and the precharge node. The N-channel device has a gate for receiving the frequency signal, a drain coupled to the precharge node, and a source. The operation logic circuit is coupled between the ground and the source of the N-channel device. This configuration enables the arithmetic logic to be implemented using complementary metal oxide semiconductor (CMOS) logic.

The write stage circuit includes a P-channel element, and first and second N-channel elements. The P-channel device has a gate coupled to the precharge node, and a drain and a source coupled between a source voltage and the first preliminary output node. The first N-channel device has a gate for receiving the frequency signal, a drain coupled to the first preliminary output node, and a source. A second N-channel element has a gate coupled to the precharge node, a drain coupled to the source of the first N-channel element, and a source coupled to ground. In one embodiment of this configuration, the high-level sustain path includes two additional P-channel elements. A second P-channel element has a gate coupled to the second preliminary output node, a source coupled to a source voltage, and a drain. The third P-channel element has a gate for receiving the frequency signal, and a drain and a source coupled between the drain of the second P-channel element and the first preliminary output node. In another embodiment of this configuration, the low-level sustain path includes the second N-channel element, and the third N-channel element, wherein the third N-channel element has a a gate, and a drain and a source coupled between the first preliminary output node and the drain of the second N-channel device.

A domino register according to an embodiment of the present invention includes an arithmetic circuit, a write circuit, an inverter, a hold circuit, and an output circuit. When a frequency signal is at low level, the operation circuit precharges the first node, and when the frequency signal becomes high level, it operates a logic function for controlling a state of the first node. When the frequency signal becomes high, if the first node is low, the writing circuit will drive the second node to high, and if the first node remains high, its will drive the second node low. The inverter has an input coupled to the second node, and an output coupled to a third node. When the third node and the frequency signal are both at low level, the sustain circuit will keep the second node at high level, and when the third node and the first node are at high level, it will keep the The second node remains low. The output circuit generates an output signal based on the states of the first node and the third node.

The operation circuit includes a P channel element, an N channel element and a logic circuit. The operation logic circuit operates the logic function based on at least one input data signal. When the frequency signal becomes a high level, the N channel element and the P The channel elements all receive the frequency signal, and jointly enable the logic circuit to control the state of the first node. The P channel element (which is coupled to the first node), when the frequency signal is When low, it precharges the first node to high. In one aspect, the logic circuit is coupled to the first node, and the N-channel element is coupled between the logic circuit and ground. In another aspect, the N-channel element is coupled to the first node, and the logic circuit is coupled between the N-channel element and ground. In this latter footless aspect, the logic circuit may be CMOS components (instead of N-channel components) to implement.

The writing circuit includes a P-channel element, and first and second N-channel elements. The P-channel element is coupled to the first node and the second node, and when the first node goes low, it pulls the second node high. The first N-channel element is coupled to the second node for receiving the frequency signal, and the second N-channel element is coupled to the first N-channel element and the first node. When the frequency signal becomes a high level, if the first node remains at a high level, the first and second N-channel elements will jointly pull the second node to a low level. In this case, the sustain circuit may include second and third P-channel elements, and a third N-channel element. The second and third P-channel elements are coupled together and will be coupled to the second and third nodes, which will jointly form a high state maintenance path, when the third node and the frequency signal are both low When the voltage is low, it will be enabled, and the second node will be pulled to a high level, otherwise it will be disabled. The third N-channel element is coupled to the second and third nodes, and is coupled to the second N-channel element. The second and third N-channel elements jointly form a low-level state maintenance path, which is enabled when the first and third nodes are both high, and pulls the second node low , otherwise it will not be enabled.

The arithmetic circuit, write circuit, inverter, sustain circuit and output circuit can be integrated using a scaled 90nm silicon-on-insulator process as previously described.

A non-inverting domino register according to another aspect of the present invention includes a P-channel element, an N-channel element, an arithmetic logic circuit, a write stage circuit, a sustain circuit, and an output stage circuit. The P-channel device has a gate for receiving a frequency signal, and a drain and a source coupled between the source voltage and the precharge node. The N-channel device has a gate for receiving the frequency signal, a drain coupled to the precharge node, and a source. The arithmetic logic circuit, which operates a logic function based on at least one input data signal, is coupled between the source of the N-channel element and ground, and is implemented as a CMOS logic circuit. The writing stage circuit is used to drive the first primary output node, and includes a first pull-up element and a first pull-down element both responsive to the precharge node, and a second pull-down element responsive to the frequency signal. The sustain circuit has an input coupled to the first preliminary output node and an output for driving the second preliminary output node. The output stage circuit is used to drive the output node, and includes a second pull-up element and a third pull-down element both responding to the precharge node, and a third pull-up element and a fourth pull-down element both responding to the second preliminary output node element. The operational logic (which is implemented in a bottomless domino stage) is implemented in CMOS logic, thereby resulting in a significantly better input level noise margin than known arrangements requiring N-channel logic.

According to an embodiment of the present invention, the method for temporarily storing a logic function and generating a non-inverted output includes precharging the first node to a high level when a frequency signal is at a low level, and precharging the first node to a high level when the frequency signal becomes a high level. Usually, a logic function is calculated to control the state of the first node, when the frequency signal becomes high level, the state of the first node is used to control the state of the second node, and the state of the third node is defined as the state of the first node The inverting state of the two nodes, when the first node and the third node are both high, will enable the low-level state maintenance path to maintain the low-level state of the second node, otherwise the The low-level state maintenance path is disabled. When the frequency signal and the third node are both low-level, the high-level state maintenance path will be enabled to maintain the high-level state of the second node, otherwise the The high level state keeps the path disabled, and determines the state of the output node based on the states of the first node and the third node.

The method may include pulling the first node to a low level when the logic function is operating, and keeping the first node at a high level when the logic function cannot be operated. The method may include when When the frequency signal becomes a high level, if the first node is pulled to a low level, the second node will be pulled to a high level, and if the first node remains at a high level, the second node will be pulled to a high level. The node is pulled to a low level. The method may include controlling a first serial pull-down element and a second serial pull-down element with the first node and the third node respectively. The method may include using the frequency signal and the The third node, to control the first series pull-up element and the second series connection pull-up element. The method may include performing a state of the first node and the third node with a NAND function. logical combination.

Description of drawings

Benefits, characteristics, and advantages of the present invention will be better understood after referring to the following description and accompanying drawings, wherein:

FIG. 1 is a schematic diagram of a non-inverting domino register implemented according to the prior art which will be incorporated by reference;

Figure 2 shows a timing diagram of the operation of the non-inverting domino registers of Figures 1, 3, 4 and 5;

3 is a schematic diagram of a bottomless non-inverting domino register implemented according to an exemplary embodiment of the present invention;

4 is a schematic diagram of another non-inverting domino register implemented in accordance with an exemplary embodiment of the invention using improved storage stage circuitry; and

5 is a schematic diagram of a bottomless non-inverting domino register implemented using the improved storage stage circuit of FIG. 4 and an exemplary embodiment of the present invention.

Wherein, the reference signs are explained as follows:

100, 300, 400, 500 non-inverting domino registers

101, 105 nodes

103 A group of N nodes

104, 301 Operational Logic Circuits

107 first intermediate output node

109A, 109B, 401 inverters

111 second intermediate output node

113 output nodes

403 NAND gate

Detailed ways

The following description is presented to enable one of ordinary skill in the art to make and use the invention, as provided in the context of specific embodiments and its requirements. However, various modifications to this preferred embodiment will be apparent to those skilled in the art, and the general principles discussed herein can be applied to other embodiments as well. Thus, the present invention is not limited to the specific embodiments shown and described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

The inventors of the present invention have realized the need for critical factors such as speed, size and stability for temporary storage outputs for logic circuits, which are flexible for arithmetic logic circuits, and which can be used in high leakage current or high noise environments. Therefore, it proposes an inverting domino register, which can have a faster data-to-output time without compromising output stability, which is flexible for arithmetic logic circuit implementations, and which can be used for high-leakage In the current or high noise environment, as will be further described below with reference to FIGS. Non-inverting domino registers allow a significant increase in the speed of operation of all components. All components can be used in higher leakage or high noise processes without compromising speed and without requiring large components to overcome sustaining components. Faster or smaller components to implement.

FIG. 1 is a schematic diagram of a non-inverting domino register 100 implemented according to the prior art CNTR.2200. The non-inverting domino register 100 includes a logic operation input stage circuit (or called a domino stage circuit), which includes stacked P-channel elements P1 and N-channel elements N2 , and an operation logic circuit 104 . The P1 element and the N2 element are a complementary pair of operand elements, which are coupled to either side of the arithmetic logic circuit 104 in the stack. Arithmetic logic 104 can be as simple as a single N-channel element, or can be significantly more complex for operating any desired logic function. The source of P1 is coupled to a voltage source VDD, and the drain is coupled to node 105 where signal TOP is generated. The arithmetic logic circuit 104 is coupled between the node 105 and the drain of N2 (which has a source coupled to ground). The input clock signal CLK is transmitted to the gates of P1 and N2 via the node 101 . A group of N nodes 103 transmits N input data signals DATA to the operation logic circuit 104 , where N is any positive integer.

The domino stage circuit of the non-inverting domino register 100 follows the storage stage circuit, which includes elements P2 , N3 and N4 , and a weak sustain circuit 109 . The elements P2, N3, and N4 can be regarded as "write-level circuits", and the sustain circuit 109 is a sustain-level circuit in the storage-level circuit. Node 101 is coupled to the gate of N3, and node 105 is coupled to the gates of P2 and N4. The source of P2 is coupled to VDD, and its drain is coupled to the first intermediate output node 107 which generates the first intermediate output signal QII. Node 107 is coupled to the drain of N3, the input of an inverter 109A, and the output of another inverter 109B. The output of inverter 109A is coupled to a second intermediate output node 111 that generates a second intermediate output signal QI, which is an input coupled to inverter 109B. Inverters 109A and 109B are mutually coupled between nodes 107 and 111 and together form weak sustain circuit 109 . The source of N3 is coupled to the drain of N4 (which has a source coupled to ground).

The storage stage circuit of the non-inverting domino register 100 is followed by an additional output stage circuit, which includes P-channel elements P3 and P4, and N-channel elements N5 and N6. Node 105 is coupled to the gates of P4 and N6, and node 111 is coupled to the gates of P3 and N5. The sources of P3 and P4 are coupled to VDD, and their drains are coupled together at the output node 113 where the output signal Q is generated. Output node 113 is coupled to the drain of N5 (which has a source coupled to N6 (which has a source coupled to ground). P-channel elements are generally used as pull-up elements, and N-channel elements are generally used as pull-down elements.

FIG. 2 shows a timing diagram of the operation of the non-inverting domino register 100, where the CLK, DATAN, TOP, QII, QI, and Q signals are plotted versus time. Relative transition times are estimated and delays are ignored. The DATAN signal is shown as a single signal representing a population combination of N DATA signals. When the population state of the data signal enables the operation logic circuit 104 to operate, thereby pulling TOP to a low level, the DATAN signal is shown as a high level, and when the operation logic circuit 104 cannot perform operations (it will keep the TOP signal at When high level), the DATAN signal is displayed as low level. At time T0, when the CLK signal is initially low, N2 turns off and P1 turns on, so that the domino circuit precharges the TOP signal high. The TOP signal will be precharged to a high level, and after the rising edge of CLK, it will be ready to operate the DATAN signal through the operation logic circuit 104, wherein the DATAN signal is initially at a high level. The precharged TOP signal will turn on N4 and N6. The QII signal will remain at the previous state (initially shown as a low logic state) and will be held there by hold circuit 109 . The QI signal is initially high and turns on N5, so that the Q output signal is initially pulled low via the N5 and N6 elements.

At time T1, the CLK signal will go high, because the DATAN signal is high, so it can discharge the TOP signal to go low. In particular, N2 will be turned on, and the arithmetic logic circuit 104 will Calculate through N2, and pull TOP to low level and ground point. QII signal will be pulled to high level through P2, and Q signal will be pulled to high level through P4. QII and Q signal will be pulled to high level at about time T1 At the same time, it will be pulled high, and QI will be pulled low by inverter 109A. The inverted state of the QI signal at the output of the maintenance circuit 109 will drive elements P3 and N5. When QI is high, P3 will be turned off, and N5 will be turned on; and when QI is low, P3 will be turned on, and N5 will be turned off. At the next time T2, when the CLK signal then becomes low, the TOP signal will be grounded again Pre-charged to a high level. P2 and N3 will be closed, so that the node 107 will not be driven into either state. However, the respective states of the QII and QI signals will be maintained by the operation of the maintenance circuit 109, so that at For all remaining half cycles of CLK, the Q and QII signals will remain high, while the QI signal will remain low.

While the CLK signal is still low, DATAN is shown transitioning low at time T3, and while the DATAN signal is low, the CLK signal then goes high at time T4. Since the operation logic circuit 104 cannot perform operations, TOP is still at high level when CLK is at high level. The CLK and TOP signals will respectively turn on the elements N3 and N4, so that at about time T4, the QII signal will turn to a low level, so the QI signal will be pulled to a high level by the inverter 109A. The TOP signal is at a high level, which keeps N6 turned on. The QI signal turns on N5 and turns off P3, so that the Q signal is pulled low via N5 and N6. At time T5, the CLK signal will then go low, causing TOP to be pulled high again. The respective states of the QII and QI signals are kept unchanged through the operation of the sustain circuit 109 . Since QI will keep N5 on and TOP will keep N6 on, the Q signal will remain low for all remaining cycles of CLK.

When the ALU 104 discharges the TOP signal low for evaluation, the Q signal transitions from low to high relatively quickly in response to the rising edge of the CLK signal. A negligible delay through elements N2 and P4 causes the output to transition. When the operation logic circuit 104 is unable to perform calculations and the TOP signal leaves the high level, the Q signal responds to the rising edge of the CLK signal, and after a negligible delay through the elements N3, N5 and the inverter 109A, it will switch from the high level to the high level. transition state to low level. The delay through inverter 109A can be minimized by implementing it as a relatively small component (with minimal capacitance), since it need not be large, nor need to perform the function of a buffer. Those of ordinary skill in the art will appreciate that transitions of the output Q signal of the non-inverting domino register 100 respond very quickly to transitions of the CLK signal. If a non-inverting output is required or desired, the non-inverting domino register 100 results in superior data-to-output speed compared to conventional designs among other benefits and advantages. The non-inverting domino register 100 can be converted to an inverting domino register simply by adding an output inverter/buffer (not shown).

AND (AND) logic and OR (OR) logic (not shown here) exemplified in the prior art CNTR.2200 can be used as the operation logic circuit 104 . As stated therein, any suitable combination of AND-OR logic circuits is contemplated, and any other complex logical operation circuits are contemplated, including, for example, multiple-input multiplexers, multi-bit encoders, and the like. Any desired simple to complex arithmetic logic circuit may be used in place of arithmetic logic circuit 104 as long as it does not adversely affect the speed of non-inverting domino register 100 or the associated power constraints. The AND and OR logic circuits are just examples and are used to show that the operation logic circuit 104 can be any complex logic operation circuit as understood by those of ordinary skill in the art. However, a possible limitation of the non-inverting domino register 100 is that it is not particularly flexible with respect to the arithmetic logic circuit 104, which typically must be implemented as an N-channel logic circuit. N-channel logic does not produce the optimum level for the input noise margin.

FIG. 3 is a schematic diagram of another non-inverting domino register 300 implemented according to an exemplary embodiment of the present invention. In addition to including stacked P-channel element P1 and N-channel element N2, and the logic operation input of the operation logic circuit 104 stage circuit, or domino stage circuit, the non-inverting domino register 300 is substantially similar to the non-inverting domino register 100, which will be recorded as a "footless" configuration, and the arithmetic logic circuit 104 is based on the arithmetic logic circuit 301 instead. The P1 and N2 elements are complementary pairs of operands that are coupled together at node 105 where the TOP signal is generated. In this case, the drain of N2 is coupled to node 105 and its The source is coupled to the top or upper end of the operational logic circuit 301. The lower or bottom end of the operational logic circuit 301 is coupled to the ground point. In this way, if the operational logic circuit 301 is coupled between P1 and N2, its would be at the foot of the P1/N2 stack. For the non-inverting domino register 300, the operation is substantially similar, and the timing diagram of Figure 2 is still valid.

The arithmetic logic circuit 301 can be configured in substantially the same manner as the arithmetic logic circuit 104 . However, as understood by those skilled in the art, the arithmetic logic circuit 301 may alternatively be implemented using complementary metal oxide semiconductor (CMOS) logic circuits (rather than N-channel logic circuits). Furthermore, the timing diagram of FIG. 2 is still efficient. When CMOS logic is used for domino stages, CMOS logic produces significantly better input-level noise margins than N-channel logic, such that a non-inverting domino register 300 produces a non-inverting domino register 100 Significantly better input level noise margin.

Both non-inverting domino registers 100 and 300 experience leakage current effects when implemented in high leakage current or high noise processes such as 90nm SOI and similar processes. Shrinking circuits to 90nm creates problems with leakage currents. Due to the shortened channel length, the scaled down process exhibits higher leakage current. Therefore, in order to write a new state to node 107 of the storage stage circuit in either of registers 100 and 300, within the feedback inverter, weak elements must be overcome (e.g., in inverter 109B, a weak P-channel elements will change to a low state, and weak N-channel elements will change to a high state). The cost of overcoming components is speed and current. Additionally, in processes with high leakage current or high noise, the weak N and P elements in the feedback inverter 109B must be large to maintain the state of the output node in the presence of leakage current or noise.

Note that, for example, when CLK is low, the storage node 107 (signal QII) is isolated from the input stage circuitry. The QII signal is not driven except for maintaining the feedback inverter 109B, which includes internal weak N and P elements (not shown). However, due to the increased leakage current corresponding to the scaling process, a larger amount of leakage current flows through the P2 and N3 elements. Therefore, the N and P elements in the inverter 109B must be large enough to overcome the leakage current. For example, if the QII signal is at a high level, the leakage current will flow to the ground through the N3 and N4 elements, so that the P element in the inverter 109B must be large enough to supply enough current to overcome the leakage current, and Keep the QII signal high. In processes where there is high leakage or high current, and the device is off, wider and wider devices are required to maintain state. Also, using wider elements substantially reduces performance because when a new state is written, the wider elements that are holding that state must be overcome. To compensate for the speed reduction, storage stage circuit elements P2, N3, and N4 are made larger to drive new states that overcome the states held by the larger elements in sustain feedback inverter 109B. Larger components consume useful space on an integrated circuit (IC).

4 is a schematic diagram of another non-inverting domino register 400 implemented in accordance with an exemplary embodiment of the present invention using an improved sustain circuit. The non-inverting domino register 400 includes an input domino stage followed by a storage stage Circuitry and Output Stage Circuitry. The domino stage circuit in register 400, and the initial portion of the storage stage circuit are similar to those in register 100. However, the sustain circuit of register 400 overcomes the need for components by removing, and in terms of speed and Current point of view, to reduce cost, and modified to improve performance. Domino stage circuit includes stacked P-channel element P1 and N-channel element N2, and arithmetic logic circuit 104. As before, P1 and N2 elements are complementary pairs The operand is coupled to either side of the ALC 104 between the voltage source VDD and ground. The source of P1 is coupled to VDD and its drain is coupled to node 105 where the TOP signal is generated. The operation logic circuit 104 is coupled between the node 105 and the drain of N2, and the source of N2 is coupled to the ground point. The input frequency signal CLK is transmitted to the gates of P1, N2 and N3 through the node 101. A set of N Node 103 will transmit N input data signals DATA to the operation logic circuit 104. As before, node 105, which will generate the TOP signal, is coupled to the gates of elements P2 and N4. The initial part of the storage stage circuit is substantially the same A write stage circuit comprising stacked components P2, N3, and N4. The source of P2 is coupled to VDD, and its source is coupled to node 107, which generates the first intermediate output signal QII. The drain of N3 is coupled to is connected to node 107 and its source is coupled to the drain of N4 (which has its source coupled to ground).

The storage stage circuit of the non-inverting domino register 400 includes a write stage circuit (including elements P3 , P4 , and P5 ), a sustain stage circuit (including elements P3 , P4 , and N3 ), and an inverter 401 . In the illustrated embodiment, the storage stage circuit is followed by the output stage circuit, which includes a two-input NAND gate 403 . In this case, the source of P3 is coupled to VDD and its drain is coupled to the source of P4 (whose drain is coupled to the drain of N5 at node 107 ). The source of N5 is coupled to the drain of N4, which is further coupled to the source of N3. Node 101, which generates the CLK signal, is coupled to the gate of P4. Node 107, which generates the QII signal, is coupled to the input of an inverter 401 whose output is coupled to node 111, which generates the second intermediate output signal QI. Node 111 is coupled to the gates of P3 and N5 and is coupled to an input of NAND gate 403 . The node 105 that generates the TOP signal is coupled to the other input of the NAND gate 403 , and the output of the NAND gate 403 generates the output Q signal.

In this case where there are only minor differences in timing, the timing diagram of FIG. 2 can be applied to non-inverting domino register 400, where such timing differences and minor delays (e.g., passing through inverter 401 and NAND gates are ignored). 403 delay). Again, it will be assumed that the QII signal is initially low and will be enabled high. Referring to FIG. 2, at time T0, the CLK, Q, and QII signals are initially low, while the QI signal is high. Because CLK is at low level, P1 will be turned on, and TOP will be pre-charged at high level, so that N4 will be turned on. The Q signal at the output of NAND gate 403 is initially low because both QI and TOP are high. When CLK is low and QI is high, N5 is on, P3 is off, and P4 is on. Thus, in this case, both N5 and N4 are on a path that provides a "low" state maintenance path from node 107 to ground, which keeps the QII signal low. Whenever the second preliminary output node 111 and the pre-charge node 105 are both high, the low sustain path is enabled, otherwise it is disabled.

When the CLK signal becomes high level at time T1, N2 is turned on, and the operation of the DATA operand is started by the operation logic circuit 104 . As before, the DADAN signal representing the input DATA operand will initially assert a high level, causing ALU 104 to be coupled to node 105 , which in turn is coupled to the drain of N2 . This pulls the TOP signal low via N2. At about time T1 (after a short delay by NAND gate 403 ), TOP going low turns on NAND gate 403 and enables Q to go high. Furthermore, TOP going low turns off N4, thereby disabling the low sustain path from N5, through N4, and down to ground. Moreover, TOP that becomes low level will turn on P2, so that at about time T1, the QII signal will be pulled to high level. When the QII signal goes high at time T1, the inverter 301 pulls the QI signal low, which turns on P3 and turns off N5. When the QI signal is low, the Q output signal will remain low.

In this example, when the TOP signal goes low, the low-hold path through N5 is disabled because N4 is turned off. Also, since N4 will be off, P2 does not have to overcome N5 to pull the QII signal high. Whenever the QII signal is low and pulled high in response to the operation (pulling TOP low), the low level maintenance path will always be disabled (because N4 will be closed), so that the storage stage The write stage in the circuit does not have to overcome sustain elements.

At time T2, when CLK then goes low, TOP will be pre-charged high again. Furthermore, at time T2, P4 will be turned on, and a voltage from node 107 to VDD will be generated through P4 and P3. The "high" state maintains the path, thereby keeping the QII signal high. Whenever the precharge node 105 and the second preliminary output node 111 are both low, the high maintain path is enabled, otherwise will not be enabled. Therefore, when TOP becomes high at time T2, the QII signal will remain at high level, which in turn will keep QI at low level to maintain the state of the Q output signal. At about time T2 , the TOP signal going high turns N4 on, but because the QI signal is low, N5 turns off, thus keeping the low sustain path off or disabled during the remainder of the cycle.

At time T3, the DATAN signal becomes low level, and at time T4, the CLK signal then becomes high level, and the DATAN signal is still low level, so that the operation logic circuit 104 cannot perform operations. Therefore, at time T4, TOP will remain at a high level, so that N4 will remain turned on. A CLK signal going high turns off P4 and turns on N3. Since P4 will be off, and both N3 and N4 will pull the QII signal low, the sustain high path from node 107 to VDD will be disabled. Because P4 will be turned off, N3 and N4 do not need to overcome any components (including weak sustain components), but will pull QII low. Whenever the QII signal is high and pulls low in response to the inability to operate (where TOP will remain high), the high-level maintenance path will always be disabled (because P4 will be closed), so that The write stage circuit in the storage stage circuit does not have to overcome the sustain element. At about time T4, the inverter 401 will pull QI to a high level in response to QII going low. Because both QI and TOP are at high level, at about time T4, the NAND gate 403 will pull Q to low level. Furthermore, QI going high turns on N5 and turns off P3 so that the high sustain path is disabled and the low sustain path through N5 and N4 is re-enabled. When CLK goes low at time T5, N3 will be turned off, and because N5 and N4 will remain on, QII will remain low through the low-level sustain path. Both TOP and QI are kept at a high level, so that Q will remain at a low level during the remaining frequency cycles of CLK.

Non-inverting domino register 400 uses an improved technique to disable weak sustain feedback elements so that strong elements inside sustain elements do not have to be overcome when a new state is being written. Therefore, the P3 and N5 elements will be made wider to overcome the leakage current to maintain the state, but because those same elements P3 and N5 will be disabled when a new state is written to the storage node 107 (QII signal), it will not will affect the speed. When writing a new state of the QII signal, it is not necessary to overcome the feedback sustain circuit, so that elements P2 and N3 can be normal sized elements. The "keeper" of the non-inverting domino register 400 is only enabled to store this state. Specifically, the feedback element is enabled to maintain this state, and is disabled when writing a new state.

FIG. 5 is a schematic diagram of an improved sustain stage circuit using a register 400 and another bottomless non-inverting domino register 500 according to another exemplary embodiment of the present invention. The non-inverting domino register 500 is substantially similar to the non-inverting domino register 400, except that it includes a stack of P-channel elements P1 and N-channel elements N2, and a logic operation input stage circuit of the operation logic circuit 104, or a domino stage circuit, It would be noted as a "bottomless" configuration, and the ALD 104 is replaced by the ALD 301 . The change from cache 500 to 400 is similar to the change from cache 300 to 100 . In this way, the operation logic circuit 301 of the non-inverting domino register 500 can be implemented in CMOS logic circuits instead of N-channel logic circuits, and moreover, the timing diagram of FIG. 2 is still applicable. As previously stated, when CMOS logic is used in a domino stage, CMOS logic produces a significantly better input-level noise margin than N-channel logic, so that the non-inverting domino register 500 performs better than the non-inverting domino register 500. Domino register 400 produces a slightly better input level noise margin.

Without compromising the stability of its output Q, the frequency-to-output time of the non-inverting domino register implemented according to an embodiment of the present invention is faster than conventional methods. In addition, storage stage circuits can be further improved to allow smaller, faster devices to be used in high leakage current environments compared to other devices that would have to overcome strong sustaining devices. This allows non-inverting domino registers to be implemented in high-leakage or high-noise processes such as 90nm SOI and similar processes without performance degradation due to leakage. Therefore, the advantages of a scaling process (including reducing size, voltage, power consumption, etc.) can be achieved without causing performance degradation corresponding to such scaling process.

Although the present invention and its objects, features and advantages have been described in detail, the present invention may also include other embodiments and variations. In addition, although the disclosed embodiments of the present invention utilize metal oxide semiconductor (MOS) type devices (which include complementary metal oxide semiconductor (CMOS) and similar devices, such as NMOS and PMOS transistors, etc.), it can still be Implemented using similar aspects or analog technology types and structures, such as bipolar components and the like. Finally, although the present invention is the best mode for carrying out the purpose of the present invention, those skilled in the art should understand that, without departing from the spirit and scope of the present invention defined by the appended claims, its The conception and specific embodiment disclosed may be immediately used as a basis for designing or modifying other structures for the same purposes of the present invention.

Claims (21)

1. noninverting domino register comprises:

One domino level circuit, in order to carry out a domino level, this domino level is based at least one input data signal and a frequency signal, come computing one logical function, wherein when this frequency signal was low level, this domino level can be a high level with a precharged node preliminary filling, if it carries out computing, then can move this precharged node to low level, and, then can make this precharged node remain on high level if it can't computing;

One writes a grade circuit, be coupled to this domino level circuit and write level to carry out one, this writes level and can respond this frequency signal, if this precharged node becomes low level, then it can move one first preliminary output node to high level, and if this precharged node remains on high level, then it can move this first preliminary output node to low level;

One inverter has an input that is coupled to this first preliminary output node, and an output that is coupled to one second preliminary output node;

One high level is kept the path, and when activation, it can make this first preliminary output node remain on high level, and wherein when this frequency signal and this second preliminary output node are low level, this high level is kept the path can activation, otherwise it can not activation;

One low level is kept the path, and when activation, it can make this first preliminary output node remain on low level, and wherein when this second preliminary output node and this precharged node are high level, this low level is kept the path can activation, otherwise it can not activation; And

One output-stage circuit, in order to carry out an output stage, this output stage produces an output signal based on the state of this precharged node and this second preliminary output node.

2. noninverting domino register as claimed in claim 1, wherein this domino level circuit comprises:

One P element in channel has in order to receiving a grid of this frequency signal, and is coupled to drain electrode of one between one source pole voltage and this precharged node and source electrode;

The arithmetic logic circuit is coupled to this precharged node; And

One N element in channel has in order to receiving a grid of this frequency signal, and is coupled to drain electrode of one between this arithmetic logic circuit and the earth point and source electrode.

3. noninverting domino register as claimed in claim 1, wherein this domino level circuit comprises:

One P element in channel has in order to receiving a grid of this frequency signal, and is coupled to drain electrode of one between one source pole voltage and this precharged node and source electrode;

One N element in channel has in order to a grid that receives this frequency signal, a drain electrode and an one source pole that is coupled to this precharged node; And

The arithmetic logic circuit is coupled between this source electrode of earth point and this N element in channel.

4. noninverting domino register as claimed in claim 1, wherein this writes a grade circuit and comprises:

One the one P element in channel has a grid that is coupled to this precharged node, and is coupled to drain electrode of one between one source pole voltage and this first preliminary output node and source electrode;

One the one N element in channel has in order to a grid that receives this frequency signal, a drain electrode and an one source pole that is coupled to this first preliminary output node; And

One the 2nd N element in channel, a drain electrode of this source electrode that have the grid that is coupled to this precharged node, is coupled to a N element in channel and the one source pole that is coupled to earth point.

5. noninverting domino register as claimed in claim 4, wherein this high level is kept the path and is comprised:

One the 2nd P element in channel has a grid that is coupled to this second preliminary output node, the one source pole that is coupled to this source voltage and a drain electrode; And

One the 3rd P element in channel has in order to receiving a grid of this frequency signal, and is coupled to this drain electrode of the 2nd P element in channel and a drain electrode and the source electrode between this first preliminary output node.

6. noninverting domino register as claimed in claim 5, wherein this low level is kept the path and is comprised the 2nd N element in channel, and one the 3rd N element in channel, it has a grid that is coupled to this second preliminary output node, and is coupled to a drain electrode and the source electrode between this drain electrode of this first preliminary output node and the 2nd N element in channel.

7. domino register comprises:

One computing circuit, when a frequency signal is low level, its can preliminary filling one first node, and when this frequency signal becomes high level, it understands the logical function of computing in order to a state of controlling this first node;

One write circuit, be coupled to this first node and in order to receive this frequency signal, when this frequency signal becomes high level, if this first node is a low level, then it can drive a Section Point and be high level, and if this first node remains on high level, then it can drive this Section Point and be low level;

One inverter has an input that is coupled to this Section Point, and an output that is coupled to one the 3rd node;

One keeps circuit, be coupled to this Section Point and the 3rd node, and this write circuit, when the 3rd node and this frequency signal are low level, it can make this Section Point remain on high level, and when the 3rd node and this first node were high level, it can make this Section Point remain on low level; And

One output circuit, it produces an output signal based on the state of this first node and the 3rd node.

8. domino register as claimed in claim 7, wherein this computing circuit comprises:

One P element in channel is coupled to this first node and in order to receive this frequency signal, when this frequency signal was low level, it can be a high level with this first node preliminary filling;

One logical circuit is coupled to this first node, and it comes this logical function of computing based at least one input data signal; And

One N element in channel is coupled between this logical circuit and the earth point, and in order to receive this frequency signal;

Wherein when this frequency signal became high level, this P element in channel and this N element in channel can jointly make this logical circuit activation, to control this state of this first node.

9. domino register as claimed in claim 7, wherein this computing circuit comprises:

One P element in channel is coupled to this first node and in order to receive this frequency signal, when this frequency signal was low level, it can be a high level with this first node preliminary filling;

One N element in channel is coupled to this first node, and in order to receive this frequency signal; And

One logical circuit is coupled between this N element in channel and the earth point, and it comes this logical function of computing based at least one input data signal;

Wherein when this frequency signal became high level, this P element in channel and this N element in channel can jointly make this logical circuit activation, to control this state of this first node.

10. domino register as claimed in claim 7, wherein this write circuit comprises:

One the one P element in channel is coupled to this first node and this Section Point, and when becoming low level as if this first node, it can move this Section Point to high level;

One the one N element in channel is coupled to this Section Point and in order to receive this frequency signal; And

One the 2nd N element in channel is coupled to a N element in channel and this first node;

Wherein a N element in channel and the 2nd N element in channel can respond this frequency signal and become high level, if this first node still is a high level, then can jointly move this Section Point to low level.

11. domino register as claimed in claim 7, wherein this holding circuit comprises:

The second and the 3rd P element in channel, be coupled in together, and can be coupled to this Section Point and the 3rd node, it can form a high level state jointly and keep the path, when the 3rd node and this frequency signal are low level, its meeting activation, and this Section Point can be moved to high level, otherwise its not activation of meeting; And

One the 3rd N element in channel, be coupled to this Section Point and the 3rd node, and can be coupled to the 2nd N element in channel, wherein the 2nd N element in channel and the 3rd N element in channel can form a low level state jointly and keep the path, when this first node and the 3rd node are high level, its meeting activation, and this Section Point can be moved to low level, otherwise it can not activation.

12. a noninverting domino register comprises:

One the one P element in channel has in order to receiving a grid of a frequency signal, and is coupled to drain electrode of one between an one source pole voltage and the precharged node and source electrode;

One the one N element in channel has in order to a grid that receives this frequency signal, a drain electrode and an one source pole that is coupled to this precharged node;

The arithmetic logic circuit is coupled between this source electrode and earth point of a N element in channel, and comprises complementary MOS integrated circuit, and it comes computing one logical function based at least one input data signal;

One writes a grade circuit, write level and drive one first preliminary output node in order to carry out one, this write grade comprise all can respond this precharged node one first on draw element and one first drop down element, and one second drop down element that can respond this frequency signal;

One keeps circuit, has an input that is coupled to this first preliminary output node, and in order to drive an output of one second preliminary output node; And

One output-stage circuit, in order to carry out an output stage and to drive an output node, this output stage comprise all can respond this precharged node one second on draw element and one the 3rd drop down element, and all can respond this second preliminary output node one the 3rd on draw element and one the 4th drop down element.

13. noninverting domino register as claimed in claim 12, wherein this writes a grade circuit and comprises:

One the 2nd P element in channel has a grid that is coupled to this precharged node, and is coupled to drain electrode of one between this source voltage and this first preliminary output node and source electrode;

One the 2nd N element in channel has in order to a grid that receives this frequency signal, a drain electrode and an one source pole that is coupled to this first preliminary output node; And

One the 3rd N element in channel, a drain electrode of this source electrode that have the grid that is coupled to this precharged node, is coupled to the 2nd N element in channel and the one source pole that is coupled to earth point.

14. noninverting domino register as claimed in claim 13, wherein this holding circuit comprises the pair of phase inverters that is coupled to mutually between this first preliminary output node and this second preliminary output node.

15. noninverting domino register as claimed in claim 12, wherein this output-stage circuit comprises:

One the 2nd P element in channel has a grid that is coupled to this precharged node, and is coupled to drain electrode of one between this source voltage and this output node and source electrode;

One the 3rd P element in channel has a grid that is coupled to this second preliminary output node, a drain electrode that is coupled to the one source pole of this source voltage and is coupled to this output node;

One the 2nd N element in channel has a grid that is coupled to this second preliminary output node, a drain electrode and an one source pole that is coupled to this output node; And

One the 3rd N element in channel, a drain electrode of this source electrode that have the grid that is coupled to this precharged node, is coupled to the 2nd N element in channel and the one source pole that is coupled to earth point.

16. a temporary logical function and produce the method for noninverting output comprises:

When a frequency signal is low level, be high level with a first node preliminary filling;

When this frequency signal became high level, computing one logical function was to control the state of this first node;

When this frequency signal becomes high level, control the state of a Section Point with the state of this first node;

The state of one the 3rd node is defined as the rp state of this Section Point;

When this first node and the 3rd node are high level, can make a low level state keep the path activation, keeping the low level state of this Section Point, otherwise can make this low level state keep not activation of path;

When this frequency signal and the 3rd node are low level, can make a high level state keep the path activation, keeping the high level state of this Section Point, otherwise can make this high level state keep not activation of path; And

Based on the state of this first node and the 3rd node, decide the state of an output node.

17. method as claimed in claim 16, wherein this computing one logical function comprises when this logical function carries out computing with the state of controlling this first node, can move this first node to low level, and when this logical function can't computing, can make this first node remain on high level.

18. method as claimed in claim 17, wherein this state of controlling this Section Point with the state of this first node comprises when this frequency signal becomes high level, if this first node is moved low level to, then can move this Section Point to high level, and, then can move this Section Point to low level if this first node remains on high level.

19. method as claimed in claim 16, wherein this can make a low level state keep the path activation, comprise respectively with this first node and the 3rd node otherwise can make this low level state keep not activation of path, control the first serial connection drop down element and the second serial connection drop down element.

20. method as claimed in claim 16, wherein this can make a high level state keep the path activation, comprise respectively with this frequency signal and the 3rd node otherwise can make this high level state keep not activation of path, control to draw on first serial connection on the element and second serial connection and draw element.

21. method as claimed in claim 16, wherein this determines the state of an output node to comprise with a NAND function, and the state of this first node and the 3rd node is carried out in logic combination.

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