CN1894781B - Method for fabricating a nitrided silicon-oxide gate dielectric - Google Patents

Abstract

A method of fabricating a gate dielectric layer, including: providing a substrate (100); forming a silicon dioxide layer (110) on a top surface of the substrate (105); performing a plasma nitridation in a reducing atmosphere to convert the silicon dioxide layer into a silicon oxynitride layer (110A). The dielectric layer so formed may be used in the fabrication of MOSFETs (145).

Description

Method for manufacturing silicon nitride oxide gate dielectric

technical field

The present invention relates to the fabrication of semiconductor devices; more particularly, it relates to methods of fabricating nitrided silicon oxide gate dielectrics.

Background technique

Integrated circuits are trending towards higher performance, higher speed and lower cost. Accordingly, device dimensions and component sizes are reduced, and the gate dielectric must be scaled accordingly. As the physical thickness of the gate dielectric decreases, the need for higher dielectric constant and lower leakage gate dielectrics arises. In advanced metal oxide semiconductor field effect transistors (MOSFETs), a silicon oxynitride (SiO _x N _y ) layer is used as the gate dielectric. A MOSFET transistor consists of a channel region formed in a silicon substrate, an N- or P-doped polysilicon gate formed atop a thin gate dielectric layer and aligned over the channel region, and on either side of the channel region source/drain regions formed on the silicon substrate.

However, one problem with _SiOxNy gate dielectrics is through wafer thickness and nitrogen concentration _changes . Variations in gate dielectric across-wafer thickness and nitrogen concentration directly result in changes in across-wafer threshold voltage and, in particular, in P-channel field-effect transistors (PFETs), cause changes in the performance of individual integrated circuit chips from the same wafer . Therefore, there is a need for a method of fabricating _SiOxNy layers with relatively uniform across-wafer thickness and _nitrogen concentration.

Contents of the invention

A first aspect of the present invention is a method of manufacturing a gate dielectric layer, comprising the steps of: providing a substrate; forming a silicon dioxide layer on the upper surface of the substrate; performing plasma nitridation in a reducing atmosphere to The silicon dioxide layer is converted to a silicon oxynitride layer.

A second aspect of the present invention is a method of manufacturing a MOSFET comprising the steps of: providing a semiconductor substrate having at least an uppermost silicon layer; forming a silicon dioxide layer on the upper surface of said semiconductor substrate; performing in a reducing atmosphere plasma nitridation to convert the silicon dioxide layer into a silicon oxynitride layer; forming a polysilicon gate on the silicon oxynitride layer, the polysilicon gate in a channel region in the semiconductor substrate aligning above; and forming source/drain regions in the semiconductor substrate, the source/drain regions being aligned with the polysilicon gate.

Description of drawings

The features of the invention are set forth in the appended claims. However, the invention itself will be better understood by reference to the following detailed description of illustrative embodiments read in conjunction with the accompanying drawings, in which:

1 to 3 are partial cross-sectional views showing the fabrication of a nitrided gate dielectric layer according to the present invention;

4 and 5 are partial cross-sectional views illustrating the fabrication of MOSFETs in accordance with the present invention;

Figure 6 is a flow chart of the process steps for fabricating the dielectric layer and MOSFET shown in Figures 1 to 4 in accordance with the present invention;

7 is a schematic diagram of a remote plasma system nitridation system for performing a nitridation step according to a first embodiment of the present invention;

Fig. 8 is a chart showing the improvement of wafer thickness control of silicon nitride oxide gate dielectric according to the present invention;

Figure 9 is a graph of the thickness of nitrided silicon dioxide with and without reducing gas according to the present invention; and

10 is a schematic diagram of a remote plasma system nitridation system for performing a nitridation step according to a second embodiment of the present invention.

Detailed ways

The term silicon dioxide nitride refers to the introduction of nitrogen into the _SiO2 layer to form silicon _oxynitride ( _SiOxNy ). The range of SiO _x N _y includes all combinations of integers x and y (or fractions thereof) in which SiO _x N _y is stable. A reducing atmosphere is defined as a gaseous atmosphere that includes nuclides that react with oxygen.

1 to 3 are partial cross-sectional views illustrating the fabrication of a nitride gate dielectric layer according to the present invention. In FIG. 1 , a substrate 100 having an upper surface 105 is provided. The substrate 100 can be an intrinsic, N-type or P-type bulk silicon substrate, an undoped or intrinsic, N-type or P-type silicon-on-insulator (SOI) substrate or a sapphire substrate or a ruby substrate .

厚。对任意衬底，基体SiO₂层110可以是自然氧化物，允许通过将清洁硅表面暴露在空气或氧气中形成，或基体SiO₂层110可以通过“裸”硅表面的氧化清洁工艺形成。In FIG. 2 , a base SiO ₂ layer 110 having a thickness D1 is formed on the upper surface 105 of the substrate 100 . Prior to forming the base _SiO2 layer 110 on the surface 105, the surface is cleaned by any of a number of cleaning processes known in the art. For example, surface 105 may be cleaned using a dilute hydrofluoric acid (BHF) clean followed by an NH ₄ OH clean followed by an HCl clean. If the substrate 100 is a bulk silicon substrate or an SOI substrate, the matrix SiO can be formed in a first example by thermal oxidation at a temperature of about 600 to 800° C. for about 0.5 to 30 minutes in a furnace containing an oxygen atmosphere. ₂ floors 110. In a second example, the base SiO ₂ layer 110 may be formed by rapid thermal oxidation (RTO) at a temperature of about 800 to 1000° C. for about 5 to 60 seconds in an oxygen-containing atmosphere. If the substrate 100 is a ruby or sapphire substrate, the base SiO ₂ layer 110 may be formed by deposition in a chemical vapor deposition (CVD) device and the dielectric layer may be tetraethoxysilane (TEOS) oxide. TEOS can also be used on bulk silicon or SOI substrates. TEOS can also be used on bulk silicon or SOI substrates. In one instance, D1 is approximately 8 to

thick. For any substrate, the base _SiO2 layer 110 can be a native oxide, allowed to form by exposing the cleaned silicon surface to air or oxygen, or the base _SiO2 layer 110 can be formed by an oxidative cleaning process of the "bare" silicon surface.

厚。在一个实例中，SiO_xN_y层110A约2到20％的氮原子。在第二实例中，在SiO_xN_y层110A中的氮的浓度在1E21和1E22atm/cm³之间。本发明的一个优点是氮化后氧化物的介质厚度与氮化前氧化物的厚度相比增加很小。尽管厚度增加的数量是氮化前氧化物的厚度(D1)的函数，氮化后氧化物的厚度(D2)通常仅增加约0到5％。In FIG. 3 , a remote plasma nitriding (RPN) process is performed to transform the base SiO ₂ layer 110 (see FIG. 2 ) into a nitrided SiO ₂ (SiO _x N _y ) layer 110A. The remote plasma nitridation process is described below with reference to FIGS. 6 , 7 and 9 . SiO _x N _y layer 110A has a thickness D2. In one instance, D2 is approximately 8 to

thick. In one example, _{the SiOxNy} layer 110A is about 2 to 20% nitrogen atoms. In a second example, the concentration of nitrogen in _{the SiOxNy} layer 110A is between 1E21 and 1E22 atm/cm ³ . An advantage of the present invention is that the dielectric thickness of the oxide after nitridation increases very little compared to the thickness of the oxide before nitridation. Although the amount of thickness increase is a function of the thickness of the oxide before nitriding (D1), the thickness of the oxide after nitriding (D2) typically only increases by about 0 to 5%.

4 and 5 are partial cross-sectional views showing the fabrication of MOSFETs according to the present invention. FIG. 4 is a continuation of FIG. 3 . In FIG. 4, a polysilicon layer 115 is formed on the upper surface of _{the SiOxNy} layer 110A. Polysilicon layer 115 may be formed using one of a number of deposition processes known in the art, such as low pressure chemical vapor deposition (LPCVD) or rapid thermal chemical vapor deposition (RTCVD). The polysilicon layer 115 can be undoped or doped N-type or P-type. In one example, the polysilicon layer 115 is 1000 to thick.

In FIG. 5 , polysilicon layer 115 (see FIG. 4 ) is etched; for example, by a reactive ion etching (RIE) process to form gate 125 . Spacers 130 are formed on sidewalls 135 of gate 125 . The formation of the source/drain 140 (typically by one or more steps of ion implantation process) basically completes the formation of the MOSFET 145, and the SiO _x N _y layer 110A acts as the gate dielectric of the MOSFET. If the polysilicon layer 115 (see FIG. 4) Undoped during deposition, after formation of spacers, gate 125 can be doped N-type or P-type by ion implantation together with the formation of source/drain 140 or through a separate step.

FIG. 6 is a flow chart of the process steps shown in FIGS. 1 to 5 for forming the dielectric layer and MOSFET in accordance with the present invention. A silicon substrate will be taken as an example. In step 150, the surface of the silicon substrate is cleaned by any one of a number of cleaning processes known in the art. In a first example, the silicon surface 105 may be cleaned using a dilute hydrofluoric acid (BHF) clean followed by an NH ₄ OH clean followed by an HCl clean. Alternatively, in a second example, a BHF followed by an _O3 clean followed by a dry HCl clean can be used to clean the silicon surface.

厚。In step 155, for example, by thermal oxidation at a temperature of about 600 to 800° C. in an oxygen-containing atmosphere for about 0.5 to 30 minutes, by RTO of about 5 at a temperature of about 800 to 1000° C. in an oxygen-containing atmosphere to 60 s, or by exposing the cleaned silicon surface to air or oxygen, to form a base _SiO2 layer. The base SiO ₂ layer is about 8 to

thick.

In step 160, a remote plasma nitridation process is performed. In a first example, a mixture of nitrogen and an inert gas such as helium is introduced into a plasma generating port of a remote plasma nitriding apparatus and a reducing gas such as hydrogen or ammonia is introduced through a second, non-plasma generating port, Simultaneously, the wafer to be processed is rotated in the processing chamber (see FIG. 7). Typical process conditions are that the flow rate of nitrogen is about 1 to 20 slm (standard liter/minute), the flow rate of helium (or other inert gas) is about 1 to 20 slm, and the flow rate of hydrogen (ammonia or other reducing gas) is about 1 to 20 slm. The air pressure is about 0.2 to 50 Torr, the microwave power is 1000 to 3000 watts, the wafer temperature is about 25 to 1000° C., and the duration is about 20 to 500 seconds.

In the second example, a mixed gas of nitrogen, an inert gas such as helium, and a reducing gas such as hydrogen or ammonia is introduced into a plasma generation port of a remote plasma nitridation apparatus while rotating a wafer to be processed in a processing chamber ( See Figure 10). Typical process conditions are that the flow rate of nitrogen is about 1 to 20 slm, the flow rate of helium (or other inert gas) is about 1 to 20 slm, the flow rate of hydrogen is about 1 to 20 slm, the reaction chamber pressure is about 0.2 to 50 Torr, and the microwave power is 1000 to 3000 watts, The wafer temperature is about 25 to 1000° C. for about 20 to 500 seconds.

In both _examples , the dose of nitrogen was about 1E14 to 5E15 atm/cm ² and the final _SiOxNy layer contained about 2 to 20% nitrogen.

In step 165, an optional annealing step is performed. Annealing is usually not required since remote plasma nitridation is performed on a hot wafer. Standard rapid thermal annealing (RTA) or peak RTA can be performed. Peak annealing was used to increase mobility without driving nitrogen into the _SiO2 /Si interface. A peak anneal is defined as an anneal in which the wafer is at the highest wafer temperature for about 60 seconds or less, while a standard RTA is defined as an anneal in which the wafer is at the highest wafer temperature for greater than about 60 seconds.

Later steps use a nitrided _SiO2 dielectric as the gate dielectric for the MOSFET.

厚。In step 170, a polysilicon layer is formed on the _SiO2 nitride using one of a variety of deposition processes known in the art, such as LPCVD or RTCVD. The polysilicon layer can be undoped or doped N-type or P-type. In one example, the polysilicon layer is 1000 to

thick.

In step 175, the MOSFET is substantially complete. Etching the polysilicon layer; for example, forming the gate by a RIE process, forming spacers on the sidewalls of the gate and forming source/drains in the substrate on either side of the gate (typically in one or more steps ion implantation process). The SiO _x N _y layer is the gate dielectric of the MOSFET. If the polysilicon layer is not doped during deposition, after the spacers are formed, the gate can be doped N-type or P-type by ion implantation together with the formation of the source/drain 140 or in a separate step.

Figure 7 is a schematic diagram of a remote plasma system nitriding system for performing a nitriding step according to a first embodiment of the present invention. In Figure 7, a remote plasma device 180 includes a reaction chamber 185 and possible Rotating wafer chuck 190 (for holding wafer 195). Microwave coil 200 for providing energy to start and maintain plasma 205 surrounds first inlet 210A in inner wall 215 of reaction chamber 185. Provides for generating The gas of the plasma 205 (in this example, a helium/nitrogen mixed gas). A reducing gas (in this example, hydrogen) is provided through the second inlet 210B. Other reducing gases include ammonia, a mixture of hydrogen and nitrogen, ammonia and Mixed gases of nitrogen, mixed gases of hydrogen, ammonia and nitrogen, deuterium, deuterated ammonia, mixed gases of deuterium and nitrogen, mixed gases of deuterated ammonia and nitrogen, mixed gases of deuterium, deuterated ammonia and nitrogen, and deuterium , a mixed gas of ammonia and nitrogen. Also in the inner wall 215 of the reaction chamber 185 and connected to the vacuum pump (not shown), the exhaust port 220 removes spent nuclides and maintains the process gas pressure. The exhaust port 220 and the first inlet 210A Located on the diametrically opposite side of chamber 185, and the second inlet 210B is located between the first inlet and the exhaust port.

In use, a wafer 195 having a matrix _SiO2 layer (not shown) on the upper surface of the wafer 230 is placed into the reaction chamber 185 from a conversion reaction chamber (not shown) and rotated, a predetermined nitridation process is carried out through the first inlet 210A. a gas mixture (in this example, He/N ₂ ) is introduced into the reaction chamber at a predetermined flow rate, a predetermined reducing gas mixture (in this example, H ₂ /NH ₃ ) is introduced into the reaction chamber at a predetermined flow rate through the second inlet B, and The reaction chamber is maintained at a predetermined pressure by a vacuum pump connected to the exhaust port 220 . A predetermined wattage of microwave power is applied to microwave coil 200 to energize and maintain plasma 205 . After a predetermined time, the microwave power is turned off to extinguish the plasma 205, the gas flow is shut off and the pressure of the reaction chamber 185 reaches the pressure of the conversion reaction chamber. The plasma 205 is mainly nitrogen ion, helium ion, hydrogen neutral plasma.

An example of a suitable apparatus for practicing the invention is an AMAT model XE12 reaction chamber manufactured by Applied Materials Corp, Santa Clara, CA, with a decoupled plasma cell also supplied by Applied Materials Corp.

FIG. 8 is a graph showing the improvement in control over wafer thickness for a silicon nitride oxide gate dielectric in accordance with the present invention. Figure 8 shows the thickness of the silicon oxide film after RPN as a function of the distance from the center of the wafer for two silicon dioxide nitride films of the same average thickness. Measurements are performed using an ellipsometer. Curve 225 is the _SiOxNy layer treated as above, but without _any reducing gas flow. The average thickness of the SiO _x N _y layer of curve 225 is Has a delta of 0.97. Curve 230 is _{the SiOxNy} layer treated as above, but with reducing gas flow. The average thickness of the SiO _x N _y layer of curve 230 is Has a delta of 0.50. Thus, the introduction of reducing nuclides results in approximately a two-fold increase in thickness non-uniformity.

The second ion mass spectrometry (SIMS) profiles of layers 225 and 230 show that the increase in nitrogen concentration uniformity compounded well with the increase in _SiOxNy thickness uniformity _, as shown in Table I. Note that there is a one-to-one correspondence between nitrogen dose and concentration.

Table I

In Table I, the nitrogen concentration varies by more than 50% from the center to the edge in wafers treated by remote plasma nitridation in a chamber in which no reducing gas is present. In both instances of wafers treated by remote plasma nitridation in a reaction chamber with a reducing gas present, the nitrogen concentration in the wafer did not vary by more than 25% from the center to the edge.

Consequently, both the _SiOxNy thickness uniformity and the nitrogen concentration uniformity are improved by a factor _of about two.

曲线245是如上述处理的SiO_xN_y层，但是具有还原气体流。曲线245的平均厚度约13到

因此，引入还原核素明显减小了介质层厚度在RPN处理期间的增加。厚度的增加限定在约35％。在一些实例中厚度的增加接近于零。Figure 9 is a graph of the thickness of nitrided silicon dioxide with and without the use of a reducing gas according to the present invention. As mentioned above, another problem with performing the RPN process without using a reducing gas is that, as shown in the substrate SiO There is an unacceptable increase in dielectric thickness between layer ₂ and the finished SiO _x N _y layer. As shown in Figure 9, the introduction of reducing gas into the RPN reaction chamber greatly reduced this thickness increase. 9 plots the thickness of native oxidation (curve 235), post-RPN native oxide film without reducing gas treatment (curve 240), and post-RPN native oxide film with reducing gas treatment (curve 245) as a function of distance from the wafer center. Measurements are performed using an ellipsometer. Curve 240 is the SiO _x N _y layer, composed of about A thick native oxide layer was produced by the above treatment, but without any reducing gas flow. The average thickness of the SiO _x N _y layer of curve 240 is about 25 to

Curve 245 is _{the SiOxNy} layer treated as above, but with reducing gas flow. The average thickness of the curve 245 is about 13 to

Therefore, the introduction of reducing nuclides significantly reduces the increase in dielectric layer thickness during RPN treatment. The increase in thickness is limited to about 35%. In some instances the increase in thickness is close to zero.

10 is a schematic diagram of a remote plasma system nitridation system for performing a nitridation step according to a second embodiment of the present invention. Figure 10 is similar to Figure 7 except that no gas is provided from the second inlet 210B and all gases (nitrogen, helium and hydrogen) are provided through the first inlet 210A. The plasma 205 is mainly nitrogen ion, helium ion, hydrogen ion plasma.

Thus _, the present invention fulfills the need for a method of fabricating a _SiOxNy layer with a relatively uniform thickness across the wafer.

The descriptions of the embodiments of the present invention are given above for the understanding of the present invention. It should be understood that the present invention is not limited to the particular embodiments described herein, but that various modifications, rearrangements, and substitutions will now be apparent to those skilled in the art without departing from the scope of the invention. It is therefore intended that the appended claims cover all such modifications and changes as fall within the true spirit and scope of the invention.

Claims (28)

1. method of making gate dielectric layer may further comprise the steps:

On the upper surface of substrate, form silicon dioxide layer;

Described substrate is placed on first Room with first inlet and second inlet;

Introduce reducing gas by described second inlet to described first Room;

Produce plasma in second Room, described plasma is nitrogen ion, helium ion and hydrogen neutral ion, contiguous described first Room, described second Room, and described second Room is connected to described first Room by described first inlet in described first Room;

By described first inlet described plasma is transferred to described first Room from described second Room;

In the reduction atmosphere, use described plasma in described first Room, to carry out pecvd nitride to change described silicon dioxide layer into silicon oxynitride layer.

2. use remote plasma nitridation technology to carry out described pecvd nitride step according to the process of claim 1 wherein.

3. according to the method for claim 2, wherein said reducing gas is a hydrogen.

4. according to the method for claim 2, wherein said reducing gas is a hydrogen, ammonia, the mist of hydrogen and nitrogen, the mist of ammonia and nitrogen, and the mist of hydrogen, ammonia and nitrogen, deuterium, ammonia, deuterated, the mist of deuterium and nitrogen, the mist of ammonia, deuterated and nitrogen, the mist of deuterium, ammonia, deuterated and nitrogen, or the mist of deuterium, ammonia and nitrogen.

5. according to the method for claim 1, wherein said substrate comprises body silicon or silicon-on-insulator substrate, and forms described silicon dioxide layer by being selected from following technology: autoxidation growth in air or oxygen, thermal oxidation, chemical vapour deposition (CVD) and oxidation cleaning procedure.

6. according to the process of claim 1 wherein that described silicon dioxide layer has 8 to 23 Thickness.

7. according to the process of claim 1 wherein that described silicon oxynitride has 8 to 24

Thickness.

8. according to the process of claim 1 wherein that described oxygen silicon nitride membrane comprises the nitrogen of 2 to 20 percentages.

9. according to the process of claim 1 wherein that the concentration of the nitrogen in described silicon oxynitride layer is at 1E21 and 1E22atm/cm ³Between.

10. according to the process of claim 1 wherein that the step of described execution pecvd nitride arrives 5E14atm/cm with 1E14 ²The nitrogen of dosage is given described silicon dioxide layer.

11. according to the process of claim 1 wherein that the thickness of described silicon oxynitride layer is than the thickness of described silicon dioxide layer thick 0 to 35%.

12. be not more than 0.5 dust δ according to the process of claim 1 wherein that the thickness of described silicon oxynitride layer changes to the edge from the center of described substrate.

13. be not more than 25% according to the process of claim 1 wherein that the nitrogen concentration of described silicon oxynitride layer changes to the edge from the center of described substrate.

14. according to the method for claim 5, wherein said thermal oxidation is a rapid thermal oxidation.

15. a method of making MOSFET may further comprise the steps:

Semiconductor substrate with at least upper silicon layer is provided;

On the upper surface of described Semiconductor substrate, form silicon dioxide layer;

Described substrate is placed on first Room with first inlet and second inlet;

Introduce neutral reduction gas by described second inlet to described first Room;

Produce plasma in second Room, described plasma is nitrogen ion, helium ion and hydrogen neutral ion, contiguous described first Room, described second Room, and described second Room is connected to described first Room by described first inlet in described first Room;

By described first inlet described plasma is transferred to described first Room from described second Room;

In reducing atmosphere, use described plasma in described first Room, to carry out pecvd nitride to change described silicon dioxide layer into silicon oxynitride layer;

On described silicon oxynitride layer, form polysilicon gate, aim on the channel region of described polysilicon gate in described Semiconductor substrate; And

Form regions and source in described Semiconductor substrate, described regions and source is aimed at described polysilicon gate.

16., wherein use remote plasma nitridation technology to carry out described pecvd nitride step according to the method for claim 15.

17. according to the method for claim 16, wherein said reducing gas is a hydrogen.

18. method according to claim 16, wherein said reducing gas is a hydrogen, ammonia, the mist of hydrogen and nitrogen, the mist of ammonia and nitrogen, and the mist of hydrogen, ammonia and nitrogen, deuterium, ammonia, deuterated, the mist of deuterium and nitrogen, the mist of ammonia, deuterated and nitrogen, the mist of deuterium, ammonia, deuterated and nitrogen, or the mist of deuterium, ammonia and nitrogen.

19. method according to claim 15, wherein said substrate comprises body silicon or silicon-on-insulator substrate, and forms described silicon dioxide layer by being selected from following technology: autoxidation growth in air or oxygen, thermal oxidation, chemical vapour deposition (CVD) and oxidation cleaning procedure.

20. according to the method for claim 15, wherein said silicon dioxide layer has 8 to 23 Thickness.

21. according to the method for claim 15, wherein said silicon oxynitride has 8 to 24

Thickness.

22. according to the method for claim 15, wherein said oxygen silicon nitride membrane comprises the nitrogen of 2 to 20 percentages.

23. according to the method for claim 15, wherein the concentration of the nitrogen in described silicon oxynitride layer is at 1E21 and 1E22atm/cm ³Between.

24. according to the method for claim 15, the step of wherein said execution pecvd nitride arrives 5E14atm/cm with 1E14 ²The nitrogen of dosage is given described silicon dioxide layer.

25. according to the method for claim 15, the thickness of wherein said silicon oxynitride layer is than the thickness of described silicon dioxide layer thick 0 to 35%.

26. according to the method for claim 15, the thickness of wherein said silicon oxynitride layer changes to the edge from the center of described substrate and is not more than 0.5 dust δ.

27. according to the method for claim 15, the nitrogen concentration of wherein said silicon oxynitride layer changes to the edge from the center of described substrate and is not more than 25%.

28. according to the method for claim 19, wherein said thermal oxidation is a rapid thermal oxidation.

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