CN204681073U - Data and charging coffret protective circuit - Google Patents

Abstract

The data and charging transmission interface protection circuit is connected between the power supply end and the bus end of the data interface of the mobile device, and consists of a comparator, a first NMOS transistor, a second NMOS transistor, a first diode, a second diode, and a second diode. A DC power supply, a second DC power supply, a current limiting resistor, a first pull-up resistor and a second pull-up resistor; the output terminals of the comparator are connected to the gates of the two NMOS transistors, and the substrates of the two NMOS transistors The power supply terminal and the bus terminal are respectively connected, and connected to their respective drains; the voltage value of the second DC power supply is greater than that of the first DC power supply. The utility model can realize effective protection for the USB power output line of the mobile device, no matter whether the USB power output line VBUS is short-circuited to the power supply or to the ground, it does not affect the normal operation of the internal circuit of the mobile device, and realizes reliable short-circuit protection.

Description

Data and charging transmission interface protection circuit

technical field

The utility model relates to the field of electronic circuits, in particular to a data and charging transmission interface protection circuit. the

Background technique

In order to ensure the safety of use, mobile devices, such as vehicle-mounted devices used in field data collection, have high safety performance requirements, and the design must ensure that the failure rate is as low as possible. As the most widely used communication interface between mobile peripherals and hosts, USB (Universal Serial Bus) has the characteristics of low cost, simple use, support for plug and play, and easy expansion. application. Because the USB interface provides a built-in power supply, it can provide a current of more than 500mA. For some devices with high power, such as mobile hard disks, the instantaneous drive current can reach more than 1A. For an interface such as the USB bus that can directly output power, the interface circuit may be short-circuited to the power supply or to the ground, which will damage the body at this time.

Utility model content

In order to overcome the technical defect that a large current will damage internal devices and equipment when the interface of a mobile device capable of external power supply and charging is short-circuited to a power supply or ground, the utility model discloses a protection circuit for a data and charging transmission interface.

The data and charging transmission interface protection circuit is connected between the power supply terminal and the bus terminal of the data interface of the mobile device, and is characterized in that it consists of a comparator, a first NMOS tube, a second NMOS tube, a first diode, a second two Composed of pole tube, first DC power supply, second DC power supply, current limiting resistor, first pull-up resistor and second pull-up resistor;

The output terminals of the comparator are connected to the gates of two NMOS transistors, the substrates of the two NMOS transistors are respectively connected to the power supply terminal and the bus terminal, and are connected to their respective drains, and the sources of the two NMOS transistors are interconnected and connected to The positive pole of the first diode, the current limiting resistor is connected between the negative pole of the first diode and the inverting input terminal of the comparator, the positive phase input terminal of the comparator is connected to the first DC power supply through the second pull-up resistor, and The anode of the second diode is connected, the cathode of the second diode is connected to the bus terminal, and the comparison output terminal is connected to the second DC power supply through the first pull-up resistor; the voltage value of the second DC power supply is greater than that of the first DC power supply;

A third NMOS transistor is connected between the bus terminal and the ground wire, the gate, source and substrate of the third NMOS transistor are all connected to the ground, the drain is connected to the bus terminal, and the power supply terminal and the second NMOS transistor are connected to each other. A PMOS transistor is connected between the sources of the transistors, the gate, source and substrate of the PMOS transistors are all connected to the power supply terminal, and the drain is connected to the source of the second NMOS transistor.

Preferably, a light emitting diode is connected between the output terminal of the comparator and the ground.

Preferably, a first capacitor and a pole resistor are respectively connected between the two ends of the current limiting resistor and the ground.

Preferably, a second capacitor is connected between the non-inverting input terminal of the comparator and the ground.

The data and charging transmission interface protection circuit described in the utility model can effectively protect the USB power output line of the mobile device, and no matter whether the USB power output line VBUS is short-circuited to the power supply or to the ground, it will not affect the normal operation of the internal circuit of the mobile device , to achieve a reliable short-circuit protection. Manufacturing costs are significantly reduced by using very low-cost common discrete devices.

Description of drawings

Fig. 1 is a kind of specific embodiment schematic diagram of the utility model;

The marks in the drawings and the names of corresponding parts: VIN-power supply terminal, VBUS-first voltage divider resistor, VCC1-first DC power supply, VCC2-second DC power supply, COMP-comparator, R1-current limiting resistor, R2-pole resistor, R3-first pull-up resistor, R4-second pull-up resistor, D1-first diode, D2-second diode, D3-light-emitting diode, C1-first capacitor, C2- The second capacitor, M1-the first NMOS transistor, M2-the second NMOS transistor, M3-the third NMOS transistor, M4-the PMOS transistor.

Detailed ways

The utility model will be further described in detail below in conjunction with the embodiments and accompanying drawings, but the implementation of the utility model is not limited thereto.

The data and charging transmission interface protection circuit described in the utility model is connected between the power supply terminal and the bus terminal of the data interface of the mobile device, and is characterized in that it consists of a comparator, a first NMOS tube, a second NMOS tube, and a first diode tube, a second diode, a first DC power supply, a second DC power supply, a first voltage dividing resistor, a second voltage dividing resistor, a first pull-up resistor and a second pull-up resistor;

The output terminals of the comparator are connected to the gates of two NMOS transistors, the substrates of the two NMOS transistors are respectively connected to the power supply terminal and the bus terminal, and are connected to their respective drains, and the sources of the two NMOS transistors are interconnected and connected to The positive pole of the first diode, the current limiting resistor is connected between the negative pole of the first diode and the inverting input terminal of the comparator, the positive phase input terminal of the comparator is connected to the first DC power supply through the second pull-up resistor, and Connect the anode of the second diode, connect the cathode of the second diode to the bus terminal, and connect the comparison output terminal to the second DC power supply through the first pull-up resistor;

The voltage value of the second DC power supply is greater than that of the first DC power supply.

For example, the first DC power source is 3.3V, and the second DC power source is 12V. At this time, for the power supply terminal, the input voltage should be between 3.3 and 12V, for example, 5V.

For two NMOS transistors, the drain is the P region, the substrate is the N region, and the substrate is connected to the drain to form a diode pointing from the drain to the substrate. For the source A point where the two NMOS transistors are connected together, when in When the VBUS terminal is connected to an external device, no matter whether the voltage of the VBUS terminal is higher or lower than 5V, the voltage at point A is the higher one between the VBUS terminal and the VIN terminal.

When the VBUS terminal voltage is outside the range between the first DC power supply and the second DC power supply voltage, that is, greater than 12V or less than 3.3V, for example, when it is less than 3.3V, the voltage at point A is 5V, through the first diode D1 And the current limiting resistor is input at the inverting input terminal of the comparator, and because the VBUS voltage is lower than 3.3V, the second diode is turned on, and the voltage at the non-inverting input terminal of the comparator is a value lower than 3.3V, and the comparison The output of the device is low, and the two MOS transistors are turned off to avoid the voltage of the VBUS terminal being too low, that is, when the usual short circuit is grounded, it will cause a short circuit between VIN and ground. And when the VBUS voltage is higher than 5V, the voltage at point A is the VBUS voltage, but the second diode is not conducting, so that the voltage of the comparator’s positive phase input terminal is still 3.3V of the first DC power supply, and the comparator’s positive phase input The input voltage of the terminal is higher than 5V, the output voltage is still negative, and the two MOS tubes are kept off, and there is no charging at this time, so as to avoid the current flowing back into the 5V voltage and damage the battery.

And when the VBUS voltage is higher than the second DC power supply 12V, since the gate voltage of the second NMOS transistor is limited to 12V by VCC2 at this time, VGS has become a negative value, and M2 will not be turned on to avoid high voltage damage to internal devices.

A third NMOS transistor is also connected between the bus terminal and the ground wire, the gate, source and substrate of the third NMOS transistor are all connected to the ground, the drain is connected to the bus terminal, and the power supply terminal and the second NMOS transistor are connected to the ground. A PMOS transistor is connected between the sources of the NMOS transistors, the gate, source and substrate of the PMOS transistors are all connected to the power supply terminal, and the drain is connected to the source of the second NMOS transistor

The function of the third NMOS transistor M3 and the PMOS transistor is to provide an electrostatic protection circuit for the bus terminal. Since the bus terminal is exposed to the outside, and due to the frequent plugging and unplugging of external devices, such as U disks, the possibility of encountering electrostatic damage is relatively high. The electrostatic protection circuit Provide electrostatic protection for the bus terminal VBUS. Under normal conditions, since the gate and source of the two MOS transistors are connected together, VGS=0, the two MOSs are not conducting, which does not affect the normal operation of the circuit.

When encountering an electrostatic pulse, take this pin encountering a positive voltage electrostatic pulse and discharge it to the ground as an example. The electrostatic voltage is coupled to the gate of M3 through the gate-drain parasitic capacitance of the third NMOS transistor M3, so that M3 is turned on. In this way, the electrostatic voltage is discharged to the ground wire. If a negative voltage static pulse is encountered, the potential of the ground wire is higher than that of the VBUS terminal, so that the parasitic diode from the substrate to the drain of M3 is turned on, so that the negative high-voltage static electricity is discharged, and the high-voltage static electricity is avoided. Act directly on internal devices, such as the input terminal of comparators, etc., and destroy internal circuits.

For PMOS transistor M4, the discharge principle is similar. The difference is that since the second NMOS transistor M2 is connected between the bus terminal and point A, there is a parasitic diode pointing from the bus terminal to point A for forward conduction, and the bus terminal VBUS encounters When the positive high-voltage electrostatic pulse of the power supply terminal VIN is applied, the static electricity first passes through the parasitic diode to point A, and then from point A passes through the drain of the PMOS transistor M4-substrate parasitic diode to reach the power supply terminal. On the contrary, when the bus terminal VBUS encounters a relative When the negative high-voltage electrostatic pulse of the power supply terminal VIN is applied, it is coupled to the gate through the gate-drain parasitic capacitance of the second NMOS transistor M2 and PMOS transistor M4, so that the corresponding MOS transistor is turned on, thereby establishing an electrostatic discharge from the VBUS terminal to the VIN terminal. Let the path go.

A light-emitting diode D3 can be set at the output end of the comparator, and the positive and negative poles are respectively connected to the output end of the comparator and the ground. When the comparator outputs a positive voltage and the two NMOS transistors are turned on, D3 lights up, indicating that the data interface is normal at this time, such as D3 If it is off, the comparator outputs a low level, indicating that the amplitude of the connected power supply is out of range.

Point A of the utility model is fed back to the inverting input terminal of the comparator, which actually constitutes a feedback loop. In order to improve the stability of the loop, a measure of connecting a capacitor at the input terminal can be taken, for example, between the two ends of the current limiting resistor and the ground. A first capacitor and a pole resistor are respectively connected between them, or a second capacitor is connected between the non-inverting input terminal of the comparator and the ground to provide a main pole, wherein the first method is more complicated, usually the pole resistor R2 The resistance value is much larger than R1, so as to weaken the influence of the voltage change at the input end of the comparator caused by the voltage division of R1 and R2 as much as possible. R2 and C1 together provide a main pole. By adjusting R2, the main pole can be better adjusted. Compared with the second method, which only connects the C2 capacitor at the input end to fuzzy processing of the input impedance of the comparator, it is more accurate.

As mentioned above, the utility model can be better realized.

Claims (4)

1. The data and charging transmission interface protection circuit is connected between the power supply terminal and the bus terminal of the data interface of the mobile device, and is characterized in that it consists of a comparator, a first NMOS transistor, a second NMOS transistor, a first diode, and a second NMOS transistor. Two diodes, a first DC power supply, a second DC power supply, a current limiting resistor, a first pull-up resistor and a second pull-up resistor; The output terminals of the comparator are connected to the gates of two NMOS transistors, the substrates of the two NMOS transistors are respectively connected to the power supply terminal and the bus terminal, and are connected to their respective drains, and the sources of the two NMOS transistors are interconnected and connected to The positive pole of the first diode, the current limiting resistor is connected between the negative pole of the first diode and the inverting input terminal of the comparator, the positive phase input terminal of the comparator is connected to the first DC power supply through the second pull-up resistor, and The anode of the second diode is connected, the cathode of the second diode is connected to the bus terminal, and the comparison output terminal is connected to the second DC power supply through the first pull-up resistor; the voltage value of the second DC power supply is greater than that of the first DC power supply; A third NMOS transistor is connected between the bus terminal and the ground wire, the gate, source and substrate of the third NMOS transistor are all connected to the ground, the drain is connected to the bus terminal, and the power supply terminal and the second NMOS transistor are connected to each other. A PMOS transistor is connected between the sources of the transistors, the gate, source and substrate of the PMOS transistors are all connected to the power supply terminal, and the drain is connected to the source of the second NMOS transistor. 2. The data and charging transmission interface protection circuit according to claim 1, wherein a light emitting diode is connected between the output terminal of the comparator and the ground. 3. The data and charging transmission interface protection circuit according to claim 1, wherein a first capacitor and a pole resistor are respectively connected between the two ends of the current limiting resistor and the ground. 4 . The data and charging transmission interface protection circuit according to claim 1 , wherein a second capacitor is connected between the non-inverting input end of the comparator and the ground.