CN205015387U - Anti-interference low-voltage detection chip - Google Patents

Abstract

The utility model belongs to the technical field of the integrated circuit technique and specifically relates to an anti-interference low-voltage detection chip. The device comprises a resistance voltage dividing circuit, a logic combination circuit, a capacitance charging and discharging circuit and a Schmidt shaping circuit which are sequentially connected, wherein a recovery voltage setting circuit is connected between the resistance voltage dividing circuit and the Schmidt shaping circuit, and the input end of the logic combination circuit is also connected with a reference voltage generating circuit. The utility model can make the waveform output by the whole chip more stable through the arranged Schmidt shaping circuit; although the capacitor charging and discharging circuit has a certain time delay when the whole chip operates, the anti-interference performance of the chip is enhanced, so that the chip is slightly interfered by the outside, and the voltage detection result is more accurate; the relationship between the recovery voltage and the starting voltage which can be greatly weakened through the arranged recovery voltage setting circuit and the resistance voltage dividing circuit enhances the variability of the input voltage and improves the detection precision; the circuit structure is simple, and the practical value and the market promotion value are very high.

Description

An anti-interference low voltage detection chip

technical field

The utility model relates to the technical field of integrated circuits, in particular to an anti-interference low-voltage detection chip.

Background technique

As we all know, the voltage detection circuit is used to detect the supply voltage. When the voltage changes to a certain set value, the voltage detection circuit outputs a control signal; when we set this standard voltage value, we hope that the circuit can accurately detect and output the corresponding The control signal, the existing voltage detection circuit can easily do this.

Figure 1 shows the electrical schematic diagram of an existing voltage detection circuit. In this circuit, the input voltage at the VIN terminal is divided by the resistors R1, R2 and R3 to obtain a voltage V1, which is connected to the positive pole of the comparator. , the negative pole of the comparator is connected to the VREF terminal pin of the reference voltage circuit, the input of the inverter is connected to the output of the comparator, the output of the inverter is connected to the gate of the MOS transistor M2 in the output circuit, the source of the MOS transistor M2 and The substrate is grounded, and the drain is the output signal. At the same time, the MOS transistor M2 is connected to the gate of the MOS transistor M1. The source and substrate of the MOS transistor M1 are grounded, and the drain is connected between the resistors R2 and R3. When the voltage at the VIN terminal is set so that V1 is lower than VREF (VIN is the turn-on voltage at this time), VOUT is in a high-impedance state; when the voltage at the VIN terminal is set so that V1 is higher than VREF, VOUT is at a low level. However, once When VOUT is low level (that is, the output of the inverter is high level), and the voltage at the VIN terminal is set again so that V1 is lower than VREF, since the turn-on voltage of the MOS transistor M1 is higher than that in the first case, This new voltage value is called the recovery voltage; during this process, the VREF output by the reference voltage circuit will not change with the change of VIN, so that the voltage detection function is realized according to the output change of VOUT.

However, although the voltage detection circuit shown in Figure 1 can generate an output control signal when the supply voltage changes to a set value, and can also set the recovery voltage value, it generally has the following defects in practical applications:

1. The anti-interference is weak. Due to the existence of external interference signals, the detection results are not accurate enough;

2. The ratio of the recovery voltage to the original turn-on voltage is related to the resistance R1, resistance R2 and resistance R3, which is inconvenient and not accurate enough to change;

3. Due to the detection of the instantaneous value of the input voltage, the output signal is extremely unstable.

Therefore, how to improve the existing voltage detection circuit is a technical problem to be solved urgently in related industries.

Utility model content

In view of the deficiencies in the prior art above, the utility model aims at an anti-interference low-voltage detection chip with simple circuit structure, strong anti-interference, high detection accuracy and stable signal output.

In order to achieve the above object, the utility model adopts the following technical solutions:

An anti-interference low-voltage detection chip, which includes:

A capacitor charging and discharging circuit for realizing voltage output through charging and discharging of a capacitor, the capacitor charging and discharging circuit is provided with a power input terminal;

A logic combination circuit for controlling the opening and closing of the capacitor charging and discharging circuit, the output terminal of the logic combination circuit is connected to the input terminal of the capacitor charging and discharging circuit;

A reference voltage generation circuit for providing a reference voltage to the logic combination circuit, the output end of the reference voltage generation circuit is connected to the input end of the logic combination circuit;

A resistor divider circuit for setting the voltage value input to the logic combination circuit, the resistor divider circuit is connected to the input terminal of the logic combination circuit, and the resistor divider circuit is provided with a voltage setting terminal;

A Schmidt shaping circuit for outputting the detection signal after shaping the voltage output by the capacitor charging and discharging circuit, the Schmidt shaping circuit is connected to the output end of the capacitor charging and discharging circuit, and the Schmidt shaping circuit A detection signal output terminal is provided;

and

A recovery voltage setting circuit for setting the ratio of the resistance voltage divider circuit according to the voltage value output by the Schmidt shaping circuit, and the recovery voltage setting circuit is connected to the output terminal of the Schmidt shaping circuit and the resistance voltage divider circuit between.

Preferably, the capacitor charging and discharging circuit includes a third MOS transistor, a fourth MOS transistor, a charging and discharging capacitor, and a fifth resistor, and the gate of the third MOS transistor and the gate of the fourth MOS transistor are simultaneously connected to a logic combination circuit The output terminal of the third MOS transistor and the drain electrode of the fourth MOS transistor are respectively connected to both ends of the fifth resistor, and the source and substrate of the third MOS transistor are connected to the power supply input terminal at the same time, so The source and the substrate of the fourth MOS transistor are grounded at the same time, one end of the charging and discharging capacitor is grounded, and the other end is connected to the input end of the Schmidt shaping circuit.

Preferably, the recovery voltage setting circuit includes a first MOS transistor and a second MOS transistor, the gate of the first MOS transistor and the gate of the second MOS transistor are simultaneously connected to the output terminal of the Schmidt shaping circuit, so The source and the substrate of the first MOS transistor are connected to the voltage setting terminal at the same time, the source and the substrate of the second MOS transistor are connected to the ground at the same time, the drain of the first MOS transistor and the drain of the second MOS transistor Connect the resistor divider circuit respectively.

Preferably, the Schmidt shaping circuit includes a sequentially connected Schmidt shaping unit and a second inverter, the input end of the Schmidt shaping unit is connected to the output end of the capacitor charging and discharging circuit, and the second inverter The output terminal of the inverter is used as the detection signal output terminal, and the gate of the first MOS transistor and the gate of the second MOS transistor are simultaneously connected between the input terminal of the second inverter and the output terminal of the Schmidt shaping unit between.

Preferably, the resistor divider circuit includes a first resistor, a second resistor, a third resistor and a fourth resistor serially connected in series between the voltage setting terminal and the ground terminal;

The input terminal of the logic combination circuit is connected between the second resistor and the third resistor, the drain of the first MOS transistor is connected between the first resistor and the second resistor, and the drain of the second MOS transistor Connected between the third resistor and the fourth resistor.

Preferably, the resistance value of the first resistor is equal to the resistance value of the fourth resistor.

Preferably, the logic combination circuit includes a comparator and a first inverter, the anode of the comparator is connected between the first resistor and the second resistor, the cathode is connected to the output terminal of the reference voltage generating circuit, and the output terminal is connected to the second resistor. An input terminal of an inverter, the output terminal of the first inverter is connected to the input terminal of the capacitor charging and discharging circuit.

Due to the adoption of the above scheme, the utility model can make the waveform output by the whole chip more stable by setting the Schmidt shaping circuit; although there will be a certain delay when the whole chip is running by using the capacitor charging and discharging circuit, it strengthens the chip. Excellent anti-interference, so that it is less disturbed by the outside world, so that the result of voltage detection is more accurate; through the recovery voltage setting circuit, it can greatly weaken the recovery voltage and the relationship between the starting voltage and the resistance divider circuit. relationship, which enhances the variability of the input voltage and improves the detection accuracy; the circuit structure is simple, the anti-interference is strong, the detection accuracy is high, the detection result is accurate, and it is easy to adjust, which has strong practical value and market promotion value.

Description of drawings

Fig. 1 is a schematic diagram of a voltage detection circuit in the prior art;

Fig. 2 is the schematic diagram of the utility model embodiment;

Fig. 3 is a circuit structure diagram of an embodiment of the utility model.

detailed description

The embodiments of the utility model will be described in detail below in conjunction with the accompanying drawings, but the utility model can be implemented in many different ways defined and covered by the claims.

As shown in Figure 2 and Figure 3, an anti-interference low-voltage detection chip provided by the embodiment of the present invention includes:

Capacitor charging and discharging circuit 1 is mainly used to realize voltage output through charging and discharging of capacitor, and a power input terminal VDD is provided on capacitor charging and discharging circuit 1;

The logic combination circuit 2 is mainly used to control the opening and closing state of the capacitor charging and discharging circuit 1, thereby controlling the charging and discharging state of the capacitor of the capacitor charging and discharging circuit 1, and its output terminal is connected to the input terminal of the capacitor charging and discharging circuit 1;

The reference voltage generating circuit 3 is mainly used to provide the reference voltage Vref to the logic combination circuit 2, and its output terminal is connected to the input terminal of the logic combination circuit 2;

The resistor divider circuit 4 is mainly used to set the voltage value input to the logic combination circuit 2, so that the logic combination circuit 2 controls the charging of the capacitor of the capacitor charging and discharging circuit 1 by comparing the reference voltage Vref with the set input voltage. In the discharge state, the resistance voltage divider circuit 4 is connected to the input terminal of the logic combination circuit 2, and a voltage setting terminal Vin is provided on the resistance voltage divider circuit 4;

The Schmidt shaping circuit 5 is mainly used for shaping the output voltage of the capacitor charging and discharging circuit 1 to realize the output of the detection signal. A detection signal output terminal Vout is provided;

and

The recovery voltage setting circuit 6 is mainly used to set the ratio of the resistance voltage divider circuit 4 according to the voltage value output by the Schmidt shaping circuit 5, which is connected to the output terminal of the Schmidt shaping circuit 5 and the resistance voltage divider circuit 4 During operation, the switch state of the recovery voltage setting circuit 6 is controlled by the voltage value of the detection signal output by the Schmidt shaping circuit 5 , so that the startup voltage and the recovery voltage are set by the recovery voltage setting circuit 6 .

In this way, the Schmidt shaping circuit 5 provided can make the waveform output by the whole chip more stable; although the capacitor charging and discharging circuit 1 has a certain delay when the whole chip is running, it enhances the anti-interference performance of the chip, It is less disturbed by the outside world, so that the result of voltage detection is more accurate; the relationship between the recovery voltage and the starting voltage and the resistance voltage divider circuit 4 can be greatly weakened by setting the recovery voltage setting circuit 6, and the the variability of the input voltage.

In order to optimize the circuit structure of the entire chip and ensure the performance of the entire chip, the capacitor charging and discharging circuit 1 of this embodiment includes a third MOS transistor M3, a fourth MOS transistor M4, a charging and discharging capacitor C1, and a fifth resistor R5; wherein, the third The MOS transistor M3 is an enhanced P-channel MOS transistor, the fourth MOS transistor M4 is an enhanced N-channel MOS transistor, and the gate of the third MOS transistor M3 and the gate of the fourth MOS transistor M4 are simultaneously connected to the output of the logic combination circuit 2 terminal, the drain of the third MOS transistor M3 and the drain of the fourth MOS transistor M4 are respectively connected to both ends of the fifth resistor R5, the source and the substrate of the third MOS transistor M3 are connected to the power input terminal VDD at the same time, and the fourth The source and the substrate of the MOS transistor M4 are grounded at the same time, one end of the charging and discharging capacitor C1 is grounded, and the other end is connected to the input end of the Schmidt shaping circuit 5 .

The recovery voltage setting circuit 6 of this embodiment includes a first MOS transistor M1 and a second MOS transistor M2; wherein, the first MOS transistor M1 is an enhanced P-channel MOS transistor, and the second MOS transistor M2 is an enhanced N-channel MOS transistor. The gate of the first MOS transistor M1 and the gate of the second MOS transistor M2 are simultaneously connected to the output terminal of the Schmidt shaping circuit 5, and the source and substrate of the first MOS transistor M1 are simultaneously connected to the voltage setting terminal Vin, The source and the substrate of the second MOS transistor M2 are grounded at the same time, and the drains of the first MOS transistor M1 and the second MOS transistor M1 are respectively connected to the resistor divider circuit 4 .

The Schmidt shaping circuit 5 of the present embodiment includes a sequentially connected Schmidt shaping unit 51 and a second inverter A2, the input end of the Schmidt shaping unit 51 is connected to the output end of the capacitor charging and discharging circuit 1, and the second inverter A2 The output terminal of the inverter A2 is used as the detection signal output terminal Vout, and the gate of the first MOS transistor M1 and the gate of the second MOS transistor M2 are simultaneously connected to the input terminal of the second inverter A2 and the Schmidt shaping unit 51 between the output terminals.

The resistor divider circuit 4 of this embodiment includes a first resistor R1, a second resistor R2, a third resistor R3 and a fourth resistor R4 connected in series between the voltage setting terminal Vin and the ground terminal; wherein, the logic combination circuit 2 The input terminal of the first MOS transistor M1 is connected between the second resistor R2 and the third resistor R3, the drain of the first MOS transistor M1 is connected between the first resistor R1 and the second resistor R2, and the drain of the second MOS transistor M2 is connected to the first between the third resistor R3 and the fourth resistor R4. In order to increase the variability of the input voltage, weaken the relationship between the recovery voltage and the turn-on voltage and each resistor, and improve the accuracy of voltage detection, the resistance values of the first resistor R1 and the fourth resistor R4 in this embodiment are equal.

Further, the logic combination circuit 2 of this embodiment includes a comparator Q and a first inverter A1, the positive pole of the comparator Q is connected between the first resistor R1 and the second resistor R2, and the negative pole is connected to the reference voltage generation circuit 3 The output terminal and the output terminal are connected to the input terminal of the first inverter A1, and the output terminal of the first inverter A1 is connected to the input terminal of the capacitor charging and discharging circuit 1 (that is, the gate of the third MOS transistor M3 and the fourth MOS transistor M3 Gate of tube M4).

In order to clearly show the superiority of the detection chip of this embodiment, its working principle is as follows: the resistance divider circuit 4 is used to generate the voltage V1 input to the comparator Q, the output of the first inverter A1 in the logic combination circuit 2 It is used to control the charging and discharging state of the charging and discharging capacitor C1. The voltage generated at both ends of the charging and discharging capacitor C1 is shaped by the Schmidt shaping circuit 5, and then the control signal is output through the detection signal output terminal Vout. At the same time, the Schmidt The voltage output by the special shaping circuit 5 controls the turn-on of the first MOS transistor M1 and the second MOS transistor M2 in the recovery voltage setting circuit 6 at the same time, so as to set the recovery voltage. When the voltage of the voltage setting terminal Vin is set so that V1 is lower than Verf, the power supply input terminal VDD charges the charging and discharging capacitor C1 through the third MOS transistor M3 and the fifth resistor R5. If within the specified time, when the voltage setting When the voltage of the fixed terminal Vin rises so that V1 is higher than Verf, the charging and discharging capacitor C1 is discharged immediately, and the time is recalculated; if within the specified time, when the voltage of the voltage setting terminal Vin does not rise to make V1 higher than Verf , the detection signal output terminal Vout is at a low level and the charging and discharging capacitor C1 continues to charge until the voltage at the voltage setting terminal Vin rises to the recovery voltage, the detection signal output terminal Vout returns to a high level, the charging and discharging capacitor C1 is discharged, and the time is reset calculation; during this process, when the detection signal output terminal Vout is at a high level, the first MOS transistor M1 is turned on, the second MOS transistor M2 is turned off, the first resistor R1 is short-circuited, and the fourth resistor R4 participates in voltage division; when the detection signal output When the terminal Vout is at a low level, the first MOS transistor M1 is turned off, the second MOS transistor M2 is turned on, the first resistor R1 participates in voltage division, and the fourth resistor R4 is short-circuited.

In addition, since the resistance values of the first resistor R1 and the fourth resistor R4 are equal, when the voltage Vout of the detection signal output terminal Vout=1 (that is, at a high level), the divided voltage V1 is equal to the turn-on voltage required by the reference voltage Verf :

$\mathrm{<span\; class="notranslate">\; V</span>}\mathrm{<span\; class="notranslate">\; i</span>}\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; o</span>}\mathrm{<span\; class="notranslate">\; p</span>}\mathrm{<span\; class="notranslate">\; e</span>}\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; R</span>}\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; R</span>}\mathrm{<span\; class="notranslate">\; 3</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; R</span>}\mathrm{<span\; class="notranslate">\; 4</span>}}{\mathrm{<span\; class="notranslate">\; R</span>}\mathrm{<span\; class="notranslate">\; 3</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; R</span>}\mathrm{<span\; class="notranslate">\; 4</span>}}<span\; class="notranslate">\; ;</span>$

When the voltage Vout of the detection signal output terminal Vout=0 (that is, when it is at a low level), the divided voltage V1 is equal to the recovery voltage required by the reference voltage Verf:

$\mathrm{<span\; class="notranslate">\; V</span>}\mathrm{<span\; class="notranslate">\; i</span>}\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; r</span>}\mathrm{<span\; class="notranslate">\; e</span>}\mathrm{<span\; class="notranslate">\; cov</span>}\mathrm{<span\; class="notranslate">\; e</span>}\mathrm{<span\; class="notranslate">\; r</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; R</span>}\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; R</span>}\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; R</span>}\mathrm{<span\; class="notranslate">\; 3</span>}}{\mathrm{<span\; class="notranslate">\; R</span>}\mathrm{<span\; class="notranslate">\; 3</span>}}<span\; class="notranslate">\; ;</span>$

And the ratio of turn-on voltage to recovery voltage:

$\frac{Vi\mathrm{no}\left(re\mathrm{cov}er\right)}{Vi\mathrm{no}\left(ope\mathrm{no}\right)}=\frac{(R1+R2+R3)(R3+R4)}{(R2+R3+R4)R3}=1+\frac{R4}{R3},$ In this way, the turn-on voltage and the recovery voltage are only related to the third resistor R3 and the fourth resistor R4, thereby weakening the influence of the resistor divider circuit 4 on the turn-on voltage and the recovery voltage, which is beneficial to improve the variable-variability of the input voltage, Guarantee the final detection accuracy.

The above is only a preferred embodiment of the utility model, and does not limit the patent scope of the utility model. Any equivalent structure or equivalent process conversion made by using the specification of the utility model and the contents of the accompanying drawings may be directly or indirectly used in Other relevant technical fields are all included in the patent protection scope of the present utility model in the same way.

Claims (7)

1. An anti-jamming low voltage detection chip is characterized in that: it comprises: A capacitor charging and discharging circuit for realizing voltage output through charging and discharging of a capacitor, the capacitor charging and discharging circuit is provided with a power input terminal; A logic combination circuit for controlling the opening and closing of the capacitor charging and discharging circuit, the output terminal of the logic combination circuit is connected to the input terminal of the capacitor charging and discharging circuit; A reference voltage generation circuit for providing a reference voltage to the logic combination circuit, the output end of the reference voltage generation circuit is connected to the input end of the logic combination circuit; A resistor divider circuit for setting the voltage value input to the logic combination circuit, the resistor divider circuit is connected to the input terminal of the logic combination circuit, and the resistor divider circuit is provided with a voltage setting terminal; A Schmidt shaping circuit for outputting the detection signal after shaping the voltage output by the capacitor charging and discharging circuit, the Schmidt shaping circuit is connected to the output end of the capacitor charging and discharging circuit, and the Schmidt shaping circuit A detection signal output terminal is provided; and A recovery voltage setting circuit for setting the ratio of the resistance voltage divider circuit according to the voltage value output by the Schmidt shaping circuit, and the recovery voltage setting circuit is connected to the output terminal of the Schmidt shaping circuit and the resistance voltage divider circuit between. 2. An anti-jamming low-voltage detection chip according to claim 1, characterized in that: the capacitor charging and discharging circuit includes a third MOS transistor, a fourth MOS transistor, a charging and discharging capacitor and a fifth resistor, and the first The gates of the three MOS transistors and the gate of the fourth MOS transistor are connected to the output terminal of the logic combination circuit at the same time, and the drains of the third MOS transistor and the fourth MOS transistor are respectively connected to both ends of the fifth resistor, The source and the substrate of the third MOS transistor are connected to the power input terminal at the same time, the source and the substrate of the fourth MOS transistor are connected to the ground at the same time, one end of the charging and discharging capacitor is connected to the ground, and the other end is connected to the Schmidt shaping input to the circuit. 3. An anti-jamming low-voltage detection chip as claimed in claim 1 or 2, characterized in that: the recovery voltage setting circuit includes a first MOS transistor and a second MOS transistor, and the gate of the first MOS transistor The pole and the gate of the second MOS transistor are connected to the output terminal of the Schmidt shaping circuit at the same time, the source and substrate of the first MOS transistor are connected to the voltage setting terminal at the same time, the source and substrate of the second MOS transistor The bottom of the first MOS transistor and the drain of the second MOS transistor are respectively connected to a resistor divider circuit. 4. A kind of anti-interference low voltage detection chip as claimed in claim 3, is characterized in that: described Schmidt shaping circuit comprises the Schmidt shaping unit and the second inverter that are connected in sequence, and described Schmidt The input terminal of the shaping unit is connected to the output terminal of the capacitor charging and discharging circuit, the output terminal of the second inverter is used as the detection signal output terminal, and the gate of the first MOS transistor and the gate of the second MOS transistor are connected simultaneously Between the input terminal of the second inverter and the output terminal of the Schmidt shaping unit. 5. An anti-jamming low voltage detection chip as claimed in claim 3, characterized in that: said resistor divider circuit comprises a first resistor, a second resistor, a a third resistor and a fourth resistor; The input terminal of the logic combination circuit is connected between the second resistor and the third resistor, the drain of the first MOS transistor is connected between the first resistor and the second resistor, and the drain of the second MOS transistor Connected between the third resistor and the fourth resistor. 6 . The anti-jamming low voltage detection chip according to claim 5 , wherein the resistance value of the first resistor is equal to the resistance value of the fourth resistor. 7. A kind of anti-jamming low voltage detection chip as claimed in claim 5, it is characterized in that: described logic combination circuit comprises comparator and first inverter, and the anode of described comparator is connected with first resistance and second Between the two resistors, the negative electrode is connected to the output terminal of the reference voltage generating circuit, and the output terminal is connected to the input terminal of the first inverter, and the output terminal of the first inverter is connected to the input terminal of the capacitor charging and discharging circuit.