CN205789112U - Circuit board and memory using the circuit board - Google Patents

Abstract

The utility model provides a memory of circuit board and applied this circuit board. The circuit board comprises a first surface and a second surface which are opposite in parallel, the first surface and the second surface are connected through side surfaces, the circuit board further comprises a first heat dissipation layer arranged on the first surface and a second heat dissipation layer arranged on the second surface, and the first heat dissipation layer and the second heat dissipation layer comprise a plurality of heat dissipation holes. Through the heat dissipation layer and the heat dissipation holes, heat in the circuit board can be rapidly discharged to reduce the temperature of the circuit board. The utility model also provides a memory of using this circuit board.

Description

Circuit board and memory using the circuit board

technical field

The utility model relates to a circuit board, and also relates to a memory using the circuit board.

Background technique

The heat dissipation efficiency of existing PCB inner layers is generally low. Taking the memory stick as an example, when the memory stick works at a high frequency, a large amount of heat accumulated in the memory stick PCB cannot be quickly discharged, and the temperature of the memory stick will rise rapidly. When the temperature of the memory stick rises to a critical value, the memory stick will no longer be able to maintain a high-frequency working state.

Utility model content

In view of this, it is necessary to provide a circuit board that can provide rapid heat dissipation and a memory using the circuit board.

A circuit board, comprising a first surface and a second surface parallel to each other, the first surface and the second surface are connected through a side surface, and the circuit board also includes a first heat dissipation layer arranged on the first surface and a The second heat dissipation layer on the second surface, the first heat dissipation layer and the second heat dissipation layer include a plurality of heat dissipation holes.

Preferably, the first surface includes a first heat dissipation area and a first component area, and the first heat dissipation layer is disposed on the first heat dissipation area.

Preferably, a first isolation groove is provided between the first heat dissipation area and the first component area.

Preferably, the first heat dissipation layer is copper foil, and when the circuit board is etched, the copper foil in the area where the first heat dissipation layer is located is not etched to form the first heat dissipation layer.

Preferably, the plurality of cooling holes include at least one through hole.

A memory, including a circuit board and a plurality of memory chips, the circuit board includes a first surface and a second surface parallel to each other, the first surface and the second surface are connected by a side surface, the circuit board also includes a device The first heat dissipation layer on the first surface and the second heat dissipation layer on the second surface, the first heat dissipation layer and the second heat dissipation layer include some heat dissipation holes.

Preferably, the memory includes several heat dissipation terminals, and the pins of the plurality of memory chips are correspondingly connected to the several heat dissipation terminals.

Preferably, the first surface includes a first isolation groove, the first heat dissipation layer is arranged on the second side of the first isolation groove, and the plurality of heat dissipation ends are arranged on the first side of the first isolation groove , the distance between the plurality of cooling ends and the first isolation slot is not greater than a first preset distance.

Preferably, the storage includes a heat sink and an interface, the interface is located at the first end of the storage, and the heat sink is used to be detachably socketed on the second end of the storage.

Preferably, the heat sink is closely connected to the plurality of memory chips, the first heat dissipation layer and the second heat dissipation layer.

Through the heat dissipation layer and the heat dissipation holes, the heat in the circuit board can be quickly discharged to reduce the temperature of the circuit board.

Description of drawings

FIG. 1 is a schematic diagram of a preferred embodiment of the circuit board of the present invention.

FIG. 2 is a cross-sectional view of a preferred embodiment of the circuit board shown in FIG. 1 .

FIG. 3 is a schematic diagram of a preferred embodiment of the storage device of the present invention.

FIG. 4 is another schematic diagram of a preferred embodiment of the storage device of the present invention.

FIG. 5 is a partial schematic diagram of another preferred embodiment of the storage device of the present invention.

Explanation of main component symbols

The following specific embodiments will further illustrate the utility model in conjunction with the above-mentioned accompanying drawings.

detailed description

Please refer to FIG. 1 and FIG. 2 , in a preferred embodiment of the circuit board 100 of the present invention, the circuit board 100 includes a first surface 11 and a second surface 12 opposite to each other in parallel, and the first surface 11 and the second surface 12 are connected by side surfaces 13 . The circuit board 100 further includes a first heat dissipation layer 110 disposed on the first surface 11 and a second heat dissipation layer 120 disposed on the second surface 12 . The first heat dissipation layer 110 includes a plurality of heat dissipation holes 21 . The second heat dissipation layer 120 includes several heat dissipation holes.

In this embodiment, the first surface 11 of the circuit board 100 includes a first heat dissipation area 31 and a first component area 41. A first isolation groove 51 is provided between the first heat dissipation area 31 and the first component area 41 . The first heat dissipation layer 110 is disposed on the first heat dissipation area 31 .

In this embodiment, the second surface 12 of the circuit board 100 includes a second heat dissipation area 32 (not shown) and a second component area 42 (not shown). A second isolation groove 52 is provided between the second heat dissipation area 32 and the second component area 42 . The second heat dissipation layer 120 is disposed on the second heat dissipation area 32 . Since the second surface 12 and the first surface 11 are designed symmetrically in this embodiment, the second heat dissipation area 32 , the second component area 42 and the second isolation groove 52 are not shown in the figure.

In other embodiments, the first heat dissipation layer 110 may be arranged on the first surface 11 of the circuit board 100 in an irregular shape, such as around each solder pad of the first component region 41, without limitation. In the first cooling zone 31. Similarly, the second heat dissipation layer 120 can be arranged on the second surface 12 of the circuit board 100 in an irregular shape, such as around each solder pad of the second component area 42, without being limited to the first Two heat dissipation zones 32 .

In other implementations, the first heat dissipation layer 110 and the second heat dissipation layer 120 may have an asymmetric design.

In this embodiment, the first isolation groove 51 and the second isolation groove 52 are used to prevent the heat dissipation layer from contacting the pad.

FIG. 2 is a schematic cross-sectional view of the circuit board 100 of the present invention. In this embodiment, the circuit board 100 includes a first layer 61 , a second layer 62 and an intermediate layer 60 .

In this embodiment, the first layer 61 is a copper foil layer, the second layer 62 is a substrate layer, and the intermediate layer 60 is an inner film layer. The middle layer 60 can be made of resin, epoxy glass fiber and other materials.

In this embodiment, the plurality of cooling holes 21 are all through holes. The plurality of heat dissipation holes 21 sequentially pass through the first heat dissipation layer 110 , the first layer 61 , the middle layer 60 , the second layer 62 and the second heat dissipation layer 120 .

In other embodiments, the first heat dissipation layer 110 is copper foil, and when the copper foil of the circuit board is etched, the copper foil in the area where the first heat dissipation layer 110 is located is not etched to form the first heat dissipation layer 110, The wiring between the first heat dissipation layer 110 and the first component area 41 is separated by the first isolation groove 51 to avoid signal interference. Similarly, the second heat dissipation layer 120 can be formed by copper foil layer without etching, and the wiring between the second heat dissipation layer 120 and the second component area 42 is divided by the second isolation groove 52 , to avoid signal interference.

Correspondingly, if the first heat dissipation layer 110 and the second heat dissipation layer 120 are formed by copper foil without etching, the first heat dissipation layer 110 and the second heat dissipation layer 120 can be applied to inner layers of a multilayer circuit board.

In this embodiment, one end of the wires in the first component region 41 is located near the first isolation trench 51 . Similarly, one end of the wires in the second component area 42 is located near the second isolation trench 52 .

In other embodiments, the plurality of heat dissipation holes 21 may be filled with specific metals to assist heat dissipation, and the specific metals include but not limited to copper.

In other embodiments, the plurality of cooling holes 21 may be partly through holes, and partly be holes opened to specific positions. The plurality of cooling holes 21 can also all be opened to a specific position, such as all opened to the middle layer 60 without penetrating through the middle layer 60 .

Please refer to FIG. 3 and FIG. 4 , the memory 200 of the present invention includes a multi-layer circuit board and a plurality of memory chips 71 . In a preferred embodiment of the multilayer circuit board, the multilayer circuit board includes the circuit board 100 . The memory 200 also includes an interface 81 and a heat sink 300 . The interface 81 is located at the first end of the memory 200 .

In this embodiment, the heat sink 300 is detachably socketed on the second end of the storage device 200 . When the heat sink 300 is socketed on the second end of the memory 200, the heat sink 300 is closely connected to the plurality of memory chips 71, the first heat dissipation layer 110 and the second heat dissipation layer 120. . The heat sink 300 is used to dissipate heat for the first heat dissipation layer 110 , the second heat dissipation layer 120 and the plurality of memory chips 71 .

In this embodiment, the first end of the memory 200 is parallel to the second end of the memory 200 .

In other implementation manners, the heat sink 300 can also be socketed on the third end of the memory 200 . The third end of the memory 200 is perpendicular to the first end of the memory 200 .

In other implementation manners, the heat sink 300 may also be welded on the first heat dissipation layer 110 or the second heat dissipation layer 120 .

The heat sink 300 can be made of metal material or other materials with good thermal conductivity. In this embodiment, the heat sink 300 is made of aluminum.

In this embodiment, the memory 200 is a memory stick. The interface 81 is a gold finger extending from the first end of the circuit board 100 . The interface 81 is used to connect a memory slot.

Please refer to FIG. 5 , in another preferred implementation manner of the memory 200 of the present invention, the memory 200 includes a multi-layer circuit board (not shown) and at least one memory chip 91 . The first surface of the multilayer circuit board includes a first isolation groove 51 , an interface 81 , a first heat dissipation layer 110 and heat dissipation terminals A1 - A8 . The first isolation groove 51 is located between the first heat dissipation layer 110 and the heat dissipation ends A1 - A8 . The memory chip 91 includes pins 1-8. The pin 1 of the memory chip 91 is connected to the pin 1 of the interface 81 . The pin 2 of the memory chip 91 is connected to the pin 2 of the interface 81 . The pin 3 of the memory chip 91 is connected to the pin 3 of the interface 81 . The pin 4 of the memory chip 91 is connected to the pin 4 of the interface 81 . The pin 5 of the memory chip 91 is connected to the pin 5 of the interface 81 . The pin 6 of the memory chip 91 is connected to the pin 6 of the interface 81 . The pin 7 of the memory chip 91 is connected to the pin 7 of the interface 81 . The pin 8 of the memory chip 91 is connected to the pin 8 of the interface 81 .

In this embodiment, the pin 1 of the memory chip 91 is also connected to the heat dissipation terminal A1 of the memory 200 . The pin 2 of the memory chip 91 is also connected to the heat dissipation terminal A2 of the memory 200 . The pin 3 of the memory chip 91 is also connected to the heat dissipation terminal A3 of the memory 200 . The pin 4 of the memory chip 91 is also connected to the heat dissipation terminal A4 of the memory 200 . The pin 5 of the memory chip 91 is also connected to the heat dissipation terminal A5 of the memory 200 . The pin 6 of the memory chip 91 is also connected to the heat dissipation terminal A6 of the memory 200 . The pin 7 of the memory chip 91 is also connected to the heat dissipation terminal A7 of the memory 200 . The pin 8 of the memory chip 91 is also connected to the heat dissipation terminal A8 of the memory 200 .

The heat dissipation ends A1-A8 are all disposed on the first side of the first isolation slot 51 in close contact with the first isolation slot 51. The first heat dissipation layer 110 is disposed on the second side of the first isolation groove 51 . The distance between the heat dissipation ends A1 - A8 and the first isolation slot 51 is not greater than a first preset distance. In this implementation manner, the first preset distance is 20 miles.

In this embodiment, the pin wiring of the memory chip 91 is located on different signal layers of the multilayer circuit board.

In other implementation manners, at least one of the pins 1-8 of the memory chip 91 is correspondingly connected to the heat dissipation terminals A1-A8.

In another embodiment, the pins 1 and 2 of the memory chip 91 are data pins, the pin 1 of the memory chip 91 is correspondingly connected to the heat dissipation terminal A1, and the pins of the memory chip 91 are 2 is correspondingly connected to the heat dissipation terminal A2. The pins 4-8 of the memory chip 91 are not connected to the heat sink due to less heat generation.

In this implementation manner, the memory 200 further includes several memory chips and several heat dissipation terminals. Pins of the plurality of memory chips are correspondingly connected to the plurality of cooling terminals.

In other implementation manners, the memory 200 further includes several sets of inner layer heat dissipation terminals located on the inner layer of the multilayer circuit board. In the inner-layer routing, each inner-layer routing is correspondingly connected to the plurality of groups of inner-layer cooling terminals.

Through the first heat dissipation layer 110 , the second heat dissipation layer 120 and the plurality of heat dissipation holes 21 , the heat accumulated in the circuit board 100 can be quickly discharged to reduce the temperature of the circuit board 100 . Similarly, the memory 200 further accelerates the heat dissipation speed of the circuit board 100 through the heat sink 300 , and the heat sink 300 can also be used to dissipate heat on the plurality of memory chips 71 .

Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present utility model without limitation. Although the utility model has been described in detail with reference to the preferred embodiments, those of ordinary skill in the art should understand that the utility model can be Modifications or equivalent replacements shall be made to the technical solutions without departing from the spirit and scope of the technical solutions of the present utility model.

Claims (10)

1. a circuit board, including parallel relative first surface and second surface, described first surface and second surface pass through Side surface connects, it is characterised in that:

Described circuit board also includes the first heat dissipating layer being located at first surface and is located at the second heat dissipating layer of second surface, described One heat dissipating layer and the second heat dissipating layer include some louvres.

2. circuit board as claimed in claim 1, it is characterised in that: described first surface includes the first radiating area and first yuan of device Part district, described first heat dissipating layer is located at described first radiating area.

3. circuit board as claimed in claim 2, it is characterised in that: it is provided with between described first radiating area and the first components and parts district First isolation channel.

4. circuit board as claimed in claim 1, it is characterised in that: described first heat dissipating layer is Copper Foil, when described circuit board enters During row etching, region Copper Foil residing for described first heat dissipating layer is not etched described first heat dissipating layer of formation.

5. circuit board as claimed in claim 1, it is characterised in that: described some louvres include at least one through hole.

6. a memorizer, including a circuit board and some storage chips, described circuit board includes parallel relative first surface And second surface, described first surface and second surface are connected by side surface, it is characterised in that:

Described circuit board also includes the first heat dissipating layer being located at first surface and is located at the second heat dissipating layer of second surface, described One heat dissipating layer and the second heat dissipating layer include some louvres.

7. memorizer as claimed in claim 6, it is characterised in that: described memorizer includes some radiating ends, described some deposits The pin correspondence of storage chip connects described some radiating ends.

8. memorizer as claimed in claim 6, it is characterised in that: described first surface includes the first isolation channel, described first Heat dissipating layer is arranged at the second side of described first isolation channel, and described some radiating ends are arranged at the first of described first isolation channel Side, described some radiating ends are not more than the first predeterminable range with the distance of described first isolation channel.

9. memorizer as claimed in claim 6, it is characterised in that: described memorizer includes a radiator and an interface, described Interface is positioned at the first end of described memorizer, and described radiator is for being removably socketed on the second end of described memorizer.

10. memorizer as claimed in claim 9, it is characterised in that: described radiator is close to be connected to described some storage cores Sheet, described first heat dissipating layer and described second heat dissipating layer.