CN206893620U - Thin film transistor (TFT), array base palte and display device - Google Patents

Abstract

The utility model discloses a kind of thin film transistor (TFT), array base palte and display device, the thin film transistor (TFT) includes：Active layer, source electrode and drain electrode, active layer includes several intervals and the active spirte being independently arranged, source electrode covers the subregion of each active spirte, and drain electrode covers the subregion of active spirte, not is electrically conductive region by source electrode and the covered region that drains on active spirte；The electrically conductive region of arbitrary neighborhood surrounds open area with source electrode, drain electrode, the electrically conductive connection figure that the electrically conductive region adjacent with corresponding two is all connected with is provided with least one opening region, electrically conductive connection figure is at most connected with one of source electrode and drain electrode.Thin film transistor (TFT) provided by the utility model has good thermal diffusivity and can effectively avoid the generation of leakage current.

Description

Thin film transistor, array substrate and display device

technical field

The utility model relates to the field of display technology, in particular to a thin film transistor, an array substrate and a display device.

Background technique

Thin film transistors can be used as switching elements for transmitting signals or driving elements for providing current paths. The active layer, the source and the drain are the core devices in the thin film transistor. The conventional active layer is a complete plate pattern, the source covers a part of the active layer, and the drain covers a part of the active layer. The portion of the source layer not covered by the source and the drain is the conductive region of the thin film transistor. After a certain gate-source voltage is applied to the thin film transistor, a conductive channel is formed in the conductive region, and the source and drain of the thin film transistor are turned on.

Since the conventional conductive region is plate-shaped, its heat dissipation effect is poor, so that the temperature of the conductive region rises, and the electrical characteristics of the thin film transistor shift.

In order to solve this technical problem, conventional thin film transistors have been improved in the prior art. Figure 1 is a top view of a thin film transistor in the prior art, and Figure 2 is a schematic cross-sectional view of C-C in Figure 1, as shown in Figures 1 and 2, the active layer includes several active sub-patterns that are spaced and independently arranged 3. Both the source electrode 1 and the drain electrode 2 cover a partial area of each active sub-pattern, and the part of the active sub-pattern 3 not covered by the source electrode 1 and the drain electrode 2 is a conductive area. Since there is a gap between adjacent conductive regions, the conductive region can dissipate heat through the gap, thereby effectively preventing the temperature of the active layer from rising.

When the active layer film is etched by an etching process to form each active sub-pattern, it is inevitable that a slope will be formed at the edge region of each active sub-pattern 3. At this time, the conductive area includes the main conductive area main and the edge conductive region sub located on both sides of the main conductive region main. Since the threshold voltage of the edge conductive region sub is lower than the threshold voltage of the main conductive region main, the edge conductive region sub will form a conductive channel before the main conductive region main (the edge conductive region is turned on before the main conductive region ), at this time there will be a leakage current in the edge conductive region sub, correspondingly the voltage-ampere characteristic curve of the thin film transistor will appear a humping phenomenon, and the working stability of the thin film transistor is poor.

As the number of active sub-patterns increases, the number of edge conductive regions in the thin film transistor increases, the leakage current phenomenon becomes more obvious, and the humping phenomenon in the volt-ampere characteristic curve of the thin film transistor becomes more apparent.

Utility model content

The utility model aims at at least solving one of the technical problems in the prior art, and proposes a thin film transistor, an array substrate and a display device.

In order to achieve the above object, the utility model provides a thin film transistor, including: an active layer, a source and a drain, the active layer includes several intervals and independently arranged active sub-patterns, the source covers A partial area of each active sub-pattern, the drain covers a partial area of the active sub-pattern, and the area of the active sub-pattern not covered by the source and the drain can be conductive area;

Any adjacent conductive region and the source and the drain form an open region, and at least one of the open regions is provided with a conductive connection connected to the corresponding two adjacent conductive regions. pattern, the conductive connection pattern is at most connected to one of the source and the drain.

Optionally, a side of the outermost active sub-pattern facing away from other active sub-patterns is formed with a raised pattern.

Optionally, the active sub-patterns are strip-shaped and extend along a first direction, all the active sub-patterns are arranged in parallel along a second direction, and the first direction is perpendicular to the second direction.

Optionally, the source electrode includes a first conductive strip and several second conductive strips arranged in parallel along the first direction, the second conductive strips extend along the second direction, and the second conductive strips A strip covers a partial area of the active sub-pattern, and the first conductive strip connects first ends of each of the second conductive strips;

The drain electrode includes a third conductive strip and several fourth conductive strips arranged in parallel along the first direction, the fourth conductive strip extends along the second direction, and the fourth conductive strip covers the In a partial area of the active sub-pattern, the third conductive strips are connected to the second ends of the fourth conductive strips;

All the second conductive strips and all the fourth conductive strips are arranged alternately along the first direction.

Optionally, the conductive connection pattern is not connected to either the source or the drain.

Optionally, the distance between the conductive connection pattern and the source and the drain is equal.

Optionally, the ratio of the area of the conductive connection pattern to the area of the corresponding opening area is: 2/5˜3/5.

Optionally, the range of the width of the active sub-pattern includes: 5um˜15um.

In order to achieve the above object, the utility model also provides an array substrate, including: the thin film transistor as mentioned above.

To achieve the above purpose, the present utility model also provides a display device, comprising: the above-mentioned array substrate.

The utility model has the following beneficial effects:

The utility model provides a thin-film transistor, an array substrate and a display device. In the opening area surrounded by adjacent conductive regions, source electrodes and drain electrodes, a conductive A conductive connection pattern, the conductive connection pattern is at most connected to one of the source and the drain, so that both ends of the edge conductive region are connected to the source or drain at the same time, thereby effectively solving the leakage current generated in the edge conductive region The problem. In addition, the conductive region and the conductive connection pattern on the active sub-pattern can dissipate heat through the opening, thus effectively improving the stability of the thin film transistor. It can be seen that the thin film transistor provided by the present invention has good heat dissipation and can effectively avoid leakage current.

Description of drawings

FIG. 1 is a top view of a thin film transistor in the prior art;

Fig. 2 is a schematic cross-sectional view of C-C direction in Fig. 1;

FIG. 3 is a top view of a thin film transistor provided in Embodiment 1 of the present invention;

Figure 4 is an enlarged schematic view of area A in Figure 3;

Fig. 5 is a schematic diagram of the volt-ampere characteristic curve of the thin film transistor provided by the present invention and the thin film transistor in the prior art;

Figure 6 is an enlarged schematic view of area B in Figure 3;

FIG. 7 is a top view of a thin film transistor provided in Embodiment 2 of the present invention.

detailed description

In order for those skilled in the art to better understand the technical solutions of the present invention, a thin film transistor, an array substrate and a display device provided by the present invention will be described in detail below with reference to the accompanying drawings.

The thin film transistor in the present invention may be a top-gate thin film transistor or a bottom-gate thin film transistor, which is not limited in the present invention.

Fig. 3 is a top view of a thin film transistor provided by Embodiment 1 of the present utility model, and Fig. 4 is an enlarged schematic diagram of area A in Fig. 3, as shown in Fig. 3 and Fig. 4, the thin film transistor includes: an active layer, a source 1 and drain 2, the active layer includes several active sub-patterns 3 that are spaced apart and independently arranged, the source 1 covers a part of each active sub-pattern 3, and the drain 2 covers a part of the active sub-pattern 3, The area on the active sub-pattern 3 not covered by the source 1 and the drain 2 is a conductive area (also called a channel area), and any adjacent conductive area forms an opening with the source 1 and the drain 2 Area 6, at least one opening area 6 is provided with a conductive connection pattern 4 connected to the corresponding two adjacent conductive areas, and the conductive connection pattern 4 is at most connected to one of the source electrode 1 and the drain electrode 2 .

As an optional solution in this embodiment, the active sub-pattern 3 is strip-shaped and extends along the first direction X, all active sub-patterns 3 are arranged in parallel along the second direction Y, and the first direction X direction is parallel to the second direction Y. The two directions Y are vertical.

In practical applications, it is found that when the width of the active sub-pattern 3 is large, the heat dissipation effect is affected due to the size of the active sub-pattern 3 being too large, and when the width of the active sub-pattern 3 is small, the main conductive area main The corresponding narrowing of the width will increase the threshold voltage of the thin film transistor, resulting in high power consumption. Considering the above two points, in this embodiment, preferably, the width W1 of the active sub-pattern 3 ranges from 5 um to 15 um. In this case, low power consumption can be achieved while achieving a better heat dissipation effect of the thin film transistor.

Optionally, the distance W2 between adjacent active sub-patterns 3 ranges from 5um to 15um.

It should be noted that, in this embodiment, the conductive connection pattern 4 and the active sub-pattern 3 are integrally formed through one patterning process. The connection between the conductive connection pattern 4 and the conductive region in this embodiment specifically means that the side of the conductive connection pattern 4 is closely connected with the side of the part of the active sub-pattern 3 located in the conductive region.

For the convenience of description, the two active sub-patterns 3 in FIG. 4 are respectively referred to as a first active sub-pattern 3a and a second active sub-pattern 3b. When the integrated first active sub-pattern 3a, second active sub-pattern 3b and conductive connection pattern 4 are formed by one patterning process, the first active sub-pattern 3a and the second active sub-pattern 3a and the second active The edges of the sub-pattern 3b are all connected to the edges of the conductive connection pattern 4 to form an edge conductive region sub with both ends connected to the source 1 or both ends connected to the drain 2 at the same time. Since both ends of the edge conductive region sub are connected to the source 1 (or drain 2) at the same time, the potentials of the two ends of the edge conductive region sub are equal at any time, so the inside of the edge conductive region sub is not There will be source-leakage current.

It can be seen that even if the edge conductive region sub is turned on under the action of the gate voltage, since there is no source-leakage current in the edge conductive region sub, there will be no problem of leakage current. It can be seen that the technical solution of the present invention can effectively solve the problem of leakage current generated after the edge conductive region sub is turned on before the main conductive region main.

Fig. 5 is a schematic diagram of the volt-ampere characteristic curves of the thin film transistor provided by the present invention and the thin film transistor in the prior art. As shown in Fig. 5, the thin film transistor in the prior art has a large number of edge regions capable of generating leakage current. Therefore, there will be a problem of obvious leakage current, and the humping phenomenon in the volt-ampere characteristic curve is obvious. However, in the technical solution of the present utility model, by setting the conductive connection pattern 4 connecting the adjacent active sub-pattern 3 in the opening area 6, and the conductive connection pattern 4 is at most connected to the source electrode 1 and the drain electrode 2 One is connected to change the edge conductive region sub whose two ends are respectively connected to the source 1 and the drain 2 in the prior art to an edge conductive region sub whose two ends are connected to the source 1 or the drain 2 at the same time, so that in No source-leakage current will be generated in the edge conductive region sub at any time, thus effectively solving the problem of leakage current generated after the edge conductive region sub is turned on before the main conductive region main. At this time, the humping phenomenon does not appear in the volt-ampere characteristic curve of the thin film transistor.

In addition, the conductive region on the active sub-pattern 3 can dissipate heat through the opening region 6 after being turned on, thus effectively improving the stability of the thin film transistor.

It can be seen that the thin film transistor provided by this embodiment has good heat dissipation and can effectively avoid leakage current.

In this embodiment, when the area of the conductive connection pattern 4 is too large, the area of the heat dissipation area not covered by the conductive connection pattern 4 in the opening area 6 is too small, which affects the heat dissipation effect; If the area is too small, the requirements for the production process of the conductive connection pattern 4 are relatively high. In order to balance the heat dissipation effect and the difficulty of the production process, in this embodiment, preferably, the ratio of the area of the conductive connection pattern 4 to the area of the opening area 6 is: 2/5˜3/5.

In the case that the opening area 6 and the conductive connection pattern 4 are both rectangular, and the width W2 of the two is equal, the ratio of the length L2 of the conductive connection pattern 4 to the length L1 of the opening area 6 is: 2/5 to 3/5 .

As a specific solution in this embodiment, the width W1 of the active sub-pattern 3 is 5um, the length L1 of the conductive region (channel) is 5um, the width W2 of the opening region 6 is 5um, and the length L1 of the opening region 6 is 5um. The width W2 of the conductive connection pattern 4 is 5um, the length L2 of the conductive connection pattern 4 is 2um, and the distances a and b from the conductive connection pattern 4 to the source 1 and drain 2 are both 1.5um. At this time, the heat dissipation effect of the thin film transistor is better, the working performance is stable, and there is no obvious leakage current problem.

It should be noted that the conductive connection pattern 4 is not connected to the source 1 and the drain 2, and the distance between the conductive connection pattern 4 and the source 1 and the drain 2 is equal only in the present invention. A preferred option for . Under the condition that the distance between the conductive connection pattern 4 and the source electrode 1 and the drain electrode 2 is the same, the part not covered by the source electrode 1 and the drain electrode 2 on the active sub-pattern 3 is covered by the conductive connection pattern 4 The constituting figure is an axisymmetric figure, which can effectively ensure the stability of the thin film transistor in operation. Those skilled in the art should know that in the present invention, it is only necessary to connect the conductive connection pattern 4 to two adjacent conductive regions corresponding to the opening region 6, and the conductive connection pattern 4 is at most connected to the source electrode 1 and the source electrode 1. One of the drains 2 is connected to improve the leakage current problem while ensuring the heat dissipation effect. The specific situation will not be described in detail here.

In this embodiment, preferably, each opening region 6 is provided with a conductive connection pattern 4 that can be electrically connected to the corresponding two adjacent conductive regions. At this time, only the two outermost active sub-patterns 3 in the thin film transistor The two ends of the edge of the side facing away from other active sub-patterns 3 are respectively connected to the source 1 and the drain 2. At this time, the number of edge conductive regions sub that can generate source and drain currents in the thin film transistor can be reduced as much as possible. , thereby effectively reducing the generation of leakage current.

Fig. 6 is an enlarged schematic diagram of area B in Fig. 3. As shown in Fig. 6, in order to avoid leakage in the edge conductive region sub1 of the two outermost active sub-patterns 3c facing away from other active sub-patterns 3 For the generation of electric current, preferably, the side of the outermost active sub-pattern 3 c facing away from other active sub-patterns 3 is formed with a raised pattern 5 . The raised pattern 5, the active sub-pattern 3 and the conductive connection pattern 4 are integrally formed through one patterning process.

In this embodiment, the length of the edge conductive region sub on the side of the outermost active sub-pattern 3c facing away from other active sub-patterns 3 can be increased by setting the raised pattern 5. When the width of the edge conductive region sub1 remains unchanged, the threshold voltage of the outermost edge conductive region sub1 increases accordingly. When the threshold voltage of the outermost edge conductive region sub1 is greater than or equal to the threshold voltage of the main conductive region main, the outermost edge conductive region sub1 will conduct later than the main conductive region main, or be connected with the main conductive region main. The main conductive region main is turned on at the same time, and at this time, there will be no leakage current problem in the outermost edge conductive region sub1.

Embodiment 1 of the present utility model provides a thin film transistor, by setting a conductive connection pattern connected to the two adjacent conductive regions in the opening area surrounded by the adjacent conductive regions, source electrodes, and drain electrodes , the conductive connection pattern is at most connected to one of the source and the drain, so that both ends of the edge conductive region are connected to the source or drain at the same time, thereby effectively solving the problem of leakage current in the edge conductive region. In addition, the conductive region and the conductive connection pattern on the active sub-pattern can dissipate heat through the opening, thus effectively improving the stability of the thin film transistor. It can be seen that the thin film transistor provided by this embodiment has good heat dissipation and can effectively avoid leakage current.

FIG. 7 is a top view of a thin film transistor provided in Embodiment 2 of the present invention. As shown in FIG. 7 , the difference from Embodiment 1 above is that the source 1 in this embodiment includes a first conductive strip 11 and Several second conductive strips 12 arranged in parallel along the first direction X, the second conductive strips 12 extend along the second direction Y, the second conductive strips 12 cover a part of the active sub-pattern 3, and the first conductive strips 11 connect each The first end of the second conductive strip 12 . The drain 2 includes a third conductive strip 21 and several fourth conductive strips 22 arranged in parallel along the first direction X, the fourth conductive strip 22 extends along the second direction Y, and the fourth conductive strip 22 covers the active sub-pattern 3 Part of the area, the third conductive strips 21 are connected to the second ends of the fourth conductive strips 22; all the second conductive strips 12 and all the fourth conductive strips 22 are arranged alternately along the first direction X.

In this embodiment, both the source electrode 1 and the drain electrode 2 are comb-shaped, and the comb teeth (second conductive strips 12 and fourth conductive strips 22) are arranged alternately, so that the opening area 6 in the thin film transistor can be effectively improved. The quantity can improve the heat dissipation effect.

It should be noted that in the accompanying drawings, the source electrode 1 includes two second conductive strips 12, and the drain electrode 2 includes a fourth conductive strip 22, which is only used as an example, and it does not affect the technology of the present utility model. Programs create limitations. Certainly, the source electrode 1 and the drain electrode 2 in the present invention may also have other shapes, which are not limited in the present invention.

The preparation process of the thin film transistors provided in the above-mentioned embodiment 1 and embodiment 2 will be described in detail below.

First, a gate and a gate insulating layer are sequentially formed above the base substrate; then, a thin film of active layer material (metal oxide semiconductor material, such as indium gallium zinc oxide, chemical formula IGZO) is formed above the gate insulating layer; then, Form an etch barrier layer material film above the active layer material film; then, pattern the etch barrier layer material film through a patterning process to obtain an etch barrier layer pattern, and the etch barrier layer pattern is covered by the subsequent sequence to be Form active sub-patterns, conductive connection patterns and raised pattern areas; next, form a source-drain metal layer material film above the etch barrier layer; finally, pattern the source-drain metal layer material film and active The layer material film is patterned, the source and drain metal layer material film is patterned to form the source electrode and the drain electrode, and the active layer material film is patterned to form an active sub-pattern, a conductive connection pattern and a raised pattern.

Embodiment 3 of the present utility model provides an array substrate. The array substrate includes: a thin film transistor. The thin film transistor adopts the thin film transistor in Embodiment 1 or Embodiment 2 above. For details, please refer to Embodiment 1 and Embodiment 2 above. The description in , will not be repeated here.

Embodiment 4 of the present invention provides a display device, the display device includes: an array substrate, the array substrate adopts the thin film transistor in the above-mentioned embodiment 3, the specific content can refer to the description in the above-mentioned embodiment 3, and will not be repeated here repeat.

It should be noted that the display device in this embodiment can be any product with a display function such as a liquid crystal panel, an electronic paper, an OLED panel, a mobile phone, a tablet computer, a television set, a monitor, a notebook computer, a digital photo frame, a navigator, etc. part.

It can be understood that, the above embodiments are only exemplary embodiments adopted to illustrate the principles of the present invention, but the present invention is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and essence of the present utility model, and these variations and improvements are also regarded as the protection scope of the present utility model.

Claims (10)

1. A kind of thin film transistor, comprises source and drain, is characterized in that, also comprises active layer, and described active layer comprises several intervals and independently arranged active sub-patterns, and described source covers each described A partial area of the active sub-pattern, the drain covers a partial area of the active sub-pattern, and the area of the active sub-pattern not covered by the source and the drain is a conductive area; Any adjacent conductive region and the source and the drain form an open region, and at least one of the open regions is provided with a conductive connection connected to the corresponding two adjacent conductive regions. pattern, the conductive connection pattern is at most connected to one of the source and the drain. 2 . The thin film transistor according to claim 1 , wherein a convex pattern is formed on a side of the outermost active sub-pattern facing away from the other active sub-patterns. 3. The thin film transistor according to claim 1, wherein the active sub-patterns are strip-shaped and extend along the first direction, all the active sub-patterns are arranged in parallel along the second direction, and the first The direction is perpendicular to the second direction. 4. The thin film transistor according to claim 3, wherein the source electrode comprises a first conductive strip and several second conductive strips arranged in parallel along the first direction, the second conductive strips are arranged along the The second direction extends, the second conductive strips cover a partial area of the active sub-pattern, and the first conductive strips connect the first ends of the second conductive strips; The drain electrode includes a third conductive strip and several fourth conductive strips arranged in parallel along the first direction, the fourth conductive strip extends along the second direction, and the fourth conductive strip covers the In a partial area of the active sub-pattern, the third conductive strips are connected to the second ends of the fourth conductive strips; All the second conductive strips and all the fourth conductive strips are arranged alternately along the first direction. 5. The thin film transistor according to claim 1, wherein the conductive connection pattern is not connected to the source and the drain. 6. The thin film transistor according to claim 5, wherein the distance between the conductive connection pattern and the source and the drain is equal. 7 . The thin film transistor according to claim 1 , wherein the ratio of the area of the conductive connection pattern to the area of the corresponding opening area is 2/5˜3/5. 8 . The thin film transistor according to claim 1 , wherein the width of the active sub-patterns ranges from 5 um to 15 um. 9. An array substrate, characterized by comprising: the thin film transistor according to any one of claims 1-8. 10. A display device, comprising: the array substrate according to claim 9.