CN207765172U - A kind of measurement jig of eMMC chips - Google Patents
A kind of measurement jig of eMMC chips Download PDFInfo
- Publication number
- CN207765172U CN207765172U CN201820443866.3U CN201820443866U CN207765172U CN 207765172 U CN207765172 U CN 207765172U CN 201820443866 U CN201820443866 U CN 201820443866U CN 207765172 U CN207765172 U CN 207765172U
- Authority
- CN
- China
- Prior art keywords
- emmc
- test
- measurement jig
- emmc chips
- positioning
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Measuring Leads Or Probes (AREA)
Abstract
The utility model discloses a kind of measurement jigs of eMMC chips, for being mounted on eMMC test development boards, the measurement jig includes the test bench for connecting the eMMC test development boards and the IC limitting casings on test bench, the IC limitting casings are for placing the eMMC chips, the test bench is equipped with double ended probes, one end of the double ended probes is used to dock the IC package pad of the eMMC test development boards, and the other end of the double ended probes is used to dock the tin ball of the eMMC chips.The measurement jig of the utility model eMMC chips is small to the decaying of signal, good in anti-interference performance, and has the advantages that easy to operate.
Description
Technical field
The utility model is related to IC test equipments technical field more particularly to a kind of measurement jigs of eMMC chips.
Background technology
Currently, the test of the eMMC chips to SD card, typically uses dedicated measurement jig, after the good software of burning
EMMC chips are put into the dedicated measurement jig, and one end of double ended probes is docked with the tin ball of eMMC chips on measurement jig,
The other end is docked with the IC package pad of SD card pcb board, the circuit trace contact corresponding with SD card plug of the IC package pad
It is connected.Measurement jig is inserted into the SD card card slot of TV motherboard, eMMC cores are judged by TV motherboard energization starting state
Whether piece and software are qualified.When TV motherboard can normally start, and dispaly state and software are preset consistent, then eMMC chips
And software is considered qualification, is otherwise considered as unqualified.
But during being tested the eMMC chips of SD card using above-mentioned measurement jig, due to SD card pcb board circuit
Cabling is longer, and signal decaying is big, and is easy to be disturbed.When the signal transmission rate of eMMC chips reaches 200MHz or more, make
It can not make eMMC chip normal operations with above-mentioned measurement jig.
Utility model content
The main purpose of the utility model is to provide a kind of measurement jigs of eMMC chips, it is intended to solve existing test and control
The existing signal decaying of tool is big and can not make eMMC chip normal operations when the transmission signal rate of eMMC chips is higher
Problem.
To achieve the above object, the measurement jig of eMMC chips provided by the utility model is tested for being mounted on eMMC
On development board, the measurement jig includes the test bench for connecting the eMMC test development boards and the IC on test bench
Limitting casing, the IC limitting casings are equipped with double ended probes for placing the eMMC chips, the test bench, the double ended probes
One end is used to dock the IC package pad of the eMMC test development boards, and the other end of the double ended probes is described for docking
The tin ball of eMMC chips.
Preferably, the test bench includes testing jig, and the testing jig is equipped with opening, and the measurement jig further includes turning over
Lid, described renovate are articulated with the side of the testing jig by an articulated shaft and are used to open or close the opening, the IC
Limitting casing is placed in the opening, and described renovate is equipped with top cap, the top cap be used for it is described renovate close the opening when
Support the eMMC chips.
Preferably, the free end renovated is equipped with grab, and the side far from the articulated shaft is equipped on the testing jig
Card column for coordinating with the grab.
Preferably, the test bench further includes the positioning between the testing jig and the eMMC test development boards
Plate, the positioning plate is for connecting the testing jig and the eMMC test development boards.
Preferably, the test bench further includes mounting plate, and the double ended probes is set on the mounting plate, the positioning plate
On offer mounting groove, the mounting plate is placed in the mounting groove and the corresponding IC package pad.
Preferably, the mounting plate is equipped with the first positioning column, is offered and first positioning column on the positioning plate
The first positioning hole of cooperation;The IC limitting casings are equipped with the second positioning column, offer on the positioning plate and determine with described second
The second location hole of position column cooperation.
Preferably, the positioning plate is equipped with third positioning column and the 4th positioning column, for the corresponding and eMMC respectively
The third location hole opened up in test development board and the cooperation of the 4th location hole.
Preferably, the diameter of the third positioning column and the diameter of the 4th positioning column are inconsistent.
Preferably, the IC limitting casings are matched with the eMMC chips, and the IC limitting casings are removably mounted to the survey
It tries on seat.
Preferably, the IC limitting casings are equipped with the mark for distinguishing the eMMC chips placement direction.
In the technical solution of the utility model, the measurement jig of eMMC chips makes double ended probes directly be opened with eMMC tests
The IC package pad docking for sending out plate, reduces circuit trace, reduces decaying and interference of the circuit to signal, and in eMMC chips
Signal transmission rate it is higher when, remain to make eMMC chip normal operations.The measurement jig of the utility model eMMC chips is to letter
Number decaying it is small, good in anti-interference performance, and having the advantages that easy to operate.
Description of the drawings
In order to illustrate the embodiment of the utility model or the technical proposal in the existing technology more clearly, below will be to embodiment
Or attached drawing needed to be used in the description of the prior art is briefly described, it should be apparent that, the accompanying drawings in the following description is only
It is some embodiments of the utility model, for those of ordinary skill in the art, in the premise not made the creative labor
Under, the structure that can also be shown according to these attached drawings obtains other attached drawings.
Fig. 1 is that the measurement jig of the utility model eMMC chips is illustrated with the assembly of eMMC chips and eMMC test development boards
Figure;
Fig. 2 is decomposition diagrams of the Fig. 1 at a visual angle;
Fig. 3 is the decomposition diagram at another visual angle after omitting eMMC test development boards in Fig. 1.
Drawing reference numeral explanation:
| Label | Title | Label | Title |
| 100 | Measurement jig | 1 | Test bench |
| 11 | Testing jig | 110 | Opening |
| 111 | Card column | 12 | Positioning plate |
| 120 | Mounting groove | 121 | First positioning hole |
| 122 | Second location hole | 123 | Third positioning column |
| 124 | 4th positioning column | 13 | Mounting plate |
| 131 | First positioning column | 2 | IC limitting casings |
| 21 | Second positioning column | 3 | It renovates |
| 31 | Top cap | 32 | Grab |
| 200 | EMMC test development boards | 201 | IC package pad |
| 202 | Silk-screen frame | 203 | IC package pad area |
| 204 | Test bench encapsulation region | 205 | Third location hole |
| 206 | 4th location hole | 300 | EMMC chips |
The utility model aim is realized, the embodiments will be further described with reference to the accompanying drawings for functional characteristics and advantage.
Specific implementation mode
Below in conjunction with the attached drawing in the present embodiment, the technical solution in the present embodiment is clearly and completely described,
Obviously, described embodiment is only a part of the embodiment of the utility model, instead of all the embodiments.Based on this reality
With the embodiment in novel, those of ordinary skill in the art are obtained every other without creative efforts
Embodiment shall fall within the protection scope of the present invention.
It is to be appreciated that the directional instruction (such as up, down, left, right, before and after ...) of institute is only used for solving in the present embodiment
Relative position relation, motion conditions etc. between each component under a certain particular pose (as shown in the picture) are released, if this is specific
When posture changes, then directionality instruction also correspondingly changes correspondingly.
In addition, the description for being such as related to " first ", " second " in the present invention is used for description purposes only, and cannot manage
Solution is instruction or implies its relative importance or implicitly indicates the quantity of indicated technical characteristic.Define as a result, " the
One ", the feature of " second " can explicitly or implicitly include at least one of the features.It is " more in the description of the present invention,
It is a " it is meant that at least two, such as two, three etc., unless otherwise specifically defined.
In the present invention unless specifically defined or limited otherwise, term " connection ", " fixation " etc. should do broad sense reason
Solution, for example, " fixation " may be a fixed connection, may be a detachable connection, or integral;It can be mechanical connection, also may be used
To be electrical connection;It can be directly connected, can also can be indirectly connected through an intermediary the connection inside two elements
Or the interaction relationship of two elements, unless otherwise restricted clearly.It for the ordinary skill in the art, can be with
The concrete meaning of above-mentioned term in the present invention is understood as the case may be.
In addition, the technical solution between each embodiment of the utility model can be combined with each other, but must be with ability
Domain those of ordinary skill can be implemented as basis, will be understood that when the combination of technical solution appearance is conflicting or cannot achieve
The combination of this technical solution is not present, also not within the protection domain of the requires of the utility model.
It should be appreciated that specific embodiment described herein is only used to explain the utility model, it is not used to limit this
Utility model.
As shown in Figure 1 to Figure 3, the utility model provides a kind of measurement jig 100 of eMMC chips 300, the measurement jig
100 for being mounted on eMMC test development boards 200, and the eMMC chips 300 of the present embodiment meaning refer to the eMMC of TV motherboard
Chip 300, eMMC test development boards 200 refer to TV motherboard.The measurement jig 100 includes test bench 1 and IC limitting casings 2,
Test bench 1 connects eMMC test development boards 200, and IC limitting casings 2 are mounted on test bench 1, and IC limitting casings 2 are for placing eMMC cores
Piece 300, test bench 1 are equipped with double ended probes (not shown), and eMMC test development boards 200 are equipped with IC package pad 201, double ended probes
One end for docking IC package pad 201, the other end of double ended probes is used to dock the tin ball of eMMC chips 300.
Specifically, when being tested eMMC chips 300 using the measurement jig 100, measurement jig 100 is mounted on
In eMMC test development boards 200, one end of double ended probes on test bench 1 is made to dock IC package pad 201, even if double ended probes
One end is directly contacted with the IC package pad 201 of TV motherboard.After the good software of 300 burning of eMMC chips, eMMC chips 300 are put
Set makes the other end of double ended probes be docked with the tin ball of eMMC chips 300 in IC limitting casings 2.EMMC will be made to test after installing
Development board 200, which is powered, to be started, and checks the operating status of eMMC chips 300.
The measurement jig 100 of the present embodiment eMMC chips 300 makes IC of the double ended probes directly with eMMC test development boards 200
Encapsulation welding tray 201 docks, and reduces circuit trace, reduces decaying and interference of the circuit to signal, and in eMMC chips 300
When signal transmission rate reaches 400MHz or more, remain to make 300 normal operation of eMMC chips.The present embodiment eMMC chips 300
Measurement jig 100 is small to the decaying of signal, good in anti-interference performance, and has the advantages that easy to operate.
As depicted in figs. 1 and 2, the test bench 1 of the present embodiment includes testing jig 11, and testing jig 11 is equipped with opening 110, test
Jig 100 further includes renovating 3, renovates 3 and is articulated with the side of testing jig 11 by an articulated shaft and is used to open or closes opening
110, IC limitting casings 2 are placed in opening 110, renovate 3 and are equipped with top cap 31, top cap 31 is used to support when renovating 3 closings opening 110
Push up eMMC chips 300.After eMMC chips 300 are placed on IC limitting casings 2,3 will be renovated and closed, even if renovating 3 closing testing jigs
Opening 110 on 11, at this point, the top cap 31 renovated on 3 supports eMMC chips 300, so that double ended probes and eMMC chips
300 tin ball is in close contact, and is conducive to test, meanwhile, renovating can be by eMMC chip 300 after the opening 110 on 3 closing testing jigs 11
It is closed, reduces the interference of outer bound pair signal.When needing to take out eMMC chips 300, rotary flip 3 makes to renovate the survey of 3 openings
Try the opening 110 on frame 11, you can eMMC chips 300 are taken out, it is simple and quick.
Further, the free end for renovating 3 is equipped with grab 32, on testing jig 11 side far from articulated shaft be equipped with for
The card column 111 that grab 32 coordinates.After renovating opening 110 on 3 closing testing jigs 11, grab 32 coordinates with card column 111, will turn over
Lid 3 latches on testing jig 11, and top cap 31 is made to keep supporting the state of eMMC chips 300, reliable and stable.In order to further subtract
The interference of few outer bound pair signal, the testing jig 11 of the present embodiment are made with renovating 3 high strength alloy material can be used.
As shown in Figure 1 to Figure 3, in the present embodiment, test bench 1 further includes positioning plate 12, and positioning plate 12 is located at testing jig 11
Between eMMC test development boards 200, testing jig 11 and positioning plate 12 are screwed in eMMC test development boards 200
On, the position that eMMC test development boards 200 correspond to positioning plate 12 is equipped with 1 encapsulation region of test bench.Test bench 1 can be fixed when assembly
In 1 encapsulation region of test bench of eMMC test development boards 200, it is conducive to test.
In the present embodiment, test bench 1 further includes mounting plate 13, and double ended probes is set on mounting plate 13, IC limitting casings 2 and
Mounting plate 13 can be fixed with 12 screw of positioning plate.Mounting groove 120 is offered on positioning plate 12, mounting plate 13 is placed in mounting groove
120 and corresponding IC package pad 201, it is docked with IC package pad 201 convenient for double ended probes.
Further, mounting plate 13 can be fixed with 12 screw of positioning plate, and 13 two opposite positions of mounting plate are respectively provided with
One positioning column 131 offers the first positioning hole 121 coordinated with the first positioning column 131 on positioning plate 12, convenient for by mounting plate 13
Location and installation is on positioning plate 12;IC limitting casings 2 can be fixed with 12 screw of positioning plate, two opposite positions on IC limitting casings 2
It is respectively provided with the second positioning column 21, the second location hole 122 coordinated with the second positioning column 21 is offered on positioning plate 12, is convenient for IC
2 location and installation of limitting casing is on positioning plate 12, to conducive to double ended probes and the eMMC chips 300 being positioned in IC limitting casings 2
Dock With Precision Position.
Further, positioning plate 12 is equipped with third positioning column 123 and the 4th positioning column 124, eMMC test development boards
200 offer third location hole 205 and the 4th location hole 206, wherein third location hole 205 is matched with third positioning column 123
It closes, the 4th location hole 206 and the 4th positioning column 124 coordinate, and are convenient for 12 location and installation of positioning plate in eMMC test development boards 200
On, to conducive to double ended probes and 201 Dock With Precision Position of IC package pad in eMMC test development boards 200.In order to more accurately
Realize positioning, the diameter of the diameter and the 4th positioning column 124 that can make third positioning column 123 is inconsistent, for example, third can be made to position
The diameter of a diameter of 1.5mm of column 123, third location hole 205 mutually should be 1.55mm, and the 4th positioning column 124 is a diameter of
The diameter of 2.0mm, the 4th location hole 206 mutually should be 2.05mm, avoid the occurrence of setup error.
As shown in Fig. 2, in the present embodiment, eMMC test development boards 200 are equipped with silk-screen frame 202, and silk-screen frame 202 surrounds IC
Encapsulation welding tray area 203 and test bench encapsulation region 204, IC package pad 201 are located in IC package pad area 203.Silk-screen frame 202
Correct installation conducive to test bench 1 is set.
In the present embodiment, IC limitting casings 2 are matched with eMMC chips 300, and IC limitting casings 2 are removably mounted on test bench 1.
There are eMMC chips 300 different sizes, the IC limitting casings 2 of 300 Corresponding matching different size of various sizes of eMMC chips to need
When replacing various sizes of eMMC chips 300, former IC limitting casings 2 can be removed from test bench 1 and by the IC with appropriate size
Limitting casing 2 is mounted on test bench 1, not only flexible and convenient operation, but also realizes the measurement jig 100 to different sizes
The compatibility of eMMC chips 300.
In the present embodiment, IC limitting casings 2 are equipped with the mark for distinguishing 300 placement direction of eMMC chips.It specifically, can be
The small triangle identifier of silk-screen on IC limitting casings 2, when testing eMMC chips 300, by 1 foot index point face of eMMC chips 300
The mark direction of the small triangle identifier on IC limitting casings 2 is placed, so as to the placement side of accurate discrimination eMMC chips 300
To.
In the present embodiment, IC limitting casings 2, positioning plate 12 and mounting plate 13 can be used insulation engineering and be made, and has and is not easy
The advantages of deformation and good insulating.The double ended probes of the present embodiment can be used the flexible double end of microsprings in the prior art and visit
Needle, have the advantages that performance stablize and it is with long service life.
It these are only the preferred embodiment of the utility model, it does not limit the scope of the patent of the present invention, every
Equivalent structure or equivalent flow shift made based on the specification and figures of the utility model, is applied directly or indirectly in
Other related technical areas are equally included in the patent within the scope of the utility model.
Claims (10)
1. a kind of measurement jig of eMMC chips, which is characterized in that for being mounted on eMMC test development boards, the test is controlled
Tool includes the test bench for connecting the eMMC test development boards and the IC limitting casings on test bench, the IC limitting casings
For placing the eMMC chips, the test bench is equipped with double ended probes, and one end of the double ended probes is described for docking
The IC package pad of eMMC test development boards, the other end of the double ended probes are used to dock the tin ball of the eMMC chips.
2. the measurement jig of eMMC chips according to claim 1, which is characterized in that the test bench includes testing jig,
The testing jig is equipped with opening, and the measurement jig further includes renovating, and described renovate is articulated with the test by an articulated shaft
The side of frame is simultaneously used to open or closes the opening, and the IC limitting casings are placed in the opening, described to renovate equipped with top
Cap, the top cap be used for it is described renovate close the opening when support the eMMC chips.
3. the measurement jig of eMMC chips according to claim 2, which is characterized in that the free end renovated is equipped with card
Hook, the side far from the articulated shaft is equipped with the card column for coordinating with the grab on the testing jig.
4. the measurement jig of eMMC chips according to claim 2, which is characterized in that the test bench further includes being located at institute
State the positioning plate between testing jig and the eMMC test development boards, the positioning plate is for connecting the testing jig and described
EMMC test development boards.
5. the measurement jig of eMMC chips according to claim 4, which is characterized in that the test bench further includes installation
Plate, the double ended probes are set on the mounting plate, and mounting groove is offered on the positioning plate, and the mounting plate is placed in described
Mounting groove and the corresponding IC package pad.
6. the measurement jig of eMMC chips according to claim 5, which is characterized in that it is fixed that the mounting plate is equipped with first
Position column, offers the first positioning hole coordinated with first positioning column on the positioning plate;The IC limitting casings are equipped with the
Two positioning columns offer the second location hole coordinated with second positioning column on the positioning plate.
7. the measurement jig of eMMC chips according to claim 4, which is characterized in that the positioning plate is fixed equipped with third
Position column and the 4th positioning column are positioned for corresponding respectively with the third location hole opened up in the eMMC test development boards and the 4th
Hole coordinates.
8. the measurement jig of eMMC chips according to claim 7, which is characterized in that the diameter of the third positioning column with
The diameter of 4th positioning column is inconsistent.
9. the measurement jig of the eMMC chips according to any one of claim 1-8, which is characterized in that the IC limitting casings
It is matched with the eMMC chips, the IC limitting casings are removably mounted on the test bench.
10. the measurement jig of the eMMC chips according to any one of claim 1-8, which is characterized in that the IC limits
Frame is equipped with the mark for distinguishing the eMMC chips placement direction.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201820443866.3U CN207765172U (en) | 2018-03-29 | 2018-03-29 | A kind of measurement jig of eMMC chips |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201820443866.3U CN207765172U (en) | 2018-03-29 | 2018-03-29 | A kind of measurement jig of eMMC chips |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN207765172U true CN207765172U (en) | 2018-08-24 |
Family
ID=63180275
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201820443866.3U Expired - Fee Related CN207765172U (en) | 2018-03-29 | 2018-03-29 | A kind of measurement jig of eMMC chips |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN207765172U (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109470963A (en) * | 2018-12-06 | 2019-03-15 | 深圳市江波龙电子股份有限公司 | A kind of test bench and its service life supervision method |
| CN110794283A (en) * | 2019-09-24 | 2020-02-14 | 南方电网数字电网研究院有限公司 | A test system for electronic chips |
| CN113012750A (en) * | 2019-12-18 | 2021-06-22 | 中移物联网有限公司 | Testing device and method for memory chip |
| CN114046975A (en) * | 2021-11-10 | 2022-02-15 | 日月光半导体制造股份有限公司 | Test fixture and test method suitable for IC bearing disc |
| TWI871615B (en) * | 2023-04-20 | 2025-02-01 | 南亞科技股份有限公司 | Measuring appratus and failure detection method of semiconductor chip |
-
2018
- 2018-03-29 CN CN201820443866.3U patent/CN207765172U/en not_active Expired - Fee Related
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109470963A (en) * | 2018-12-06 | 2019-03-15 | 深圳市江波龙电子股份有限公司 | A kind of test bench and its service life supervision method |
| CN109470963B (en) * | 2018-12-06 | 2021-01-12 | 深圳市江波龙电子股份有限公司 | Test socket and service life monitoring method thereof |
| CN110794283A (en) * | 2019-09-24 | 2020-02-14 | 南方电网数字电网研究院有限公司 | A test system for electronic chips |
| CN113012750A (en) * | 2019-12-18 | 2021-06-22 | 中移物联网有限公司 | Testing device and method for memory chip |
| CN113012750B (en) * | 2019-12-18 | 2023-08-15 | 中移物联网有限公司 | Testing device and method for memory chip |
| CN114046975A (en) * | 2021-11-10 | 2022-02-15 | 日月光半导体制造股份有限公司 | Test fixture and test method suitable for IC bearing disc |
| TWI871615B (en) * | 2023-04-20 | 2025-02-01 | 南亞科技股份有限公司 | Measuring appratus and failure detection method of semiconductor chip |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN207765172U (en) | A kind of measurement jig of eMMC chips | |
| JP6515003B2 (en) | Interface device, interface unit, probe device and connection method | |
| CN207216203U (en) | Lighting laminating mechanism and lighting jig | |
| CN202167730U (en) | USB switching device used for test | |
| CN206540936U (en) | Fixtures for functional testing of mobile phone motherboards | |
| CN109633934A (en) | Lighting laminating mechanism and lighting jig | |
| EP3438679A1 (en) | Substrate inspection apparatus | |
| US6281695B1 (en) | Integrated circuit package pin indicator | |
| CN210665346U (en) | Drop test fixture of cell-phone camera module | |
| CN211856799U (en) | Integrated circuit IC carrier board post-balling test instrument | |
| CN111308237A (en) | Survey value needle, survey value needle structure and automatic value measuring machine | |
| CN110133113A (en) | Acoustic emission probe positioning system, the test block used in the system and the application of the system | |
| CN215067128U (en) | Online performance testing device for liquid crystal display drive board | |
| KR101892646B1 (en) | Probe Card Low Leakage Current Measuring Device | |
| CN205067627U (en) | Probe testing apparatus | |
| CN110534973B (en) | Guiding device | |
| WO2017156779A1 (en) | Test probe of detection apparatus | |
| TWI325500B (en) | Integrated circuit testing apparatus | |
| US20230045808A1 (en) | Systems, devices, and methods for testing integrated circuits in their native environments | |
| CN207798989U (en) | A kind of open-short circuit device of flexible circuit board connector | |
| CN215728759U (en) | Mounting device for probe card needle point coplanarity measurement and needle adjustment | |
| CN205450162U (en) | Special tool with detect function | |
| CN217639379U (en) | Online TV mainboard automatic test equipment | |
| CN211718401U (en) | Quick identification device of test conversion board ID | |
| CN222689801U (en) | Packaging-oriented universal chip test carrier plate |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20180824 |