CN209515676U - Semiconductor devices and chip - Google Patents

Abstract

The utility model relates to a kind of semiconductor devices and chip, which includes: terminal trenches grid structure and several cellular trench gate structures in substrate；The terminal trenches grid structure has along the spaced several annular side surfaces of direction initialization；Several cellular trench gate structures are located at the inside of several annular side surfaces, and the annular side surface of each terminal trenches grid structure is arranged concentrically with the side surface of the cellular trench gate structure of corresponding inside with constant space.The technical solution of the utility model, which solves the problems, such as that the trench gate structure spacing of existing splitting bar trench MOSFET cannot be consistent, causes electrical parameter consistency poor.

Description

Semiconductor Devices and Chips

technical field

The utility model relates to the technical field of semiconductors, in particular to a semiconductor device and a chip.

Background technique

Compared with planar MOSFET (Metal Oxide Semiconductor Field Effect Transistor), trench MOSFET has many advantages such as large drive current, high power density, and small on-resistance due to its vertical conduction characteristics, so it has been widely used. Among them, the split-gate trench MOSFET is a commonly used trench MOSFET because it can reduce internal resistance.

As shown in FIG. 1 , an existing split-gate trench MOSFET includes a substrate 1 and several trench gate structures 2 in the substrate 1 (only one is shown in the figure). Wherein, the trench gate structure 2 includes a trench 20 in the substrate 1 , a dielectric layer 21 covering the inner wall of the trench 20 , a first gate 22 and a second gate 23 . The first gate 22 is located below the second gate 23 along the depth direction of the trench 20 , and the two are separated by a dielectric layer 21 .

The plurality of trench gate structures include cellular trench gate structures and terminal trench gate structures, wherein the plurality of terminal trench gate structures are located outside the plurality of cellular trench gate structures to serve as terminal protection structures. There are two common ways of arrangement between the cell trench gate structure and the terminal trench gate structure:

As shown in Figure 2, several strip-shaped cellular trench gate structures 2a are arranged at intervals along the direction X1, the interval between two adjacent cellular trench gate structures 2a is D1, and several strip-shaped terminal trench gate structures 2b are arranged along the direction X1. The direction Y1 is distributed on both sides of several cellular trench gate structures 2a, and the terminal trench gate structure 2b is perpendicular to the cellular trench gate structure 2a, and the distance between the terminal trench gate structure 2b and the cellular trench gate structure 2a The interval is D2, and D2 is equal to D1.

As shown in FIG. 3 , several strip-shaped cellular trench gate structures 2c are arranged at intervals along the direction X2, and several arc-shaped terminal trench gate structures 2d are arranged outside the plurality of cellular trench gate structures 2c.

However, the aforementioned split-gate trench MOSFETs all have the problem that the trench gate structure spacing cannot be kept consistent, resulting in poor consistency of electrical parameters. For example, continuing to refer to FIG. 2, although the interval D2 between the terminal trench gate structure 2b and the cell trench gate structure 2a is equal to D1, it only ensures that the substrates in regions A and B in FIG. The electrical stress coupling of the two grooves is the same, but the substrate in the C region is subjected to the electrical stress coupling from the terminal groove and the cell grooves in the oblique direction on both sides, so that the electrical stress of the C region is the same as that of the A and B regions. Stress is different. Continuing to refer to FIG. 3 , the distance between the terminal trench gate structure 2d and the cellular trench gate structure 2c shown in the area A is not equal to the distance between the terminal trench gate structure 2d and the cellular trench gate structure 2c shown in the area B. The spacing between them, and it cannot be guaranteed that the electrical stress coupling of the substrate at the bottom of the trench remains consistent

In addition, the above-mentioned split-gate trench MOSFET still has the problem of uniform orientation of stress on the chip, because all the trench gate structures of the cells are arranged in the same direction, which easily causes excessive stress to the chip.

Utility model content

One of the technical problems to be solved by the utility model is the poor consistency of the pitch of the trench gate structure of the existing split gate trench MOSFET.

The second technical problem to be solved by the utility model is that the deep groove of the existing split-gate trench MOSFET tends to cause stress concentration on the chip where it is located.

In order to solve the above problems, the utility model provides a semiconductor device, which includes: a terminal trench gate structure and several cell trench gate structures located in the substrate; A plurality of annular side surfaces arranged; several of the cellular trench gate structures are respectively located on the inner sides of the plurality of annular side surfaces, and each annular side surface of the terminal trench gate structure is aligned with the corresponding inner cellular trench gate The side surfaces of the structure are arranged concentrically at a constant pitch.

Optionally, the lateral cross-sections of the annular side surface of the terminal trench gate structure and the side surface of the cell trench gate structure are rounded rectangles or right-angled rectangles.

Optionally, the terminal trench gate structure includes: several first segments; several second segments, arranged alternately and alternately with the plurality of cellular trench gate structures along the set direction; in the set direction The ends of any two adjacent second sections are connected by the first section; when the transverse section is a rounded rectangle, the first section is an arc section, and the second section is a strip section ; when the transverse section is a right-angled rectangle, the first section and the second section are both bar-shaped sections.

Optionally, the thickness of the first segment is equal to the thickness of the second segment, and the thickness is a dimension in a direction parallel to the substrate.

Optionally, the thickness of the cell trench gate structure is equal to the thickness of the first segment.

Optionally, the semiconductor device includes a split gate trench MOSFET having the terminal trench gate structure and the cell trench gate structure; the terminal trench gate structure and the cell trench gate structure both include: A trench in the substrate; a dielectric layer covering the inner wall of the trench; a first gate located in the trench, and the first gate is isolated from the substrate by the dielectric layer Come; the cell trench gate structure further includes a second gate located in the trench, and the first gate and the second gate are separated by the dielectric layer.

Optionally, the first gate and the second gate are arranged at intervals along a direction parallel to the substrate, and the second gate is located outside the first gate.

Optionally, the first gate and the second gate are arranged at intervals along the depth direction of the trench.

Optionally, it also includes: an insulating layer located on the substrate, the terminal trench gate structure and the cell trench gate structure; a first conductive plug passing through the insulating layer, the first conductive plug A plug forms an ohmic contact electrical connection with the first grid; a metal layer located on the insulating layer and the first conductive plug, the metal layer is electrically connected with the first conductive plug.

Optionally, a first-type doped region and a second-type doped region are formed in the substrate, and the second-type doped region is located on the surface of the first-type doped region; the semiconductor device further It includes: a second conductive plug passing through the insulating layer and the second type doped region, and the second conductive plug forms an ohmic contact with the first type doped region and the second type doped region. connect.

Optionally, the semiconductor device includes a trench Schottky diode having the terminal trench gate structure and the cell trench gate structure; the terminal trench gate structure and the cell trench gate structure both include: A trench located in the substrate; a dielectric layer covering the inner wall of the trench; a gate located in the trench and covering the dielectric layer.

In addition, the present invention also provides a chip, which includes any one of the above-mentioned semiconductor devices.

Optionally, the cellular trench gate structures of at least one of the semiconductor devices are arranged at intervals along the first direction, and at least the cellular trench gate structures of the other semiconductor device are arranged at intervals along the second direction arranged, the second direction is perpendicular to the first direction.

In the semiconductor device of the present invention, the ring-shaped side surface of the terminal trench gate structure and the side surface of the corresponding inner cell trench gate structure are concentrically arranged at a constant distance, so that the ring-shaped side surface of each terminal trench gate structure and the corresponding The distance between the side surfaces of the corresponding inner cell trench gate structure in the 360-degree direction is always kept at a constant value, so that the distance between the trench gate structures remains consistent and the electrical parameters of the product have better consistency.

By arranging the cell trench gate structures of some semiconductor devices at intervals along the first direction in the chip, and arranging the cell trench gate structures of other semiconductor devices at intervals along the second direction perpendicular to the first direction, the on-chip The cellular trench gate structure is alternately distributed along two perpendicular directions, and the stress brought by the deep cellular trench structure does not show a uniform orientation.

Description of drawings

1 is a schematic cross-sectional view of an existing split-gate trench MOSFET;

Fig. 2 is a planar layout diagram between the cell trench gate structure and the terminal trench gate structure in the split gate trench MOSFET shown in Fig. 1;

Fig. 3 is another planar layout diagram between the cell trench gate structure and the terminal trench gate structure in the split gate trench MOSFET shown in Fig. 1;

Fig. 4 is a plane arrangement diagram between the cell trench gate structure and the terminal trench gate structure of the semiconductor device in an embodiment of the present invention;

Fig. 5 is a sectional view along the A-A direction of Fig. 4;

Fig. 6 is the sectional view along B-B direction of Fig. 4;

7 is a schematic cross-sectional view of a semiconductor device in the first embodiment of the present invention;

8 to 13 are schematic cross-sectional views of the semiconductor device shown in FIG. 7 at various manufacturing stages;

14 is a schematic cross-sectional view of a semiconductor device in a second embodiment of the present invention;

15 is a schematic cross-sectional view of a semiconductor device in a third embodiment of the present invention;

Fig. 16 is a schematic plan view of a chip in an embodiment of the present invention.

Detailed ways

Fig. 4 is a plane arrangement diagram between the cell trench gate structure and the terminal trench gate structure of the semiconductor device in an embodiment of the present invention, Fig. 5 is a cross-sectional view along the direction A-A of Fig. 4, Fig. 6 is Fig. 4 A cross-sectional view along the B-B direction, as shown in FIG. 4 to FIG. 6 , the semiconductor device of this embodiment includes a terminal trench gate structure 20 located in the substrate 10 and several (three are taken as an example in the figure) cellular trenches gate structure 30 .

The terminal trench gate structure 20 has several annular side surfaces F1 arranged at intervals along the set direction X. In the present utility model, the so-called side surface refers to the surface extending along the thickness direction Z of the substrate 10, and the so-called annular refers to It is closed in the 360-degree direction, and the ring may be a circle or a ring other than a circle. Several cellular trench gate structures 30 are respectively located inside the ring-shaped side surface F1 of several terminal trench gate structures 20, so that the terminal trench gate structures 20 are distributed on the periphery of each cellular trench gate structure 30 as a terminal protective structure.

The annular side surface F1 of each terminal trench gate structure 20 is arranged concentrically with the side surface F2 of the corresponding inner cellular trench gate structure 30 at a constant interval, that is: the annular side surfaces F1 of all terminal trench gate structures 20 are aligned with all The cellular trench gate structures 30 are in one-to-one correspondence, the annular side surface F1 of each terminal trench gate structure 20 is located at the periphery of a corresponding cellular trench gate structure 30, and the annular side surface F1 of each terminal trench gate structure 20 The surface F1 has the same shape as the side surface F2 of the corresponding cellular trench gate structure 30, and each annular side surface F1 and the corresponding inner side surface F2 are concentrically arranged at a constant distance S, so that each annular side surface F1 The distance between the side surface F2 and the corresponding inner side surface F2 in the 360-degree direction is always kept as S, so that the distance between the trench gate structure in the semiconductor device remains consistent, and the electrical parameters of the product have better consistency.

In some embodiments, the spacing S between the annular side surface F1 and the corresponding inner side surface F2 is 0.5 μm to 2.5 μm, and the depth of the terminal trench gate structure 20 and the cell trench gate structure 30 is 1 μm to 15 μm. .

In this embodiment, the lateral cross-sectional shapes of the annular side surface F1 of each terminal trench gate structure 20 and the side surface F2 of the cellular trench gate structure 30 are circular and rectangular, and the so-called transverse cross-sectional shape refers to The cross-sectional shape in the direction parallel to the substrate, the so-called rounded rectangle means that two of the sides of the rectangle are straight lines arranged in parallel and at intervals, and the other two sides are semicircular or nearly tangent to the two sides. Semicircle.

Of course, in other embodiments, the ring-shaped side surface F1 of the terminal trench gate structure 20 and the side surface F2 of the cell trench gate structure 30 can also be set as other ring-shaped surfaces that are easy to manufacture, as long as they are concentrically arranged. , such as circles, rounded hexagons, and so on. For example, in an alternative example, the lateral cross-sectional shapes of the annular side surface F1 of the terminal trench gate structure 20 and the side surface F2 of the cellular trench gate structure 30 may also be right-angled rectangles, which is more convenient for manufacturing and processing. In this variant, the terminal trench gate structure includes a plurality of first strip segments extending along a set direction X and a plurality of second strip segments extending in a direction perpendicular to the set direction X, all of the second strips Segments and all the cellular trench gate structures are alternately arranged along the set direction X, and the ends of any two adjacent second strip segments in the set direction X pass through the first strip section connection.

In this embodiment, the terminal trench gate structure 20 includes several (four as an example in the figure) strip segments 21 and several (six as an example in the figure) arc-shaped segments 22, and several strip segments 21 and several The cellular trench gate structure 30 is arranged alternately and at intervals along the set direction X, and the ends of any two adjacent strip segments 21 in the set direction X are connected by the arc segment 22 , so that any two adjacent bar-shaped segments 21 and the corresponding two arc-shaped segments 22 connecting the two bar-shaped segments 21 form a round-end rectangle surrounding a cell trench gate structure 30, and the terminal trench gate The side profile F3 of the structure 20 has the same shape as the annular side surface F1 at corresponding positions.

It should be noted that, in other embodiments, the side profile F3 of the terminal trench gate structure 20 and the annular side surface F1 may also have different shapes at corresponding positions, for example, the side profile F3 of the terminal trench gate structure 20 is Rectangular, circular, oval, etc.

Further, the thickness D1 of the arc segment 22, the thickness D3 of the strip segment 21, and the thickness D2 of the cellular trench gate structure 30 are equal, so that the terminal trench gate structure 20, the cellular trench gate structure 30 The thickness remains the same, and the so-called thickness refers to the dimension in the direction parallel to the substrate. In some embodiments, the thicknesses D1 , D2 , D3 are set to be 1 μm to 3.5 μm.

It should be noted that, in other embodiments, the thicknesses of the terminal trench gate structure 20 and the cellular trench gate structure 30 may also be set to be different, for example, the thickness of the terminal trench gate structure 20 is greater than that of the cellular trench gate structure 30 thickness of.

According to the above, it can be seen that the above-mentioned arrangement between the terminal trench gate structure and the cell trench gate structure can keep the distance between the trench gate structures in the semiconductor device consistent, so that the electrical parameters of the product have better consistency. The arrangement between the terminal trench gate structure and the cell trench gate structure can be applied to various semiconductor devices with trench gate structures, and will be described in sequence through three embodiments below.

first embodiment

7 is a schematic cross-sectional view of a semiconductor device in the first embodiment of the present invention. As shown in FIG. 7, the semiconductor structure includes a split-gate trench MOSFET, and the split-gate trench MOSFET includes a terminal trench in the substrate 10 For the arrangement of the gate structure 20 and the plurality of cellular trench gate structures 30 , and the terminal trench gate structure 20 and the plurality of cellular trench gate structures 30 , refer to the above, and details will not be repeated here.

Both the terminal trench gate structure 20 and the cellular trench gate structure 30 include a trench T located in the substrate 10, the dielectric layer 40 covers the inner wall of the trench T, and the first gate 50 is located in the trench T , and the first gate 50 is isolated from the substrate 10 by the dielectric layer 40 . Wherein, the cellular trench gate structure 30 further includes a second gate 60 located in the trench T, and the second gate 60 is isolated from the first gate 50 by the dielectric layer 40 . Specifically, the first gate 50 and the second gate 60 are arranged at intervals along a direction parallel to the substrate 10 , and the second gate 60 is located outside the first gate 50 . In some other embodiments, the depth of the second gate 60 is 0.6 μm to 2 μm.

In this embodiment, the substrate 10 includes a first type heavily doped substrate 101 and a first type lightly doped epitaxial layer 102 on the surface of the first type heavily doped substrate 101, and a first type lightly doped epitaxial layer 102 is formed in the first type lightly doped epitaxial layer 102. There are a first type doped region 103 and a second type doped region 104 , and the second type doped region 104 is located on the surface of the first type doped region 103 . In this embodiment, the material of the substrate 10 is silicon, the first type is N type, and the second type is P type. In other embodiments, according to the type of the semiconductor device, it may also be set that the first type is P-type and the second type is N-type. Specifically, the depth of the first type doped region 103 may be set to 0.2 μm to 1.5 μm, and the depth of the second type doped region 104 may be set to be 0.1 μm to 0.7 μm.

In this embodiment, the longitudinal section of the trench T is substantially rectangular, the sidewalls are perpendicular to the surface of the substrate 10, and the corners of the bottom have rounded corners, so that the inner wall surface of the trench T is relatively smooth, which can avoid the occurrence of peak electric fields, thereby Improve device reliability. In other specific embodiments of the present utility model, the trench T has an inclined side wall, so that the width of the top of the trench T is slightly larger than the width of the bottom, which is convenient for filling the material inside the trench. The specific angle of inclination of the inclined side wall is The angle between the inclined sidewall and the surface of the substrate 10 is 85°-90° (89.5-90 deg is the best), which can make the width of the upper part of the current path and the width of the bottom consistent, and the on-resistance is reduced.

In this embodiment, the material of the dielectric layer 40 is silicon oxide, the material of the first gate 50 and the second gate 60 is polysilicon, and the first gate 50 is heavily doped with the first type.

Continuing to refer to FIG. 7, the substrate 10, the terminal trench gate structure 20, and the plurality of cellular trench gate structures 30 are covered with an insulating layer 70, and the first conductive plug CT1 passes through the insulating layer 70 and connects with the first gate The electrode 50 forms an ohmic contact electrical connection, and the second conductive plug CT2 passes through the insulating layer 70 and the second-type doped region 104, and is connected to the first-type doped region 103 and the second-type doped region 104. An ohmic contact electrical connection is formed. The metal layer 80 is located on the insulating layer 70 , the first conductive plug CT1 and the second conductive plug CT2 , and is electrically connected to the first conductive plug CT1 and the second conductive plug CT2 . The metal layer 80 forms an ohmic contact with the first-type doped region 103 through the second conductive plug CT2, and short-circuits the first-type doped region 103 and the second-type doped region 104 to avoid conduction of the parasitic transistor. The third conductive plug (not shown) passes through the insulating layer 70, and one end thereof forms an ohmic contact electrical connection with the second gate 60, and the other end is electrically connected with another metal layer (not shown). When the semiconductor device is in operation , different voltages are applied to the other metal layer and the metal layer 80 .

In this embodiment, the insulating layer 70 is made of undoped silicon glass or phosphorus-doped borosilicate glass, the apertures of the first conductive plug CT1 and the second conductive plug CT2 are 0.2 μm to 1.2 μm, and the material of the metal layer 80 includes Other metal materials such as aluminum or Cu.

8 to 13 are schematic cross-sectional views of the semiconductor device shown in FIG. 7 at various manufacturing stages. The method for forming the semiconductor device of the first embodiment will be described in detail below with reference to FIGS. 7 to 13 .

As shown in FIG. 8, a substrate 10 is provided. The substrate 10 includes a first type heavily doped base 101 and a first type lightly doped epitaxial layer 102 on the surface of the first type heavily doped base 101 . In this embodiment, the material of the substrate 10 is silicon, the first type is N type, and the second type is P type. In other embodiments, according to the type of the semiconductor device, it may also be set that the first type is P-type and the second type is N-type.

A number of trenches T are formed in the lightly doped epitaxial layer 102 of the substrate 10, and the trenches include two types, namely, a terminal trench for forming a terminal trench gate structure, and a trench T for forming a cell trench gate structure. cell groove. The method for forming the trench T includes: forming a patterned mask layer (not shown) on the substrate 10; using the patterned mask layer as a mask to etch the substrate 10 to form the trench T, The etching method may be dry etching or wet etching; removing the patterned mask layer.

As shown in FIG. 4 , in several trenches T, the terminal trench where the terminal trench gate structure 20 is located has a number of annular side surfaces arranged at intervals along the set direction X, and the cells where the trench gate structure 30 is located The grooves are respectively located on the inner side of several of the annular side surfaces, and the annular side surface of each terminal groove is arranged concentrically with the side surface of the corresponding inner cell trench gate at a constant distance.

Continuing to refer to FIG. 8 , a first dielectric material layer 400 covering the upper surface of the substrate 10 , the sidewalls and the bottom wall of the trench T is formed, and the first dielectric material layer 400 does not fill the trench T. The material of the first dielectric material layer 400 is silicon oxide, the thickness is 0.5 μm to 2 μm, and the formation method is chemical vapor deposition, thermal oxidation, atomic layer deposition and the like. A first gate material layer 500 is formed on the first dielectric material layer 400 , and part of the first gate material layer 500 is filled in the trench T. Referring to FIG. The material of the first gate material layer 500 is polysilicon, and the formation method is chemical vapor deposition, atomic layer deposition and the like.

As shown in FIG. 9 , the first gate material layer 500 outside the trench T (combined with FIG. 8 ) is removed, and the remaining first gate material layer 500 constitutes the first gate 50 . The removal method of the first gate material layer 500 is dry etching.

As shown in FIG. 10 , part of the first dielectric material layer 400 in the cell trench T is removed (combined with FIG. 9 ), so that the top sidewall of the first gate 50 in the cell trench T, The end sidewalls of the trench T are all exposed. In some embodiments, the exposed top sidewall of the first gate 50 has a depth H of 0.6 μm to 2 μm.

As shown in FIG. 11 , a second dielectric material layer 401 is formed on the exposed top sidewall of the first gate 50 and the end sidewall of the trench T, and the second dielectric material layer 401 contains A groove (not marked) located on the periphery of the first gate 50 . The material of the second dielectric material layer 401 is silicon oxide, which is formed by thermal oxidation of the exposed top sidewall of the first gate 50 and the end sidewall of the trench T. A second gate material layer 600 covering the second dielectric material layer 401 is formed, and the second gate material layer 600 fills in the groove of the second dielectric material layer 401 . In some embodiments, the material of the second gate material layer 600 is polysilicon.

As shown in FIG. 12, the second dielectric material layer 401 and the second gate material layer 600 (combined with FIG. 11) outside the trench T are removed to form the terminal trench gate structure 20 and the cell trench gate structure respectively. 30. The method of removing the part of the second dielectric material layer 401 and the second gate material layer 600 is etching or chemical mechanical polishing.

As shown in FIG. 13 , ion implantation is performed on part of the lightly doped epitaxial layer 102 of the substrate 10 to form a first type doped region 103 . In this embodiment, the first type is N type, and the depth of the first type doped region 103 is 0.2 μm to 1.5 μm. Next, ion implantation is performed on part of the lightly doped epitaxial layer 102 of the substrate 10 again to form the second type doped region 104 on the surface layer of the first type doped region 103 . In this embodiment, the second type is P-type, and the depth of the second-type doped region 104 is 0.1 μm to 0.7 μm.

7 and 13, an insulating layer 70 is formed on the substrate 10, the terminal trench gate structure 20 and the cell trench gate structure 30. In this embodiment, the material of the insulating layer 70 is undoped Silicon glass or phosphorus-doped borosilicate glass, formed by chemical vapor deposition. Next, etching is performed to form a first hole (not marked) passing through the insulating layer 70, a third hole (not shown) and a first hole (not shown) passing through the insulating layer 70 and the second type doped region 104. Two insertion holes (not marked), the first insertion hole exposes the first grid 50 , the third insertion hole exposes the second grid 60 , and the second insertion hole exposes the first type doped region 103 . Then, filling the first hole, the second hole, and the third hole with metal to respectively form a first conductive plug CT1 electrically connected to the first grid 50 ohm contact, and the first conductive plug CT1 Both the type doped region 103 and the second type doped region 104 are in ohmic contact with the second conductive plug CT2 electrically connected to the third conductive plug (not shown) electrically connected with the second gate 70 . In this embodiment, the apertures of the first conductive plug CT1 and the second conductive plug CT2 are 0.2 μm to 1.2 μm. Finally, a metal layer 80 is formed on the insulating layer 70 , the first conductive plug CT1 and the second conductive plug CT2 , and another metal layer (not shown) is formed on the third conductive plug. In this embodiment, the material of the metal layer 80 includes other metal materials such as aluminum or Cu, and the method of forming the metal layer 80 is physical vapor deposition or electroplating.

second embodiment

The difference between the second embodiment and the first embodiment is that referring to FIG. 14 , the first gate 50 and the second gate 60 are arranged at intervals along the depth direction Z of the trench T. Referring to FIG.

third embodiment

Referring to FIG. 15, in this embodiment, the semiconductor device includes a trench Schottky diode, which includes a terminal trench gate structure 20b and several cell trench gate structures 30b in the substrate 10b, and the terminal trench For the arrangement of the gate structure 20b and the plurality of cell trench gate structures 30b, reference is made to the above, and details will not be repeated here. Both the terminal trench gate structure 20b and the cell trench gate structure 30b include a trench T1 in the substrate 10b, a dielectric layer 40b covering the inner wall of the trench T1, and a trench T1 in the trench T1. And cover the gate 50b on the dielectric layer 40b. Specifically, the material of the dielectric layer 40b is silicon oxide, and the material of the gate 50b is polysilicon. The Schottky metal layer 90 covers the substrate 10b, the terminal trench gate structure 20b and the cell trench gate structure 30b to form a Schottky contact.

On the basis of the embodiments of the above-mentioned semiconductor devices, the utility model also provides a chip, which includes several first-type semiconductor devices and several second-type semiconductor devices, the first-type semiconductor devices, the second-type semiconductor devices For the specific structure of the device, refer to the above description, which will not be repeated here. The cell trench gate structures of the first type of semiconductor device are arranged at intervals along a first direction, the cell trench gate structures of the second type of semiconductor device are arranged at intervals along a second direction, and the second The direction is perpendicular to the first direction, thus, the cell trench gate structures on the chip are alternately distributed along two perpendicular directions, and the stress brought by the cell trench gate structures is also alternately distributed along two perpendicular directions distribution, avoiding chip problems.

In an embodiment, as shown in FIG. 16 , the chip includes semiconductor devices C1-C7, the cell trench gate structures 30c of the semiconductor devices C1-C6 are arranged at intervals along the first direction L1, and the cell trenches of the three semiconductor devices C7 The gate structures 30d are arranged at intervals along a second direction L2 perpendicular to the first direction L1. The semiconductor devices C1-C3 are arranged in a row along the first direction L1, the semiconductor devices C4-C6 are arranged in a row along the first direction L1, and the two rows of semiconductor devices are arranged at intervals along the second direction L2. The three semiconductor devices C7 are arranged in a row along the first direction L1 and distributed between the two rows of semiconductor devices.

The above is only a preferred embodiment of the utility model, it should be pointed out that for those of ordinary skill in the art, without departing from the principle of the utility model, some improvements and modifications can also be made. It should be regarded as the protection scope of the present utility model.

Claims (13)

1. A semiconductor device, characterized in that, comprising: a terminal trench gate structure and a plurality of cellular trench gate structures located in the substrate; The terminal trench gate structure has several annular side surfaces arranged at intervals along a set direction; A plurality of the cellular trench gate structures are respectively located inside the plurality of annular side surfaces, and the annular side surface of each terminal trench gate structure is at a constant distance from the side surface of the corresponding inner cellular trench gate structure Concentric setting. 2. The semiconductor device according to claim 1, wherein the lateral cross-sections of the annular side surface of the terminal trench gate structure and the side surface of the cell trench gate structure are rounded rectangles or right-angled rectangles . 3. The semiconductor device according to claim 2, wherein the terminal trench gate structure comprises: certain first paragraphs; Several second segments are arranged alternately and alternately with several of the cellular trench gate structures along the set direction; The ends of any two adjacent second segments in the set direction are connected by the first segment; When the transverse section is a rounded rectangle, the first segment is an arc segment, and the second segment is a strip segment; When the transverse cross-section is a right-angled rectangle, the first section and the second section are strip-shaped sections. 4. The semiconductor device according to claim 3, wherein the thickness of the first segment is equal to the thickness of the second segment, and the thickness is a dimension in a direction parallel to the substrate. 5. The semiconductor device according to claim 4, wherein the thickness of the cell trench gate structure is equal to the thickness of the first segment. 6. The semiconductor device according to any one of claims 1 to 5, wherein the semiconductor device comprises a split-gate trench MOSFET having the terminal trench gate structure and the cell trench gate structure; Both the terminal trench gate structure and the cell trench gate structure include: a trench in the substrate; a dielectric layer covering the inner wall of the trench; a first gate located within the trench, the first gate being isolated from the substrate by the dielectric layer; The cell trench gate structure further includes a second gate located in the trench, and the first gate and the second gate are separated by the dielectric layer. 7. The semiconductor device according to claim 6, wherein the first gate and the second gate are arranged at intervals along a direction parallel to the substrate, and the second gate is located at the first outside of a gate. 8. The semiconductor device according to claim 6, wherein the first gate and the second gate are arranged at intervals along the depth direction of the trench. 9. The semiconductor device according to claim 7, further comprising: an insulating layer over the substrate, the terminal trench gate structure, and the cellular trench gate structure; A first conductive plug passing through the insulating layer, the first conductive plug is electrically connected to the first gate by forming an ohmic contact; A metal layer located on the insulating layer and the first conductive plug, the metal layer is electrically connected to the first conductive plug. 10. The semiconductor device according to claim 9, wherein a first-type doped region and a second-type doped region are formed in the substrate, and the second-type doped region is located in the first the surface of the type doped region; The semiconductor device further includes: a second conductive plug passing through the insulating layer and the second type doped region, the second conductive plug is connected to the first type doped region and the second type doped region Both form an ohmic contact electrical connection. 11. The semiconductor device according to any one of claims 1 to 5, wherein the semiconductor device comprises a trench Schottky diode having the terminal trench gate structure and the cell trench gate structure; Both the terminal trench gate structure and the cell trench gate structure include: a trench in the substrate; a dielectric layer covering the inner wall of the trench; A gate located in the trench and covering on the dielectric layer. 12. A chip, characterized by comprising the semiconductor device according to any one of claims 1 to 11. 13. The chip according to claim 12, wherein the cell trench gate structures of at least one of the semiconductor devices are arranged at intervals along the first direction, and the cell trench gate structures of at least one of the other semiconductor devices The cell trench gate structures are arranged at intervals along a second direction, and the second direction is perpendicular to the first direction.