CN202663360U - High-speed phase splitting circuit with band spreading function - Google Patents

Abstract

The utility model belongs to the communication circuit field, relates to a high-speed phase splitting circuit with a band spreading function and aims at removing limit of trans-impedance amplifier bandwidth in the existing phase splitting circuit to work frequency of a head amplifier. The high-speed phase splitting circuit with the band spreading function comprises a first P-channel metal oxide semiconductor (PMOS) transistor M1, a resistor R1, a resistor R 2, a phase splitting amplifier and an integrator. The phase splitting amplifier is composed of a first amplifier A1 and a second amplifier A 2 in cascading mode. The integrator is composed of a third amplifier A3, a resistor R3, a resistor R4 and a capacitor C1. A source electrode of the first PMOS transistor M1 is connected with a power supply through the resistor R1, a drain electrode of the first PMOS transistor M1 is grounded through the resistor R 2, and the source electrode of the first PMOS transistor M1 is further connected with a normal-phase input end of the first amplifier A1. Two output ends of the second amplifier A 2 are respectively connected with two input ends of the integrator, and the output end of the integrator is connected with a reverse-phase input end of the first amplifier A1.

Description

High-speed phase splitting circuit with frequency band extension function

technical field

The utility model relates to a high-speed phase splitting circuit for an optical fiber preamplifier. The phase splitting circuit uses a phase splitting amplifier with a frequency band expansion function to increase the working frequency of the preamplifier.

Background technique

Optical fiber communication uses light as the information carrier and optical fiber as the transmission medium. It has the advantages of high bandwidth, low loss, and small external electromagnetic interference. It has become the main form of network communication. The optical transceiver module is the core device of the optical fiber access network, mainly composed of two parts: the receiving module and the transmitting module. The transmitter module is mainly composed of a laser drive circuit and a laser diode (LD). The laser diode converts the electrical signal sent by the user into an optical signal and emits it. The drive circuit provides the drive current for the laser diode to determine the output power and speed. The receiving module is mainly composed of a photodiode (PD), a preamplifier and a limiting amplifier. The photodiode receives the optical signal transmitted by the network and converts it into a current signal, and the preamplifier amplifies the current signal into a voltage signal. The limiting amplifier further amplifies the output signal of the preamplifier and turns it into a digital signal that meets the user's amplitude requirements.

The working principle of the preamplifier and photodiode is shown in Figure 1. The photodiode receives the optical signal transmitted by the network, and converts the optical signal into a corresponding current signal I _IN and inputs it to the preamplifier. _CD in Figure 1 is the equivalent parasitic capacitance of the photodiode, and the part in the dashed box is the preamplifier. The preamplifier is mainly composed of two parts: a transimpedance amplifier and a phase splitting circuit. The transimpedance amplifier is composed of the amplifier A and the feedback resistor R _F , and converts the input current signal into a single-ended voltage signal V _{O_TIA} for output. However, the single-ended output signal is easily affected by power disturbance and noise, resulting in misjudgment of the output signal. For this reason, the preamplifiers widely used in the industry at present introduce a phase splitting circuit behind the transimpedance amplifier to convert the single-ended signal output by the transimpedance amplifier into a differential form to improve the signal's resistance to power and common-mode voltage changes. inhibition ability. Generally, the phase splitting circuit only converts the input single-ended signal into a differential signal with a phase difference of 180 degrees, which basically does not affect the gain and operating frequency of the preamplifier. That is, important indicators such as the gain and bandwidth of the preamplifier are determined by parameters such as the gain of the transimpedance amplifier and the parasitic capacitance of the photodiode. Therefore, the bandwidth of the transimpedance amplifier becomes the main bottleneck limiting the operating frequency of the overall preamplifier.

The phase splitting circuit in the traditional optical fiber preamplifier generally obtains its common-mode voltage by passing the input signal through a low-pass filter. However, the capacitance of this low-pass filter is large to obtain a lower cut-off frequency, which requires more chip area, and the response time of the low-pass filter will be longer. Therefore, it often occurs that the common-mode voltages at both ends of the phase-split amplifier are not exactly equal, resulting in an offset of the common-mode voltage or a phase shift of the two differential signals. At the same time, there are other solutions, such as the Chinese patent "High Speed Phase Splitting Circuit", whose publication number is CN101626232, and the publication date is January 13, 2010. It proposes a high-speed phase splitting circuit, and its phase splitting circuit consists of phase splitting The amplifier and the lossy integrator are composed of parts such as the lossy integrator. The input signal of the lossy integrator comes from the output of the phase splitting amplifier to generate the common mode voltage at the input end of the phase splitting amplifier. The phase splitting amplifier combines the input single-ended signal with the output of the lossy integrator. The difference of the common mode voltage is amplified to obtain a differential signal with a phase difference of 180 degrees. However, this solution has the following disadvantages: firstly, the phase splitting circuit does not have a frequency extension function, and cannot increase the operating frequency of the entire preamplifier. Second, the lossy integrator requires a linear resistor in parallel with the integrating capacitor, which greatly increases the chip area and reduces the low-frequency gain of the amplifier. Third, a compensation resistor is added to the non-inverting input of the lossy integrator to compensate the current difference between its non-inverting and inverting terminals. However, due to the existence of random mismatch in the processing process, the compensation resistor cannot be exactly equal to the linear resistance of the lossy integrator, which will cause a deviation in the output common-mode voltage of the lossy integrator, making the output differential signal of the phase splitting amplifier appear significantly The DC deviation will cause unnecessary DC offset to the subsequent stage circuit, resulting in misjudgment of the optical receiving module.

Contents of the invention

The purpose of the utility model is to solve the restriction of the bandwidth of the transimpedance amplifier in the existing phase splitting circuit to the operating frequency of the preamplifier, and propose a phase splitting circuit with a frequency band expansion function, which can improve the frequency of the preamplifier working frequency.

The high-speed phase splitting circuit with frequency band expansion function described in the utility model includes a first PMOS transistor M1, a resistor R1, a resistor R2, a phase splitting amplifier and an integrator,

The phase splitting amplifier is composed of the first amplifier A1 and the second amplifier A2 cascaded,

The integrator is composed of a third amplifier A3, a resistor R3, a resistor R4 and a capacitor C1,

One end of the resistor R1 is connected to the power supply VDD! , the other end of the resistor R1 is simultaneously connected to the source of the first PMOS transistor M1 and the non-inverting input terminal VIP of the first amplifier A1, the gate of the first PMOS transistor M1 is used as the receiving end of the transimpedance amplifier output signal VO_TIA, and the first PMOS transistor M1 The drain is connected to one end of resistor R2, and the other end of resistor R2 is connected to GND! ;

The inverting input terminal VIN of the first amplifier A1 is connected to the output terminal VCM of the third amplifier A3,

The inverting output terminal VON of the second amplifier A2 is connected to one end of the resistor R4, and the other end of the resistor R4 is connected to the non-inverting input terminal of the third amplifier A3,

The non-inverting output terminal VOP of the second amplifier A2 is connected to one end of the resistor R3, and the other end of the resistor R3 is connected to the inverting input terminal of the third amplifier A3,

The capacitor C1 is connected between the inverting input terminal and the output terminal of the third amplifier A3.

The first amplifier A1 includes a first NMOS transistor MN1_A1, a second NMOS transistor MN2_A1, a third NMOS transistor MN3_A1, a fourth NMOS transistor MN4_A1, a fifth NMOS transistor MN5_A1, a sixth NMOS transistor MN6_A1, a resistor RB_A1, a resistor RS1_A1, a resistor RS2_A1 and Resistor RCM_A1,

One end of the resistor RB_A1 is connected to the power supply VDD! , the other end of the resistor RB_A1 is connected to the common terminal of the gate of the sixth NMOS transistor MN6_A1 and its drain, and the source of the sixth NMOS transistor MN6_A1 is connected to GND! ;

One end of the resistor RCM_A1 is connected to the power supply VDD! , the other end of the resistor RCM_A1 is connected to the drain common end of the third NMOS transistor MN3_A1 and the fourth NMOS transistor MN4_A1;

The gate of the third NMOS transistor MN3_A1 is connected to one end of the resistor RS1_A1, and the other end of the resistor RS1_A1 is connected to the other end of the resistor RB_A1;

The common end connected between the source of the third NMOS transistor MN3_A1 and the drain of the first NMOS transistor MN1_A1 is used as the non-inverting output terminal VOP1 of the first amplifier A1; the gate of the first NMOS transistor MN1_A1 is used as the inverting input terminal of the first amplifier A1 VIN, the source common terminal of the first NMOS transistor MN1_A1 and the second NMOS transistor MN2_A1 are connected to the drain of the fifth NMOS transistor MN5_A1, the gate of the fifth NMOS transistor MN5_A1 is used as the input terminal of the tail current bias voltage of the first amplifier A1, and the second The source of the five NMOS transistor MN5_A1 is connected to GND! ;

The common terminal connected to the drain of the second NMOS transistor MN2_A1 and the source of the fourth NMOS transistor MN4_A1 serves as the inverting output terminal VON1 of the first amplifier A1, and the gate of the second NMOS transistor MN2_A1 serves as the non-inverting input terminal of the first amplifier A1 VIP;

The gate of the fourth NMOS transistor MN4_A1 is connected to one end of the resistor RS2_A1, and the other end of the resistor RS2_A1 is connected to the other end of the resistor RB_A1.

The second amplifier A2 includes a seventh NMOS transistor MN1_A2, an eighth NMOS transistor MN2_A2, a ninth NMOS transistor MN3_A2, a second PMOS transistor MP1_A2, a third PMOS transistor MP2_A2, a resistor RL1_A2, a resistor RL2_A2, a resistor RC_A2, a capacitor CL1_A2 and a capacitor CL2_A2,

One end of the resistor RC_A2 is connected to the power supply VDD! , the other end of the resistor RC_A2 is connected to the source common terminals of the second PMOS transistor MP1_A2 and the third PMOS transistor MP2_A2,

The capacitor CL1_A2 is connected between the source and the gate of the second PMOS transistor MP1_A2, the resistor RL1_A2 is connected between the drain and the gate of the second PMOS transistor MP1_A2,

The capacitor CL2_A2 is connected between the source and the gate of the third PMOS transistor MP2_A2, the resistor RL2_A2 is connected between the drain and the gate of the third PMOS transistor MP2_A2,

The drain of the second PMOS transistor MP1_A2 and the drain of the seventh NMOS transistor MN1_A2 are connected to the common terminal as the non-inverting output terminal VOP of the second amplifier A2, and the gate of the seventh NMOS transistor MN1_A2 is used as the inverting input terminal VIN2 of the second amplifier A2 ;

The drain of the third PMOS transistor MP2_A2 and the drain of the eighth NMOS transistor MN2_A2 are connected to a common terminal as the inverting output terminal VON of the second amplifier A2, and the gate of the eighth NMOS transistor MN2_A2 is used as the non-inverting input terminal VIP2 of the second amplifier A2 ;

The source of the seventh NMOS transistor MN1_A2 is connected to the source of the eighth NMOS transistor MN2_A2, and the source of the seventh NMOS transistor MN1_A2 is also connected to the drain of the ninth NMOS transistor MN3_A2,

The gate of the ninth NMOS transistor MN3_A2 serves as the tail current bias voltage input terminal of the second amplifier A2;

The source of the ninth NMOS transistor MN3_A2 is connected to GND! .

Advantages of the utility model: the utility model designs a phase split circuit with a frequency band extension function, which is mainly composed of a phase split amplifier and an integrator, wherein the phase split amplifier is composed of two cascaded amplifiers with a frequency extension function Composition can expand the operating bandwidth of the phase splitting circuit, thereby increasing the operating frequency of the entire preamplifier.

Compared with the phase splitting circuit that does not apply the frequency band expansion function, the frequency band expansion function is an active inductance formed by on-chip MOS transistors, resistors and capacitors, and its inductance can be adjusted by adjusting the on-chip resistors and capacitors to fulfill.

The specific effect of the utility model has been verified by circuit simulation results in the worst case of circuit simulation. The variation of transistor threshold voltage during processing can be reflected by the variation of process corner (Process Corner) in the simulation. Typically, the threshold voltage deviation of transistors is zero, which is generally called TT situation. When the transistor conduction becomes faster, the threshold voltage of all transistors decreases. This is the FF mode of the process corner, and its threshold voltage is reduced by about 20% compared with typical conditions; otherwise, it is SS mode, and its threshold voltage is more typical. Increase around 20%. Changes in process parameters will affect factors such as transistor threshold voltage and electron mobility, which will also significantly affect the -3dB bandwidth of the transimpedance amplifier. Table 1 shows the comparison of the -3dB bandwidth of the preamplifier without using the phase splitting circuit with the function of frequency band extension and applying the phase splitting circuit with the function of frequency band under the condition of the change of the process angle. It can be seen from Table 1 that when the FF condition occurs in the processing process, the bandwidth of the preamplifier is the lowest, only 1.63GHz. After applying the phase splitting circuit with the function of frequency band expansion, the bandwidth of the preamplifier reaches 2.336GHz. Its bandwidth has been improved by 706MHz. When the TT condition of the processing process occurs, the bandwidth of the preamplifier is 1.981GHz. After applying the phase splitting circuit with the function of frequency band extension, the bandwidth of the preamplifier is 2.423GHz, and the bandwidth improvement reaches 442MHz. In the case of SS, the bandwidth improvement of the phase splitting circuit with frequency extension function is only 276MHz. The results in Table 1 show that the phase splitting circuit with frequency extension function can significantly improve the working bandwidth of the preamplifier, and reduce the change rate of the bandwidth under different process angles.

Table 1 Bandwidth improvement of the preamplifier under process corner variation

Description of drawings

Fig. 1 is the working principle block diagram of background technology preamplifier and photodiode;

Fig. 2 is a schematic diagram of a phase splitting circuit with a frequency band extension function;

The circuit structure diagram of the amplifier A1 with the frequency band extension function in the phase splitting amplifier of Fig. 3;

The circuit structure diagram of the amplifier A2 with the function of frequency band extension in the phase splitting amplifier in Fig. 4 .

Detailed ways

Specific embodiment one: the present embodiment is described below in conjunction with Fig. 2, the high-speed phase splitting circuit with frequency band expansion function described in the present embodiment, it comprises the first PMOS transistor M1, resistance R1, resistance R2, phase splitting amplifier and integrator,

The phase splitting amplifier is composed of the first amplifier A1 and the second amplifier A2 cascaded,

The integrator is composed of a third amplifier A3, a resistor R3, a resistor R4 and a capacitor C1,

One end of the resistor R1 is connected to the power supply VDD! , the other end of the resistor R1 is simultaneously connected to the source of the first PMOS transistor M1 and the non-inverting input terminal VIP of the first amplifier A1, the gate of the first PMOS transistor M1 is used as the receiving end of the transimpedance amplifier output signal VO TIA, the first PMOS transistor The drain of M1 is connected to one end of resistor R2, and the other end of resistor R2 is connected to GND! ;

The inverting input terminal VIN of the first amplifier A1 is connected to the output terminal VCM of the third amplifier A3,

The inverting output terminal VON of the second amplifier A2 is connected to one end of the resistor R4, and the other end of the resistor R4 is connected to the non-inverting input terminal of the third amplifier A3,

The non-inverting output terminal VOP of the second amplifier A2 is connected to one end of the resistor R3, and the other end of the resistor R3 is connected to the inverting input terminal of the third amplifier A3,

The capacitor C1 is connected between the inverting input terminal and the output terminal of the third amplifier A3.

The first PMOS transistor M1 forms a source follower, the input signal of the first PMOS transistor M1 is the output signal VO_TIA of the transimpedance amplifier, the output signal of the first PMOS transistor M1 is transmitted to the phase splitting amplifier, and the phase splitting amplifier consists of two The extended-function amplifiers A1 and A2 are cascaded. The non-inverting output VOP and the inverting output VON of the second amplifier A2 (also of the phase splitting amplifier) mainly have two functions:

First, the post-stage circuit of the preamplifier provides the input voltage;

Second, the common-mode voltage difference between the two is transmitted to the input of the integrator. The integrator will amplify the common-mode voltage difference between VOP and VON, and adjust the common-mode voltage of the inverting input terminal VIP of the phase-splitting amplifier according to the amplification result to ensure that the common-mode voltage of the non-inverting input terminal VIN of the phase-splitting amplifier is the same as The VIPs are equal to realize the function of the phase splitting amplifier circuit.

Circuit implementation:

A phase splitting circuit with a frequency band extension function, a source follower is connected to a phase splitting amplifier, and the phase splitting amplifier is connected to an integrator; its source follower performs level shift on the signal output by the transimpedance amplifier; its The phase splitting amplifier converts the input single-ended signal into a double-ended differential signal, and has the function of frequency band expansion; its integrator, the two input ends are respectively connected to the output end of the phase splitting amplifier, and the output end is connected to the phase splitting amplifier. On the inverting input, the common-mode voltage is provided for the phase-splitting amplifier.

The phase splitting amplifier is composed of two cascaded fully differential amplifiers, and is an amplifier with a frequency band extension function.

Specific Embodiment 2: The present embodiment will be described below with reference to FIG. 3. This embodiment is a further description of Embodiment 1. The first amplifier A1 includes a first NMOS transistor MN1_A1, a second NMOS transistor MN2_A1, a third NMOS transistor MN3_A1, a first Four NMOS transistors MN4_A1, fifth NMOS transistors MN5_A1, sixth NMOS transistors MN6_A1, resistors RB_A1, resistors RS1_A1, resistors RS2_A1 and resistors RCM_A1,

One end of the resistor RB_A1 is connected to the power supply VDD! , the other end of the resistor RB_A1 is connected to the common terminal of the gate of the sixth NMOS transistor MN6_A1 and its drain, and the source of the sixth NMOS transistor MN6_A1 is connected to GND! ;

One end of the resistor RCM_A1 is connected to the power supply VDD! , the other end of the resistor RCM_A1 is connected to the drain common end of the third NMOS transistor MN3_A1 and the fourth NMOS transistor MN4_A1;

The gate of the third NMOS transistor MN3_A1 is connected to one end of the resistor RS1_A1, and the other end of the resistor RS1_A1 is connected to the other end of the resistor RB_A1;

The common end connected between the source of the third NMOS transistor MN3_A1 and the drain of the first NMOS transistor MN1_A1 is used as the non-inverting output terminal VOP1 of the first amplifier A1; the gate of the first NMOS transistor MN1_A1 is used as the inverting input terminal of the first amplifier A1 VIN, the source common terminal of the first NMOS transistor MN1A1 and the second NMOS transistor MN2_A1 is connected to the drain of the fifth NMOS transistor MN5_A1, the gate of the fifth NMOS transistor MN5_A1 is used as the input terminal of the tail current bias voltage of the first amplifier A1, and the second The source of the five NMOS transistor MN5_A1 is connected to GND! ;

The common terminal connected to the drain of the second NMOS transistor MN2_A1 and the source of the fourth NMOS transistor MN4_A1 serves as the inverting output terminal VON1 of the first amplifier A1, and the gate of the second NMOS transistor MN2_A1 serves as the non-inverting input terminal of the first amplifier A1 VIP;

The gate of the fourth NMOS transistor MN4_A1 is connected to one end of the resistor RS2_A1, and the other end of the resistor RS2_A1 is connected to the other end of the resistor RB_A1.

The resistor RB_A1 in Figure 3 and the sixth transistor MN6_A1 form a bias circuit to generate a bias voltage VB2, the voltage of which can be expressed as

VB2＝VGS _{MN6_A1} ＝VDD-I*R _{RB_A1} (1)

In the formula (1), VGS _{MN6_A1} is the voltage between the gate and the source of the sixth transistor MN6_A1, and R _{RB_A1} is the resistance value of the resistor RB_A1.

The bias voltage VB2 provides gate bias voltages for the third NMOS transistor MN3_A1 and the fourth NMOS transistor MN4_A1. The first NMOS transistor MN1_A1, the second NMOS transistor MN2A_1, the third NMOS transistor MN3_A1, the fourth NMOS transistor MN4_A1 and the fifth NMOS transistor MN5_A1 form the main structure of the first amplifier A1, wherein the gate of the fifth NMOS transistor MN5_A1 is driven by VB1 , to provide a bias current for the first amplifier A1. The gate of the first NMOS transistor MN1_A1 is connected to the inverting input terminal VIN of the first amplifier A1, and the second NMOS MN2_A1 is connected to the non-inverting input terminal VIP to form a differential pair of transistors of the first amplifier A1. The third NMOS transistor MN3_A1 and the fourth NMOS transistor MN4_A1 are formed, the sources of which are connected to the bias voltage VB2 through the resistor RS1_A1 and the resistor RS2_A1. An active inductance is formed by the third NMOS transistor MN3_A1 and its source resistance RS1_A1, the impedance of which can be expressed as

${\mathrm{<span\; class="notranslate">\; Z</span>}}_{\mathrm{<span\; class="notranslate">\; out</span>}}<span\; class="notranslate">\; -</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}}}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; *</span>{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; GS</span>}}<span\; class="notranslate">\; *</span><span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; S</span>}}<span\; class="notranslate">\; -</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}}}<span\; class="notranslate">\; )</span>}{{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; *</span>{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; GS</span>}}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; )</span>$

where _Zout is the equivalent impedance seen from the source of the third NMOS transistor MN3_A1, _gm is the transconductance of the third NMOS transistor MN3_A1, s is the complex frequency, and _CGS is the gate and source of the third NMOS transistor MN3_A1 R _S is the resistance value of the gate resistor of the third NMOS transistor MN3_A1, and R _S =R _{RS1_A1} , R _{RS1_A1} is the resistance value of the resistor RS1_A1, so a reasonable adjustment of the resistance value of the resistor R _{S1_A1} is Active inductance can be realized and the working frequency band of the first amplifier A1 can be expanded.

Specific Embodiment 3: The present embodiment will be described below in conjunction with FIG. 4. This embodiment is a further description of Embodiment 1 or 2. The second amplifier A2 includes a seventh NMOS transistor MN1_A2, an eighth NMOS transistor MN2_A2, and a ninth NMOS transistor MN3_A2. , the second PMOS transistor MP1_A2, the third PMOS transistor MP2_A2, the resistor RL1_A2, the resistor RL2_A2, the resistor RC_A2, the capacitor CL1_A2 and the capacitor CL2_A2,

One end of the resistor RC_A2 is connected to the power supply VDD! , the other end of the resistor RC_A2 is connected to the source common terminals of the second PMOS transistor MP1_A2 and the third PMOS transistor MP2_A2,

The capacitor CL1_A2 is connected between the source and the gate of the second PMOS transistor MP1_A2, the resistor RL1_A2 is connected between the drain and the gate of the second PMOS transistor MP1_A2,

The capacitor CL2_A2 is connected between the source and the gate of the third PMOS transistor MP2_A2, the resistor RL2_A2 is connected between the drain and the gate of the third PMOS transistor MP2_A2,

The drain of the second PMOS transistor MP1_A2 and the drain of the seventh NMOS transistor MN1_A2 are connected to the common terminal as the non-inverting output terminal VOP of the second amplifier A2, and the gate of the seventh NMOS transistor MN1_A2 is used as the inverting input terminal VIN2 of the second amplifier A2 ;

The drain of the third PMOS transistor MP2_A2 and the drain of the eighth NMOS transistor MN2_A2 are connected to a common terminal as the inverting output terminal VON of the second amplifier A2, and the gate of the eighth NMOS transistor MN2_A2 is used as the non-inverting input terminal VIP2 of the second amplifier A2 ;

The source of the seventh NMOS transistor MN1_A2 is connected to the source of the eighth NMOS transistor MN2_A2, and the source of the seventh NMOS transistor MN1_A2 is also connected to the drain of the ninth NMOS transistor MN3_A2,

The gate of the ninth NMOS transistor MN3_A2 serves as the tail current bias voltage input terminal of the second amplifier A2;

The source of the ninth NMOS transistor MN3_A2 is connected to GND! .

In Fig. 4, the gate of the ninth NMOS transistor MN3_A2 is driven by the bias voltage VB3, which determines the tail current of the second amplifier A2, and the seventh NMOS transistor MN1_A2 and the eighth NMOS transistor MN2_A2 form a differential pair of transistors of the second amplifier A2 , the gate of the seventh NMOS transistor MN1_A2 serves as the inverting input terminal VIN2 of the second amplifier A2, the drain of the seventh NMOS transistor MN1_A2 serves as the non-inverting output terminal VOP of the second amplifier A2, and the gate of the eighth NMOS transistor MN2_A2 serves as the first The non-inverting input terminal VIP2 of the second amplifier A2 and the drain of the eighth NMOS transistor MN2_A2 serve as the inverting output terminal VON of the second amplifier A2.

The second PMOS transistor MP1_A2, resistor RL1_A2 and capacitor CL1_A2 form an active inductance of the second amplifier A2, and the third PMOS transistor MP2_A2, resistor RL2_A2 and capacitor CL2_A2 form another active inductance of the second amplifier A2. The basic principle is as follows. From the drain of the second PMOS transistor MP1_A1, the equivalent impedance after considering the transconductance of the transistor can be expressed as

${\mathrm{<span\; class="notranslate">\; Z</span>}}_{\mathrm{<span\; class="notranslate">\; out</span>}}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; *</span>{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; CL</span>}\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; \_</span>\mathrm{<span\; class="notranslate">\; A</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; *</span>{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; RL</span>}\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; \_</span>\mathrm{<span\; class="notranslate">\; A</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}}{{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; *</span>{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; CL</span>}\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; \_</span>\mathrm{<span\; class="notranslate">\; A</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 3</span>}<span\; class="notranslate">\; )</span>$

In the formula, Z _out is viewed from the drain of the second PMOS transistor MP1_A2, considering the equivalent impedance of the transistor transconductance, the resistance RL1_A2 connected to the gate and the capacitance CL1_A2 connected to the gate, and g _m is the equivalent impedance of the second PMOS transistor The transconductance of MP1_A2, C _{CL1_A2} is the capacitance value of capacitor CL1_A2, R _{RL1_A2} is the resistance value of resistor RL1_A2, and S is the complex frequency.

Therefore, reasonably adjusting the resistance value of the resistor RL1_A2 and the capacitance value of the capacitor CL1_A2 can significantly expand the bandwidth of the second amplifier A2, thereby realizing the bandwidth expansion function of the phase splitting circuit.

Claims (3)

1. The high-speed phase splitting circuit with frequency band extension function is characterized in that it includes the first PMOS transistor M1, resistor R1, resistor R2, phase splitting amplifier and integrator, The phase splitting amplifier is composed of the first amplifier A1 and the second amplifier A2 cascaded, The integrator is composed of a third amplifier A3, a resistor R3, a resistor R4 and a capacitor C1, One end of the resistor R1 is connected to the power supply VDD! , the other end of the resistor R1 is simultaneously connected to the source of the first PMOS transistor M1 and the non-inverting input terminal VIP of the first amplifier A1, the gate of the first PMOS transistor M1 is used as the receiving end of the transimpedance amplifier output signal VO_TIA, and the first PMOS transistor M1 The drain is connected to one end of resistor R2, and the other end of resistor R2 is connected to GND! ; The inverting input terminal VIN of the first amplifier A1 is connected to the output terminal VCM of the third amplifier A3, The inverting output terminal VON of the second amplifier A2 is connected to one end of the resistor R4, and the other end of the resistor R4 is connected to the non-inverting input terminal of the third amplifier A3, The non-inverting output terminal VOP of the second amplifier A2 is connected to one end of the resistor R3, and the other end of the resistor R3 is connected to the inverting input terminal of the third amplifier A3, The capacitor C1 is connected between the inverting input terminal and the output terminal of the third amplifier A3. 2. The high-speed phase splitting circuit with frequency band extension function according to claim 1, wherein the first amplifier A1 comprises a first NMOS transistor MN1_A1, a second NMOS transistor MN2_A1, a third NMOS transistor MN3_A1, and a fourth NMOS transistor MN4_A1 , the fifth NMOS transistor MN5_A1, the sixth NMOS transistor MN6_A1, the resistor RB_A1, the resistor RS1_A1, the resistor RS2_A1 and the resistor RCM_A1, One end of the resistor RB_A1 is connected to the power supply VDD! , the other end of the resistor RB_A1 is connected to the common terminal of the gate of the sixth NMOS transistor MN6_A1 and its drain, and the source of the sixth NMOS transistor MN6_A1 is connected to GND! ; One end of the resistor RCM_A1 is connected to the power supply VDD! , the other end of the resistor RCM_A1 is connected to the drain common end of the third NMOS transistor MN3_A1 and the fourth NMOS transistor MN4_A1; The gate of the third NMOS transistor MN3_A1 is connected to one end of the resistor RS1_A1, and the other end of the resistor RS1_A1 is connected to the other end of the resistor RB_A1; The source of the third NMOS transistor MN3_A1 and the drain of the first NMOS transistor MN1_A1 are connected to the common terminal as the non-inverting output terminal VOP1 of the first amplifier A1; the gate of the first NMOS transistor MN1_A1 is used as the inverting input terminal VIN of the first amplifier A1 , the source common terminal of the first NMOS transistor MN1_A1 and the second NMOS transistor MN2_A1 is connected to the drain of the fifth NMOS transistor MN5_A1, the gate of the fifth NMOS transistor MN5_A1 is used as the input terminal of the tail current bias voltage of the first amplifier A1, and the fifth The source of the NMOS transistor MN5_A1 is connected to GND! ; The common end connected to the drain of the second NMOS transistor MN2_A1 and the source of the fourth NMOS transistor MN4_A1 is used as the inverting output terminal VON1 of the first amplifier A1, and the gate of the second NMOS transistor MN2_A1 is used as the non-inverting input of the first amplifier A1 Terminal VIP; The gate of the fourth NMOS transistor MN4_A1 is connected to one end of the resistor RS2_A1, and the other end of the resistor RS2_A1 is connected to the other end of the resistor RB_A1. 3. The high-speed phase splitting circuit with frequency band extension function according to claim 1 or 2, wherein the second amplifier A2 comprises a seventh NMOS transistor MN1_A2, an eighth NMOS transistor MN2_A2, a ninth NMOS transistor MN3_A2, a second PMOS transistor MP1_A2, third PMOS transistor MP2_A2, resistor RL1_A2, resistor RL2_A2, resistor RC_A2, capacitor CL1_A2 and capacitor CL2_A2, One end of the resistor RC_A2 is connected to the power supply VDD! , the other end of the resistor RC_A2 is connected to the source common terminals of the second PMOS transistor MP1_A2 and the third PMOS transistor MP2_A2, The capacitor CL1_A2 is connected between the source and the gate of the second PMOS transistor MP1_A2, the resistor RL1_A2 is connected between the drain and the gate of the second PMOS transistor MP1_A2, The capacitor CL2_A2 is connected between the source and the gate of the third PMOS transistor MP2_A2, the resistor RL2_A2 is connected between the drain and the gate of the third PMOS transistor MP2_A2, The drain of the second PMOS transistor MP1_A2 and the drain of the seventh NMOS transistor MN1_A2 are connected to the common terminal as the non-inverting output terminal VOP of the second amplifier A2, and the gate of the seventh NMOS transistor MN1_A2 is used as the inverting input terminal VIN2 of the second amplifier A2 ; The drain of the third PMOS transistor MP2_A2 and the drain of the eighth NMOS transistor MN2_A2 are connected to a common terminal as the inverting output terminal VON of the second amplifier A2, and the gate of the eighth NMOS transistor MN2_A2 is used as the non-inverting input terminal VIP2 of the second amplifier A2 ; The source of the seventh NMOS transistor MN1_A2 is connected to the source of the eighth NMOS transistor MN2_A2, and the source of the seventh NMOS transistor MN1_A2 is also connected to the drain of the ninth NMOS transistor MN3_A2, The gate of the ninth NMOS transistor MN3_A2 serves as the tail current bias voltage input terminal of the second amplifier A2; The source of the ninth NMOS transistor MN3_A2 is connected to GND! . the

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