CN202976857U - Electronic programmable fuse circuit - Google Patents

Abstract

The utility model discloses an electronic programmable fuse circuit. In the electronic programmable fuse circuit, the circuit unit only includes a fuse unit and a first thin oxygen MOS tube, and each row of circuit units shares a thick oxygen MOS tube. , compared with the prior art, the number of thick oxygen MOS tubes is greatly reduced, and the problem of occupying circuit area caused by the use of thick oxygen MOS tubes for each circuit unit in the prior art is solved.

Description

An electronic programmable fuse circuit

technical field

The utility model relates to the field of circuit protection, in particular to an electronic programmable fuse circuit.

Background technique

Electronically programmable fuse (Electrically programmable Fuse, E-fuse) is a fuse that is often used in redundant circuits to improve chip failure. It is usually called a polysilicon fuse. It is located on two electrodes A short span of minimum width polysilicon.

The E-fuse circuit is based on the principle of electromigration. When there is no current flowing, the resistance of the fuse (fuse) is very small; when there is a large enough current flowing, the relevant atoms will migrate along the direction of electron movement and form holes. , resulting in a short circuit of the fuse, at this time, the fuse is equivalent to a large resistor.

When the chip fails, the E-fuse circuit in the chip can repair the defect of the chip. When the chip runs incorrectly, the E-fuse circuit realizes the automatic correction of the chip. The E-fuse circuit controls the writing logic through the corresponding circuit and signal. 0 or logic 1, and read out through the amplifier, used to replace the corresponding failure part of the chip to complete the operation of inputting logic 0 or logic 1.

The E-fuse circuit is composed of multiple circuit units, and the circuit unit is taken as an example for illustration. The structure of the existing circuit unit is shown in Figure 1, where N1 is a thick oxygen MOS tube, N0 is a thin oxygen MOS tube, The read operation signal of the control circuit at the RWL end, the write operation signal of the control circuit at the WWL end, the input signal of the fuse fuse at the FS end, and the drain of the thick oxygen MOS transistor N1 is used to connect to the amplifier, and the data written to the Q point is written to the Q point through the amplifier. Logic value readout; Q point is the initial value before the circuit works normally, and the initial value can be defined as logic 0 or logic 1 by the designer.

When the RWL terminal is connected to a high level, the thick oxygen MOS transistor N1 is turned on, and the amplifier reads the logic 1 of the Q point;

When the WWL terminal is connected to a high level, the RWL terminal is connected to a low level, and the FS terminal is connected to a programming voltage, the thin oxygen MOS transistor N0 is turned on, and the thick oxygen MOS transistor N1 is turned off, so that there is a large current passing through both ends of the fuse. Cause the short circuit of the fuse fuse. At this time, the fuse fuse is equivalent to a large resistance, and the Q point is grounded, and logic 0 can be written into the Q point; when the WWL terminal is connected to a low level, the RWL terminal is connected to a high level, and the FS terminal is grounded. , the thick oxygen MOS transistor N1 is turned on, and the amplifier reads out the logic 0 at point Q.

The E-fuse circuit array with n rows and m columns composed of the circuit units shown in Figure 1 is shown in Figure 2. In the E-fuse circuit composed of circuit units, since the circuit units all use thick oxygen MOS tubes, it takes up a lot of space. The area of the E-fuse circuit.

Utility model content

In view of this, the utility model provides an electronic programmable fuse circuit, which is used to solve the problem in the prior art that each circuit unit in the E-fuse circuit uses a thick oxygen MOS tube and occupies the area of the E-fuse circuit.

In order to achieve the above object, the utility model provides the following technical solutions:

An electronic programmable fuse circuit, including an array unit and m thick oxygen MOS transistors; wherein:

The array unit includes n×m circuit units, the circuit unit includes a fuse unit and a first thin oxide MOS transistor, and the first end of the fuse unit is connected to the drain of the first thin oxide MOS transistor ;

The second terminal of the fuse unit in each row of circuit units in the array unit is connected to the first voltage generating terminal; the source of the first thin-oxygen MOS transistor in each row of circuit units is connected to the drain of a thick-oxygen MOS transistor ; The gate of the first thin oxide MOS transistor in each row of circuit units in the array unit is connected to a first level emitter;

The sources of the m thick-oxygen MOS transistors are all grounded, and the gate of each thick-oxygen MOS transistor is connected to a second-level emitter; wherein, n and m are both positive integers.

Preferably, both the first thin oxygen MOS transistor and the thick oxygen MOS transistor are N-channel MOS transistors.

Preferably, each column of circuit units in the array unit further includes a reference resistor, a second MOS transistor, a third MOS transistor, and a fourth MOS transistor, wherein:

The first end of the reference resistor is connected to the second voltage generating end;

The source of the first thin oxide MOS transistor in each row of circuit units is connected to the drain of the fourth MOS transistor;

The second end of the reference resistor is connected to the drain of the second MOS transistor;

The source of the second MOS transistor is connected to the drain of the third MOS transistor, and the gate of the second MOS transistor is connected to a third level emitter;

The gate of the third MOS transistor is connected to the gate of the fourth MOS transistor, and the source is grounded;

The source of the fourth MOS transistor is grounded;

The gate of the third MOS transistor is connected to the source of the second MOS transistor to form a first signal terminal.

Preferably, the first thin oxide MOS transistor and the second MOS transistor are N-channel MOS transistors.

Preferably, the third MOS transistor and the fourth MOS transistor are N-channel MOS transistors.

Preferably, each column of circuit units in the array unit is provided with an amplifier; the first end of the amplifier is connected to the drain of the fourth MOS transistor, and the second end of the amplifier is connected to the first signal end connected; the amplifier includes a first inverter, a second inverter, a first transmission gate, a second transmission gate and a fifth MOS transistor, wherein:

Both the first terminal of the first inverter and the first terminal of the second inverter are connected to a power supply voltage;

Both the second end of the first inverter and the second end of the second inverter are connected to the drain of the fifth MOS transistor;

The gate of the fifth MOS transistor is connected to the fourth level transmitter, and the source of the fifth MOS transistor is grounded;

The third terminal of the first inverter is connected to the fourth terminal of the second inverter, and the third terminal of the second inverter is connected to the fourth terminal of the first inverter;

The input terminal of the first transmission gate is the first terminal of the amplifier, the output terminal is connected to the third terminal of the first inverter, the first control terminal is connected to the fourth level transmitting terminal, and the second control terminal is connected to the fourth level transmitting terminal. The terminal is connected to the fifth level transmitting terminal;

The input end of the second transmission gate is the second end of the amplifier, the output end is connected to the third end of the second inverter, the first control end is connected to the fourth level transmitting end, and the second control end is connected to the third end of the second inverter. The terminal is connected to the fifth level transmitting terminal.

Preferably, the first inverter includes a sixth PMOS transistor and a seventh NMOS transistor, wherein:

The drain of the sixth PMOS transistor is the first terminal of the first inverter, the source is connected to the drain of the seventh NMOS transistor and is the third terminal of the first inverter, and the gate After being connected to the gate of the seventh NMOS transistor, it is the fourth end of the first inverter; the source of the seventh NMOS transistor is the second end of the first inverter;

The second inverter includes a sixth PMOS transistor and a seventh NMOS transistor, wherein:

The drain of the sixth PMOS transistor is the first end of the second inverter, the source is connected to the drain of the seventh NMOS transistor and is the third end of the second inverter, and the gate The fourth end of the second inverter is connected to the gate of the seventh NMOS transistor; the source of the seventh NMOS transistor is the second end of the second inverter.

It can be seen from the above technical solutions that, compared with the prior art, the utility model discloses an electronic programmable fuse circuit, in which the circuit unit only includes a fuse unit and a first thin Oxygen MOS tubes, each column of circuit units share a thick oxygen MOS tube, compared with the existing technology, greatly reduces the number of thick oxygen MOS tubes, and solves the problem that each circuit unit needs to use thick oxygen MOS tubes in the prior art The problem of occupying the circuit area caused by the MOS tube.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the accompanying drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description It is only an embodiment of the utility model, and those skilled in the art can also obtain other drawings according to the provided drawings without creative work.

Fig. 1 is the circuit structural diagram of the circuit unit of electronic programmable fuse circuit in the prior art;

FIG. 2 is a circuit structure diagram of an electronic programmable fuse circuit array in the prior art;

Fig. 3 is a circuit structure diagram of a circuit unit of an electronic programmable fuse circuit of the present invention;

Fig. 4 is a structural diagram of an embodiment of an electronic programmable fuse circuit of the present invention;

5 is a circuit structure diagram of another embodiment of an electronic programmable fuse circuit of the present invention;

FIG. 6 is a circuit structure diagram of an amplifier of an electronic programmable fuse circuit of the present invention.

Detailed ways

The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. example. Based on the embodiments of the present utility model, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the scope of protection of the present utility model.

For the sake of reference and clarity, the technical terms used in the following description are abbreviated as follows:

E-fuse: Electrically programmable Fuse, electronically programmable fuse;

MOS: Metal Oxide Semiconductor, Metal Oxide Semiconductor Field Effect Transistor;

PMOS: Positive channel Metal Oxide Semiconductor, P-channel Metal Oxide Semiconductor Field Effect Transistor;

NMOS: Negative channel Metal Oxide Semiconductor, N-channel Metal Oxide Semiconductor;

NBTI: Negative Bias Temperature Instability, negative bias temperature instability.

Referring to FIG. 3 , it shows a structural diagram of a circuit unit of an E-fuse circuit of the present invention.

The circuit unit of the E-fuse circuit may include a fuse unit fuse and a first thin oxygen MOS transistor N0;

The work of the E-fuse circuit unit is based on the principle of electromigration. When there is no current flowing, the resistance of the fuse is very small; when there is a large enough current flowing, the relevant atoms will migrate along the direction of electron movement to form holes. Cause the fuse short circuit, at this time, the fuse is equivalent to a large resistance.

The first end of the fuse unit fuse is connected to the drain of the first thin oxide MOS transistor N0;

Referring to Fig. 4, it shows a circuit structure diagram of an E-fuse circuit of the present invention.

The E-fuse circuit may include an array unit 401 and m thick oxygen MOS transistors N1;

3 and 4, the array unit 401 includes n×m circuit units, the circuit unit includes a fuse unit fuse and a first thin oxide MOS transistor N0, the first end of the fuse unit fuse is connected to the The drain of the first thin oxygen MOS transistor N0 is connected;

Wherein, n and m are both positive integers;

The n×m circuit units correspond to n rows and m columns, each row has m circuit units, and each column has n circuit units;

The second terminal of the fuse unit fuse in each column of circuit units in the array unit 401 is connected to the first voltage generating terminal FS ₀ , and the m column circuit units share a first voltage generating terminal FS ₀ ;

The source of the first thin-oxygen MOS transistor N0 in each column of circuit units is connected to the drain of a thick-oxygen MOS transistor N1, that is, the sources of n first thin-oxygen MOS transistors N0 in each column are connected to a thick-oxygen MOS transistor N1. The drain of the tube N1 is connected;

The gate of the first thin oxide MOS transistor N0 in each row of circuit units in the array unit 401 is connected to a first level transmitter, that is, n rows of circuit units are respectively connected to n first level transmitters, that is, WWL ₀ ~WWLn _-1 ;

The sources of the m thick oxygen MOS transistors N0 are all grounded, the gate of each thick oxygen MOS transistor is connected to a second level transmitter, and the gates of the m thick oxygen MOS transistors are connected to m second level emitters terminal, that is, BS ₀ ~BS _m-1 .

Wherein, the array unit has m columns, and each column has n circuit units, and the circuit units in the m columns are all connected to the first voltage generating terminal FS ₀ ; specifically, the n fuse units in the circuit units of the first column are The second terminals of the two terminals are all connected to the first voltage generating terminal FS ₀ , and the sources of the n first thin-oxygen MOS transistors N0 in the first column of circuit units are all connected to the drain of the first thick-oxygen MOS transistor N1. The connection point is Q ₀ point; the second end of the n fuse units fuse in the second column of the circuit unit is connected to the first voltage generating terminal FS ₀ , and the n first thin oxide MOS transistors in the second column of the circuit unit The source of N0 is connected to the drain of the second thick-oxygen MOS transistor N1, and its connection point is _Q1 point; and so on, the second end of the n fuse unit fuse in the m-th column of the circuit unit is connected to To the first voltage generating terminal FS ₀ , the sources of the n first thin-oxygen MOS transistors N0 in the m-th column of circuit units are all connected to the drains of the m-th thick-oxygen MOS transistor N1, and the connection point is Q _{m- 1} point;

The array unit has n rows, corresponding to n first-level transmitters, and each row has m circuit units; specifically, the gates of the m first thin-oxide MOS transistors in the first row of circuit units are connected to to the first level emitter WWL ₀ , the gates of the m first thin oxide MOS transistors in the circuit unit in the second row are connected to the first level emitter WWL ₁ , and so on, the circuit unit in the nth row The gate of the first thin oxide MOS transistor is connected to the first level emitter WWL _n-1 ;

m columns of circuit units correspond to m thick-oxygen MOS transistors and m second-level emitters, and the gate of each thick-oxygen MOS transistor is connected to a second-level emitter; specifically, the first thick-oxygen MOS transistor The gate is connected to the second level emitter BS ₀ , the gate of the second thick oxygen MOS transistor is connected to the second level emitter BS ₁ , and so on, the gate of the mth thick oxygen MOS transistor It is connected with the second level transmitter BS _m-1 .

Wherein, the first voltage generating terminal can provide programming voltage or power supply voltage for the E-fuse circuit, and the first level transmitting terminal and the second level transmitting terminal can provide high power for the E-fuse circuit flat or low level.

Wherein, the first thin oxygen MOS transistor and the thick oxygen MOS transistor may be N-channel MOS transistors.

In this embodiment, the E-fuse circuit includes an array unit and m thick oxygen MOS transistors, the array unit includes n×m circuit units, and each E-fuse circuit unit includes a fuse (fuse) unit and a first A thin oxygen MOS tube, by connecting n circuit units in each column with a thick oxygen MOS tube, compared with the prior art, greatly reduces the number of thick oxygen MOS tubes, and solves the problems in the prior art Each circuit unit needs to use a thick oxygen MOS tube, which leads to the problem of occupying the circuit area.

The E-fuse circuit can be applied in a redundant circuit. When the chip fails, it can replace the corresponding failed part of the chip circuit, and the decoder can generate different control signals to control the first voltage generating terminal and the first level transmitting terminal. And the second level transmitter, so that the E-fuse circuit can sequentially write logic 0 or logic 1 into the corresponding Q ₀ ~ Q _m-1 point, and finally read and store it through the amplifier to replace the corresponding failure part of the chip The circuit completes the input logic 0 or logic 1 operation.

Wherein, the values of points Q ₀ to Q _m-1 in the E-fuse circuit can be set as initial values, and the initial values can be defined as logic 0 or logic 1 by the designer.

In this embodiment, the initial value of points Q ₀ to Q _m-1 is illustrated as logic 1. Since the initial value is set to be logic 1, when the E-fuse circuit needs to write logic 1, it is not necessary to The circuit unit in the E-fuse circuit is programmed, and when the E-fuse circuit needs to write logic 0, the circuit unit in the E-fuse circuit needs to be programmed earlier;

Specifically, the E-fuse circuit generates memory cells that need to be programmed through the decoder, that is, generates circuit cells that need to be programmed, and generates different control signals through the decoder to control the corresponding first voltage generating terminal, first level transmitting terminal and The second level transmitting end, by programming the circuit units in the array unit, writes logic 0 into the corresponding Q ₀ ~Q _m-1 points, which can be finally read by the amplifier.

Take the programming operation of the circuit unit in the first row and the first column in the circuit array as an example: when the first voltage generating terminal FS ₀ is the programming voltage VDQ, the first level transmitting terminal WWL ₀ and the second level When the transmitting terminal BS ₀ is at high level, the other terminals can keep low level, then the first thin oxygen MOS transistor N0 in the first row and the first column is turned on, and the thick oxygen MOS transistor N1 in the first column is turned on, and the first The circuit unit in the first column of the row writes logic 0 into point Q ₀ ;

When the first voltage generating terminal FS ₀ is the power supply voltage VDD, the signal terminal of the first level transmitting terminal WWL ₀ is at a high level, the second level transmitting terminal BS ₀ is at a low level, and the other terminals are kept at a low level , then the first thin oxygen MOS transistor N0 in the first row and the first column is turned on, and the thick oxygen MOS transistor N1 in the first column is turned off, and the circuit unit in the first row and the first column can be written into the logic of point _Q0 through the amplifier A value of 0 is read.

Correspondingly, if the E-fuse circuit unit in the nth row and the mth column of the array unit performs a programming operation and writes logic 0, when the first voltage generating terminal _FS0 is connected to the programming voltage VDQ, the first level emits When the terminal WWL _n-1 and the second level transmitting terminal BS _m-1 are at a high level, and the other terminals can be kept at a low level, then the first thin oxide MOS transistor N0 in the nth row and the mth column is turned on, and the second Thick oxygen MOS transistor N1 in column m is turned on, and the E-fuse circuit unit in row n and column m writes logic 0 into point Q _m-1 ;

When the first voltage generating terminal FS _m-1 is connected to the power supply voltage VDD, the first level transmitting terminal WWL _n-1 is at a high level, the second level transmitting terminal BS _m-1 is at a low level, and the other terminals are Keep the low level, then the first thin oxygen MOS transistor N0 in the nth row and mth column is turned on, and the thick oxygen MOS transistor N1 in the mth column is turned off, and the circuit unit in the nth row and mth column is written into Q _m through the amplifier A logical value of 0 at _-1 point is read out.

Wherein, the E-fuse circuit can realize the programming operation of the circuit units in the E-fuse circuit in the manner described above, which will not be repeated here.

It should be noted that the E-fuse circuit can only be programmed one bit at a time, that is, only one E-fuse circuit unit writes the logic value to the corresponding Q ₀ ~Q _m-1 points at a time, and the E-fuse The circuit generates different control signals through the decoder. The first level transmitter, the second level transmitter and the first voltage generator are controlled by the control signal, and the E-fuse circuit sequentially writes the data that each circuit unit needs to write. Logical value, realizing one-by-one programming.

In this embodiment, the operation of writing logic 1 or logic 0 into the corresponding Q ₀ ~Q _m-1 points is realized by sharing the same thick oxygen MOS transistor with each row of E-fuse circuit units, which greatly saves the E-fuse the area of the circuit.

After the E-fuse circuit unit writes the corresponding logic values into the corresponding Q ₀ ~Q _m-1 points, it can be read by the amplifier, and the logic value stored in the circuit unit can be judged through the current mirror structure, namely Judging the logic value written into Q ₀ ~Q _m-1 points, the current mirror structure is realized by setting a reference resistor and a MOS transistor in the array unit of the E-fuse circuit;

Referring to Fig. 5, the circuit structural diagram of another embodiment of a kind of E-fuse circuit of the present invention is shown;

Each column of circuit units in the m columns of circuit units of the E-fuse circuit also includes a reference resistor R1, a second MOS transistor N2, a third MOS transistor N3, and a fourth MOS transistor N4;

It should be noted that when the fuse unit fuse in the circuit unit is not programmed, the resistance value is small, generally 150 ohms; after programming, the resistance becomes larger, generally 2000 ohms.

The resistance value of the reference resistor is generally between the resistance value of the fuse unit before programming and the resistance value after programming. According to the above description, the resistance value of the reference resistor is generally located at 150 ohms Between ~2000 ohms.

The first terminal of the reference resistor R1 is connected to the second voltage generating terminal _FS1 ;

Wherein, when the amplifier is performing a read operation, the second voltage generating terminal FS ₁ is the power supply voltage VDD, and when the amplifier is not performing a reading operation, the second voltage generating terminal FS ₁ is grounded.

The source of the first thin oxide MOS transistor N1 in each column of circuit units is connected to the drain of the fourth MOS transistor N4;

The second end of the reference resistor R1 is connected to the drain of the second MOS transistor N2;

The source of the second MOS transistor N2 is connected to the drain of the third MOS transistor N3, and the gate of the second MOS transistor N2 is connected to the third level transmitter wwl;

Wherein, the gates of the second MOS transistors N2 of each column of circuit units are connected to the third level transmitting terminal wwl, and the gates of the second MOS transistors N2 of the m columns of circuit units share a third level transmitting terminal wwl; specifically The gate of the second MOS transistor N2 in the first column is connected to the third-level emission terminal wwl; the gate of the second MOS transistor N2 in the second column is connected to the third-level emission terminal wwl, and so on, The gate of the second MOS transistor N2 in the mth column is connected to the third level emitting terminal wwl.

The gate of the third MOS transistor N3 is connected to the gate of the fourth MOS transistor N4, and the source is grounded;

The source of the fourth MOS transistor N4 is grounded;

The gate of the third MOS transistor N3 is connected to the source of the second MOS transistor N2 to form a first signal terminal;

Wherein the first thin oxide MOS transistor N0 and the second MOS transistor N2 are the same N-channel MOS transistor;

Wherein the third thin oxide MOS transistor N3 and the fourth MOS transistor N4 are the same N-channel MOS transistor.

Wherein, m columns of circuit units can form m first signal terminals; specifically, the gate of the third MOS transistor N3 in the first column of circuit units is connected to the source of the second MOS transistor N2 to form the first A signal terminal RBL ₀ , and so on, the gate of the third MOS transistor N3 in the mth column of circuit units is connected to the source of the second MOS transistor N2 to form a first signal terminal RBL _m-1 .

Wherein, each row of circuit units of the E-fuse circuit includes a reference resistor R1, a second MOS transistor N2, a third MOS transistor N3, and a fourth MOS transistor N4, and each row of circuit units is connected to the reference resistor R1, the second MOS transistor The connection methods of N2, the third MOS transistor N3, and the fourth MOS transistor N4 are all shown in the above connection methods, and will not be repeated here.

When it is necessary to read the logic value written into points Q ₀ ~Q _m-1 through the amplifier, the voltage value of points Q ₀ ~Q _m-1 and the corresponding points RBL ₀ ~RBL _m-1 can be compared to determine the corresponding Whether the circuit unit is programmed;

When the amplifier reads the E-fuse circuit, the first voltage generating terminal FS ₀ is the power supply voltage VDD, the second voltage generating terminal FS ₁ is the power supply voltage VDD, and the second level emission Terminals BS ₀ ~ BS _m-1 are all low level, the third level transmitting terminal wwl is high level, and the corresponding first level transmitting terminal is high level;

Specifically, when the first level transmitting terminal WWL ₀ is at a high level, it can be judged by comparing the voltage value of points Q ₀ ~Q _m-1 with the corresponding voltage values of points RBL ₀ ~RBL _m-1 . Whether the circuit cells in the first row of the array cells are programmed, so as to determine whether the logic value written to points Q ₀ -Q _m-1 by the circuit cells in the first row is 1 or logic 0.

By analogy, when the first level transmitting terminal WWL _n-1 is at a high level, by comparing the voltage value of points Q ₀ ~Q _m-1 with the corresponding voltage values of points RBL ₀ ~RBL _m-1 , Judging whether the circuit cells in the nth row of the array cells are programmed, so as to determine whether the logic value written to points Q ₀ -Q _m−1 through the nth row of circuit cells is 1 or logic 0.

Taking point Q ₀ of the E-fuse circuit as an example, when the first level generating terminal WWL ₀ is at a high level, the amplifier is reading the logic value of Q ₀ , and the voltage value at point Q ₀ and RBL ₀ can be compared , so as to know the resistance value of the fuse unit fuse in the first row and the first column and the resistance value of the reference resistor R1, judge whether the circuit unit in the first row and the first column is programmed, and determine whether the circuit unit passed the first row and the first column The circuit unit writes the logic value of Q ₀ point is 1 or logic 0;

It should be noted that when it is necessary to determine whether a certain circuit unit of the array unit is programmed, as described above, the voltage value at points Q ₀ ~Q _m-1 can be compared with the corresponding RBL ₀ ~RBL _m The voltage value of _-1 point is enough, so I won’t go into details here.

Each column of circuit units is provided with a reference resistor R1, a second MOS transistor N2, a third MOS transistor N3, and a fourth MOS transistor N4. By controlling the corresponding first voltage generating terminal, the second voltage generating terminal, and the first level Transmitter, second-level transmitter and third-level transmitter to compare the voltage values of Q ₀ ~Q _m-1 points and the corresponding RBL ₀ ~RBL _m-1 points, and the corresponding fuse unit can be determined Resistance value, and then judge whether the corresponding circuit unit is programmed;

In this embodiment, when the amplifier reads out the logic value located at points Q ₀ ~Q _m-1 , the first end of the reference resistor can be connected to the power supply voltage, which can ensure that the points Q ₀ ~Q _m-1 and the phase The corresponding RBL ₀ ~ RBL _m-1 point has enough voltage difference to accurately judge whether the corresponding circuit unit is programmed.

The logic values of points Q ₀ to Q _m-1 of the E-fuse resistors can be read out by corresponding amplifiers and stored, so as to complete the operation of inputting logic 0 or logic 1 instead of the chip.

Wherein, the logic value of the E-fuse circuit can be read by the amplifier, which is used to replace the input logic 0 or logic 1 of the corresponding failure part circuit of the chip, and the circuit structure of the amplifier is not specifically limited, wherein, as an embodiment ,As shown in Figure 6;

Referring to FIG. 6 , it shows a circuit structure diagram of an amplifier of an E-fuse circuit of the present invention.

The E-fuse circuit also includes m amplifiers, each row of circuit units in the array unit 401 is provided with an amplifier, the first end of the amplifier is connected to the drain of the fourth MOS transistor, and the amplifier's The second terminal is connected to the first signal terminal;

Wherein, the amplifier in the first column is connected to the first signal terminal RBL ₀ , the amplifier in the second column is connected to the first signal terminal RBL ₁ , and so on, the amplifier in the mth column is connected to the first signal terminal RBL _m-1 ;

The amplifier includes a first inverter 601, a second inverter 602, a first transmission gate G1, a second transmission gate G2 and a fifth MOS transistor N5, wherein:

Both the first terminal of the first inverter 601 and the first terminal of the second inverter 602 are connected to the power supply voltage VDD;

Both the second end of the first inverter 601 and the second end of the second inverter 602 are connected to the drain of the fifth MOS transistor N5;

The gate of the fifth MOS transistor N5 is connected to the fourth level transmitter SAEN, and the source of the fifth MOS transistor N5 is grounded;

The third terminal of the first inverter 601 is connected to the fourth terminal of the second inverter 602, and the third terminal of the second inverter 602 is connected to the fourth terminal of the first inverter 601. four-terminal connection;

The input end of the first transmission gate G1 is the first end of the amplifier, the output end is connected to the third end of the first inverter 601, and its connection point is set as point L, and the first control end is connected to the third end of the first inverter 601. The four-level transmitting terminal SAEN is connected, and the second control terminal is connected to the fifth-level transmitting terminal SAEB;

The input terminal of the second transmission gate G2 is the second terminal of the amplifier, the output terminal is connected to the third terminal of the second inverter 602, and its connection point is set as the R terminal, and the first control terminal is connected to the second terminal. The four-level transmitting terminal SAEN is connected, and the second control terminal is connected to the fifth-level transmitting terminal SAEB.

Wherein, the gate of the PMOS transistor in the first transmission gate G1 is the first control terminal of the first transmission gate G1, and the gate of the NMOS transistor in the first transmission gate G1 is the first control terminal of the first transmission gate G1. the second control terminal.

The gate of the PMOS transistor in the second transmission gate G2 is the first control terminal of the second transmission gate G2, and the gate of the NMOS transistor in the second transmission gate G2 is the first control terminal of the second transmission gate G2. Two control terminals.

It should be noted that m columns correspond to m amplifiers, that is, each column is provided with an amplifier, and the connection mode between each amplifier and the corresponding circuit unit in each column is as shown in the above connection mode, and will not be described here one by one. repeat.

There are n rows and m columns of circuit units in the array unit, that is, m amplifiers are provided, and each column is provided with an amplifier;

Finally, the logic value of is read out through the amplifier and locked in the first inverter and the second inverter;

Wherein, the first inverter 601 includes a sixth PMOS transistor P6 and a seventh NMOS transistor N7, wherein: the drain of the sixth PMOS transistor N6 is the first terminal of the first inverter, and the source and The drain of the seventh MOS transistor N7 is connected to be the third terminal of the first inverter; the gate is connected to the gate of the seventh NMOS transistor N7 to be the third terminal of the first inverter. Four terminals, the source of the seventh NMOS transistor N7 is the second terminal of the first inverter;

The second inverter 602 includes a sixth PMOS transistor N6 and a seventh NMOS transistor N7, wherein: the drain of the sixth PMOS transistor N6 is the first terminal of the second inverter, and the source is connected to the The drain of the seventh MOS transistor N7 is connected to be the third terminal of the second inverter, and the gate is connected to the gate of the seventh NMOS transistor N7 to be the fourth terminal of the second inverter , the source of the seventh NMOS transistor N7 is the second terminal of the second inverter.

When the amplifier is performing a read operation, comparing the voltage values of points Q ₀ ~ Q _m-1 with the corresponding points RBL ₀ ~ RBL _m-1 can determine the resistance value of the corresponding fuse unit, and then determine the corresponding circuit unit Whether it is programmed or not, through the control of the fourth-level transmitter SAEN and the fifth-level transmitter SAEB, the voltage of points Q ₀ ~Q _m-1 and the first signal RBL ₀ ~RBL _m-1 can be written into point L and point R;

Take the logic value written into Q ₀ as an example, when the fourth-level transmitting terminal SAEN is at low level, and when the fifth-level transmitting terminal SAEB is at high level, the first transmission gate G1 and the second transmission gate G2 are opened , the voltages of Q ₀ and RBL ₀ can be written into the circuit nodes L and R through the first transfer gate G1 and the second transfer gate G2. When the circuit is stable, the fourth level transmitter SAEN becomes low level , the fifth level transmitting terminal SAEB becomes high level, at this time, the first transmission gate G1 and the second transmission gate G2 are closed, and the voltage values of point L and point R are stored in the amplifier, after the first reflection The phaser 601 and the second inverter 602 amplify the voltage. When the data is stable, the logic value can be read through the L point and the R point, which is used to replace the corresponding chip to complete the operation of inputting the corresponding logic 0 or logic 1. ;

It should be noted that the amplifiers in each column in the E-fuse circuit perform the operation of reading logic values in the manner described above, which will not be repeated here.

Each column of circuit units can be provided with an amplifier, which can write the voltages of points Q ₀ to Q _m-1 and the corresponding first signal terminals RBL ₀ to RBL _m-1 through the first transmission gate and the second transmission gate. Input the L point and R point, amplify the voltage through two inverters, and finally read the logic value through the L point and R point, which is used to replace the chip to complete the input of the corresponding logic 0 or logic 1.

In this embodiment, by cross-coupling two inverters, this structure enables the MOS transistor to still work normally under process fluctuations, reducing the NBTI effect.

Each embodiment in this specification is described in a progressive manner, each embodiment focuses on the difference from other embodiments, and the same and similar parts of each embodiment can be referred to each other.

The above description of the disclosed embodiments enables those skilled in the art to realize or use the utility model. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the present invention will not be limited to these embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims (7)

1. an electronic programmable fuse circuit, is characterized in that, comprises array element and m thick oxygen metal-oxide-semiconductor; Wherein:

Described array element comprises n * m circuit unit, and described circuit unit comprises fuse cell and the first thin oxygen metal-oxide-semiconductor, and the first end of described fuse cell is connected with the drain electrode of the described first thin oxygen metal-oxide-semiconductor;

The second end of the fuse cell in described array element in each column circuits unit connects the first voltage and holds; The source electrode of the first thin oxygen metal-oxide-semiconductor in each column circuits unit is connected with the drain electrode of a thick oxygen metal-oxide-semiconductor; The grid of the first thin oxygen metal-oxide-semiconductor in described array element in every a line circuit unit connects first a level transmitting terminal;

The source grounding of described m thick oxygen metal-oxide-semiconductor, the grid of each thick oxygen metal-oxide-semiconductor connects a second electrical level transmitting terminal; Wherein, n and m are positive integer.

2. circuit according to claim 1, is characterized in that, the described first thin oxygen metal-oxide-semiconductor and described thick oxygen metal-oxide-semiconductor are the N-channel MOS pipe.

3. circuit according to claim 1, is characterized in that, in described array element, each column circuits unit also comprises reference resistance, the second metal-oxide-semiconductor, the 3rd metal-oxide-semiconductor, the 4th metal-oxide-semiconductor, wherein:

The first end of described reference resistance connects second voltage and holds;

The source electrode of the first thin oxygen metal-oxide-semiconductor in each column circuits unit is connected with the drain electrode of described the 4th metal-oxide-semiconductor;

The second end of described reference resistance is connected with the drain electrode of described the second metal-oxide-semiconductor;

The source electrode of described the second metal-oxide-semiconductor is connected with the drain electrode of described the 3rd metal-oxide-semiconductor, and the grid of described the second metal-oxide-semiconductor connects the 3rd level transmitting terminal;

The grid of described the 3rd metal-oxide-semiconductor is connected with the grid of described the 4th metal-oxide-semiconductor, source ground;

The source ground of described the 4th metal-oxide-semiconductor;

The source electrode of the grid of described the 3rd metal-oxide-semiconductor and described the second metal-oxide-semiconductor is connected to form the first signal end.

4. circuit according to claim 3, is characterized in that, the described first thin oxygen metal-oxide-semiconductor and described the second metal-oxide-semiconductor are the N-channel MOS pipe.

5. circuit according to claim 3, is characterized in that, described the 3rd metal-oxide-semiconductor and described the 4th metal-oxide-semiconductor are the N-channel MOS pipe.

6. circuit according to claim 3, is characterized in that, also comprises m amplifier, and in described array element, each column circuits unit is provided with an amplifier; The first end of described amplifier is connected with the drain electrode of described the 4th metal-oxide-semiconductor, and the second end of described amplifier is connected with described first signal end; Described amplifier comprises the first phase inverter, the second phase inverter, the first transmission gate, the second transmission gate and the 5th metal-oxide-semiconductor, wherein:

The first end of described the first phase inverter all is connected with supply voltage with the first end of described the second phase inverter;

The second end of described the first phase inverter all is connected with the drain electrode of described the 5th metal-oxide-semiconductor with the second end of described the second phase inverter;

The grid of described the 5th metal-oxide-semiconductor is connected with the 4th level transmitting terminal, the source ground of described the 5th metal-oxide-semiconductor;

The 3rd end of described the first phase inverter is connected with the 4th end of described the second phase inverter, and the 3rd end of described the second phase inverter is connected with the 4th end of described the first phase inverter;

The first end that the input end of described the first transmission gate is described amplifier, output terminal is connected with the 3rd end of described the first phase inverter, and the first control end is connected with the 4th level transmitting terminal, and the second control end is connected with the 5th level transmitting terminal;

The second end that the input end of described the second transmission gate is described amplifier, output terminal is connected with the 3rd end of described the second phase inverter, and the first control end is connected with the 4th level transmitting terminal, and the second control end is connected with the 5th level transmitting terminal.

7. circuit according to claim 6, is characterized in that, described the first phase inverter comprises the 6th PMOS pipe and the 7th NMOS pipe, wherein:

The first end that the drain electrode of described the 6th PMOS pipe is described the first phase inverter, after source electrode is connected with the drain electrode of described the 7th NMOS pipe, being the 3rd end of described the first phase inverter, is the 4th end of described the first phase inverter after grid is connected with the grid of described the 7th NMOS pipe; The second end that the source electrode of described the 7th NMOS pipe is described the first phase inverter;

Described the second phase inverter comprises the 6th PMOS pipe and the 7th NMOS pipe, wherein:

The first end that the drain electrode of described the 6th PMOS pipe is described the second phase inverter, after source electrode is connected with the drain electrode of described the 7th NMOS pipe, being the 3rd end of described the second phase inverter, is the 4th end of described the second phase inverter after grid is connected with the grid of described the 7th NMOS pipe; The second end that the source electrode of described the 7th NMOS pipe is described the second phase inverter.

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