CN203434152U - Capacitor structure of panel integrated scanning drive circuit - Google Patents
Capacitor structure of panel integrated scanning drive circuit Download PDFInfo
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- CN203434152U CN203434152U CN201320208601.2U CN201320208601U CN203434152U CN 203434152 U CN203434152 U CN 203434152U CN 201320208601 U CN201320208601 U CN 201320208601U CN 203434152 U CN203434152 U CN 203434152U
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Abstract
The utility model discloses a capacitor structure of a panel integrated scanning drive circuit. The capacitor structure comprises a first metal layer, a first dielectric layer, a second metal layer, a second dielectric layer, a first transparent capacitance electrode layer and a second transparent capacitance electrode layer, wherein the first dielectric layer is covered on the first metal layer and includes a first opening, the second metal layer is located on the first dielectric layer and is connected with the first metal layer through the first opening, the second dielectric layer is covered on the second metal layer and includes a second opening which is located right above the first opening, the first transparent capacitance electrode layer is arranged on the first dielectric layer and is connected with the second metal layer, the second transparent capacitance electrode layer is located on the second dielectric layer and is connected with the first metal layer through the second opening, and the second transparent capacitance electrode layer and the first transparent capacitance electrode layer are stacked along a thickness direction and are opposite to each other with the second dielectric layer arranged therein.
Description
Technical field
The utility model relates to a kind of capacitance structure of panel integration scanning drive circuit.
Background technology
In order to reduce the cost of display floater, manufacturer directly does scan drive circuit on panel gradually, and does not need additionally to buy drain drives IC.This kind do not need the panel of drain drives IC to be referred to as GIP (Gate Driver In Panel) panel, i.e. panel integration scanning drive circuit.But for high-resolution display floater, the demand of the capacitance of scan drive circuit is higher.Thus, electric capacity by account in entire scan drive circuit area most, and the width of frame is increased, and is unfavorable for reaching the demand of narrow frame (narrow border).And general capacitance electrode is metal and light tight, splashes into processing procedure (One Drop Filling, ODF) and cannot apply liquid crystal.
Therefore, need a kind of capacitance structure of improvement, can shorten border width, and can be applicable to liquid crystal and splash into processing procedure, significantly to reduce processing procedure time and cost.
Summary of the invention
The purpose of this utility model is to provide a kind of capacitance structure of improvement, and it has multi-layer transparent capacitance electrode layer, and electric capacity to account for entire scan drive circuit area less, and can reach the demand of narrow frame.In addition,, because capacitance structure has certain light transmittance, the liquid crystal of can arranging in pairs or groups splashes into processing procedure, and can shorten processing procedure time and cost.
For achieving the above object, the utility model adopts following technical scheme:
A capacitance structure for panel integration scanning drive circuit, it comprises:
One the first metal layer;
One first dielectric layer, is covered on this first metal layer, and comprises one first opening, and this first opening exposes the part of this first metal layer;
One second metal level, is positioned on this first dielectric layer, and a part for this second metal level sees through this first opening and is connected with this first metal layer;
One second dielectric layer, is covered on this second metal level, and comprises one second opening, and this second opening is positioned at directly over this first opening, and exposes this part of this second metal level;
One first transparent capacitance electrode layer, is positioned on this first dielectric layer, and connects another part of this second metal level; And
One second transparent capacitance electrode layer, is positioned on this second dielectric layer, and connects this first metal layer through this second opening, wherein this second transparent capacitance electrode layer and this first transparent capacitance electrode layer through-thickness storehouse and relative across this second dielectric layer.
Capacitance structure described in the utility model, it also comprises one the 3rd transparent capacitance electrode layer and this first transparent capacitance electrode layer through-thickness storehouse and relative across this first dielectric layer, and connects this first metal layer.
Described the second metal level be positioned at this first transparent capacitance electrode layer above or below.
Described the first metal layer be positioned at the 3rd transparent capacitance electrode layer above or below.
Described the first metal layer and this second metal level are a pierced pattern, and this pierced pattern comprises box-shaped pattern or palisade pattern.
Described panel comprises a thin-film transistor, the drain electrode of this first metal layer and this thin-film transistor is made simultaneously, the source electrode of this second metal level and this thin-film transistor is made simultaneously, the transparency electrode of sharing of this second transparent capacitance electrode layer and this thin-film transistor is made simultaneously, and the pixel electrode of this first transparent capacitance electrode layer and this thin-film transistor is made simultaneously.
A capacitance structure for integration scanning drive circuit, it comprises:
One the first metal layer;
One first dielectric layer, is covered on this first metal layer, and comprises one first opening, and this first opening exposes the part of this first metal layer;
One second metal level, is positioned on this first dielectric layer, and a part for this second metal level sees through this first opening and is connected with this first metal layer;
One second dielectric layer, is covered on this second metal level, and comprises one second opening and one the 3rd opening, and this second opening is positioned at directly over this first opening, and exposes this part of this second metal level, and the 3rd opening exposes another part of this second metal level;
One the 3rd metal level, is positioned on this second dielectric layer;
One the 3rd dielectric layer, be covered on the 3rd metal level, and comprise one the 4th opening, one the 5th opening and one the 6th opening, the 4th opening is positioned at directly over this second opening, the 5th opening is positioned at directly over the 3rd opening, and the 6th opening is positioned at the 3rd metal level top;
One first transparent capacitance electrode layer, is positioned on this second dielectric layer, and connects the 3rd metal level; And
One second transparent capacitance electrode layer, be positioned on the 3rd dielectric layer, and connect this first metal layer through the 4th opening, see through the 5th opening and connect this second metal level, see through the 6th opening and connect the 3rd metal level, wherein this second transparent capacitance electrode layer and this first transparent capacitance electrode layer through-thickness storehouse and relative across the 3rd dielectric layer.
Capacitance structure of the present utility model, it also comprises one the 3rd transparent capacitance electrode layer and this first transparent capacitance electrode layer through-thickness storehouse and relative across this first dielectric layer, this second dielectric layer, and connects this first metal layer.
Capacitance structure of the present utility model also comprises one the 4th transparent capacitance electrode layer and this first transparent capacitance electrode layer through-thickness storehouse and relative across this second dielectric layer, and connects this second metal level.
The 3rd described metal level be positioned at this first transparent capacitance electrode layer above or below.
Described the first metal layer be positioned at the 3rd transparent capacitance electrode layer above or below.
The second described metal level be positioned at the 4th transparent capacitance electrode layer above or below.
The 3rd described metal level is a pierced pattern, and this pierced pattern comprises box-shaped pattern or palisade pattern.
Described panel comprises a thin-film transistor, the drain electrode of this first metal layer and this thin-film transistor is made simultaneously, the source electrode of this second metal level and this thin-film transistor is made simultaneously, and the pixel electrode of this second transparent capacitance electrode layer and this thin-film transistor is made simultaneously.
Described panel more comprises a common lines, and the 3rd metal level and this common lines are made simultaneously.
Described panel more comprises one and shares transparency electrode, and this first transparent capacitance electrode layer and this shared transparency electrode are made simultaneously.
In the utility model, the multi-layer transparent capacitance electrode layer of through-thickness storehouse can be equivalent to shunt capacitance, and can increase capacitance, reduces the area that electric capacity accounts for entire scan drive circuit, to reach the object of narrow frame.In addition, because the capacitance structure of printing opacity can reach liquid crystal, splash into the required light transmittance of light-hardening resin in processing procedure, and can be applicable to liquid crystal, splash into processing procedure.Compared to traditional Liquid crystal pour processing procedure, liquid crystal splashes into processing procedure more can save processing procedure time and cost.
Accompanying drawing explanation
Below in conjunction with the drawings and specific embodiments, the utility model is described in further detail:
Fig. 1 is the local elevational schematic view that the utility model drives substrate;
Fig. 2 is the generalized section of the capacitance structure of the utility model embodiment 1;
Fig. 3 is the generalized section of the capacitance structure of this new embodiment 2;
Fig. 4 is the generalized section of the capacitance structure of the utility model embodiment 3;
Fig. 5 is the generalized section of the capacitance structure of this new embodiment 4;
Fig. 6 is the elevational schematic view of the capacitance structure of the utility model embodiment 5;
Fig. 7 is the cross-sectional schematic of the capacitance structure of the utility model embodiment 5;
Fig. 8 is the generalized section of the Ji Ci pixel region, thin film transistor region of this novel driving substrate;
Fig. 9 is the generalized section of the capacitance structure of the utility model embodiment 6;
Figure 10 is the upward view of the capacitance structure of this new embodiment 7;
Figure 11 is the generalized section of the capacitance structure of the utility model embodiment 7;
Figure 12 is the generalized section of the capacitance structure of the utility model embodiment 8;
Figure 13 is the generalized section that the utility model drives the ,Ci pixel region, thin film transistor region of substrate;
Figure 14 is the generalized section that the utility model drives the cabling district of substrate.
Embodiment
Below in conjunction with embodiment, the utility model is described in further detail:
Fig. 1 is the local elevational schematic view that the utility model drives substrate 100.Drive substrate 100 comprise AA,Nei cabling district, an active region INNER, scan drive circuit district GIP,Wai cabling district OUTER and cut split plot CUT.Frame is contained interior cabling district INNER, scan drive circuit district GIP,Wai cabling district OUTER and is cut split plot CUT, and the width of frame is W2.Thin-film transistor or thin-film transistor array can be arranged in the AA of active region.The cabling that is arranged in cabling district INNER Yu Wai cabling district OUTER can be electrically connected the cabling of active region AA.Scan drive circuit can be arranged in scan drive circuit district GIP.Cut the region that split plot CUT is crack line place.Certainly, above-mentioned zone can be done according to practical application request suitable change, and is not limited to Fig. 1 illustration person.
Fig. 2 is the generalized section of capacitance structure of the panel integration scanning drive circuit (Gate Driver In Panel) of the utility model embodiment 1.In the utility model, " panel integration scanning drive circuit " word means scan drive circuit structure and directly does for example driving, on the base material of substrate (thin film transistor base plate).As shown in Figure 2, the capacitance structure of scan drive circuit structure is by the first metal layer M1, the first dielectric layer 120, the first transparent capacitance electrode layer TR1, the second metal level M2, the second dielectric layer 130 and the second transparent capacitance electrode layer TR2 storehouse and forming on base material 110 sequentially.
The first metal layer M1 is positioned on base material 110.It is upper that the first dielectric layer 130 is covered in the first metal layer M1, and comprise the part that one first opening 120a exposes the first metal layer M1.
The second metal level M2 is positioned on the first dielectric layer 130, and a part of the second metal level M2 is connected with the first metal layer M1 through the first opening 120a.
It is upper that the second dielectric layer 130 is covered in the second metal level M2, and comprise one second opening 130a, and the second opening 130a is positioned at directly over the first opening 120a, and exposes this part of the second metal level M2.
The first transparent capacitance electrode layer TR1 is positioned on the first dielectric layer 120, and connects another part of the second metal level M2.
The second transparent capacitance electrode layer TR2 is positioned on the second dielectric layer 130, and connect the first metal layer M1, wherein the second transparent capacitance electrode layer TR2 and the first transparent capacitance electrode layer TR1 through-thickness storehouse and relative across the second dielectric layer 130 through the second opening 130a.Thus, the first transparent capacitance electrode layer TR1, the second dielectric layer 130, the second transparent capacitance electrode layer TR2 can form an electric capacity.
Above-mentioned the first transparent capacitance electrode layer TR1 directly receives the voltage of this another part that comes from the second metal level M2.This part that the second transparent capacitance electrode layer TR2 can see through the second metal level M2 connects the first metal layer M1, and receives the voltage that comes from the first metal layer M1.The second transparent capacitance electrode layer TR2 at this, do not limit the stack architecture of conductive layer in the first opening 120a and the second opening 130a (being selected from the second metal level M2, the first transparent capacitance electrode layer TR1 or its combination in any), as long as can be electrically connected to the first metal layer M1.
Fig. 3 is the generalized section of the capacitance structure (comprising three layers of transparent capacitance electrode layer) of the utility model embodiment 2.Be with the illustrative capacitance structure difference of Fig. 2, Fig. 3 more comprises one the 3rd transparent capacitance electrode layer TR3 and the first transparent capacitance electrode layer TR1 through-thickness storehouse and relative across the first dielectric layer 120.And the 3rd transparent capacitance electrode layer TR3 connects the first metal layer M1, and receive the voltage that comes from the first metal layer M1.Thus, the 3rd transparent capacitance electrode layer TR3, the first dielectric layer 120, the first transparent capacitance electrode layer TR1, the second dielectric layer 130, the second transparent capacitance electrode layer TR2 can form an electric capacity.Wherein, the second transparent capacitance electrode layer TR2 in the structure shown in Fig. 2 sees through the second metal level M2 to connect the first metal layer M1, and its contact impedance is low; The second transparent capacitance electrode layer TR2 in structure shown in the 3rd figure sees through the second metal level M2, the first transparent capacitance electrode layer TR1 and the 3rd transparent capacitance electrode layer TR3 connection the first metal layer M1, therefore its contact impedance is higher.
Fig. 4 is the utility model embodiment 3 capacitance structures generalized sections of (comprising three layers of transparent capacitance electrode layer).Be with the Main Differences of the illustrative capacitance structure of Fig. 2, the second metal level M2 of Fig. 4 is positioned at the below of the first transparent capacitance electrode layer TR1.
Fig. 5 is the generalized section of the capacitance structure (comprising three layers of transparent capacitance electrode layer) of the utility model embodiment 4.Be that with the Main Differences of the illustrative capacitance structure of Fig. 3 the second metal level M2 of Fig. 5 is positioned at the below of the first transparent capacitance electrode layer TR1.
Fig. 6 and Fig. 7 are respectively upward view and the generalized section of the capacitance structure of the utility model embodiment 5.In the present embodiment, the first metal layer M1 and the second metal level M2 can be all pierced pattern, for example, be box-shaped pattern or palisade pattern.The pattern of the second metal level M2 can roughly overlap with the first metal layer M1 shown in 6A figure.In the utility model, it is patterned metal layer that " box-shaped pattern " word means metal level, and it has an opening can printing opacity; " palisade pattern " word mean this patterned metal layer there are a plurality of openings can printing opacity.In other words, pierced pattern encloses the window shape region of putting out and is transparent area TR.Because the surface resistance of metal is less than the surface resistance of transparent capacitance electrode layer, therefore metal pierced pattern is set, contribute to reduce resistance, and maintain certain light transmittance.Certainly, in practical application, can go out according to the Demand Design of light transmittance the shape of various pierced patterns, and be not limited to Fig. 6 illustration person.
Each assembly in forming thin-film transistor on base material 110 time, can form each layer of metal level, dielectric layer and the transparent capacitance electrode layer of capacitance structure of the present utility model simultaneously.This capacitance structure for example can arrange in pairs or groups IPS (In-Plane Switching) or FFS (Fringe Field Switching) technology, but be not limited to this.For example also can arrange in pairs or groups TN (twisted nematic) or VA (vertical alignment) technology.
Below, utilizing the capacitance structure of an end lock type thin-film transistor and Fig. 2 is example, and the embodiment of each layer is described in detail in detail.Fig. 8 is the generalized section of TFTJi Ci pixel region, the thin film transistor region P of driving substrate of the present utility model.TFTJi Ci pixel region, thin film transistor region P can be positioned at the active region AA of Fig. 1.Drive substrate to comprise a thin-film transistor, thin-film transistor comprises drain electrode M1', gate dielectric layer 120', semiconductor layer S, source electrode M2' and drain M2'', the first protective layer 130', pixel electrode TR1' and shared transparency electrode TR2'.
Referring to Fig. 2 and Fig. 8, the first metal layer M1 and drain electrode M1' can form in same processing procedure.That is the first metal layer M1 can be made by the material of the drain electrode M1' of thin-film transistor.Drain electrode M1' material can be metal or metallic compound.Metal material comprises molybdenum (Mo), chromium (Cr), aluminium (Al), neodymium (Nd), titanium (Ti), copper (Cu), silver (Ag), gold (Au), zinc (Zn), indium (In), gallium (Ga), other suitable materials or above-mentioned combination.Metallic compound material comprises metal alloy, metal oxide, metal nitride, metal oxynitride, other suitable materials or above-mentioned combination.
The first dielectric layer 120 can form with gate dielectric layer 120' in same processing procedure.The material of gate dielectric layer 120' comprises organic dielectric materials, inorganic material or combinations thereof.Organic dielectric materials is for example pi (Polyimide, PI), Merlon (PC), polyphthalate, poly-how dioctyl phthalate alcohol ester, polypropylene (PP), polyethylene (PE), polystyrene (PS) or other suitable material.Inorganic material is for example silica, silicon nitride, silicon oxynitride or other suitable material.
The second metal level M2 and source electrode M2' can form in same processing procedure.In other words, the second metal level M2 can be made by the source electrode M2' material of thin-film transistor.Source electrode M2' material can be with reference to the embodiment of above-mentioned drain electrode M1' material.
The second dielectric layer 130 and the first protective layer 130' can form in same processing procedure.The material of the first protective layer 130' can be with reference to the embodiment of the material of above-mentioned gate dielectric layer 120'.
The second transparent capacitance electrode layer TR2 and shared transparency electrode (Vcom) TR2' can form in same processing procedure.In other words, the second transparent capacitance electrode layer TR2 is made by the material of sharing transparency electrode TR2'.Share transparency electrode TR2' material and can be tin indium oxide (ITO), indium zinc oxide (IZO), hafnium oxide (HfOx), zinc oxide (ZnOx), aluminum zinc oxide (AZO), aluminium oxide tin (ATO), indium oxide gallium zinc (IGZO), gallium oxide zinc (GZO), indium oxide titanium (ITiO), indium oxide molybdenum (IMO), other suitable materials or above-mentioned combination.
One pixel electrode TR1' is set in inferior pixel region P between gate dielectric layer 120' and the first protective layer 130'.This pixel electrode TR1' and the first transparent capacitance electrode layer TR1 can form in same processing procedure.The material of the first transparent capacitance electrode layer TR1 can be with reference to the embodiment of above-mentioned shared transparency electrode TR2' material.
In another embodiment, the 3rd transparent capacitance electrode layer TR3 shown in Fig. 3,4,5,7 also can form with another layer of shared transparency electrode (not illustrating) or storage capacitors electrode (not illustrating) in same processing procedure.
Fig. 9 is the generalized section of the capacitance structure (comprising Double-layered transparent capacitance electrode layer) of the utility model embodiment 6.This capacitance structure comprises the first metal layer M1, the second metal level M2, the 3rd metal level M3, the first dielectric layer 220, the second dielectric layer 230, the 3rd dielectric layer 240, the first transparent capacitance electrode layer TR1 and the second transparent capacitance electrode layer TR2.
The first metal layer M1 is positioned on base material 210.It is upper that the first dielectric layer 220 is covered in the first metal layer M1, and comprise one first opening 220a, and the first opening 220a exposes a part of the first metal layer M1.
The second metal level M2 is positioned on the first dielectric layer 220, and a part of the second metal level M2 contacts with this part of the first metal layer M1 through the first opening 220a.
The second dielectric layer 230 is covered on the second metal level M2, and comprise one second opening 2301a and one the 3rd opening 2302a, the second opening 2301a is positioned at directly over the first opening 220a, and exposes this part of the second metal level M2, and the 3rd opening 2302a exposes another part of the second metal level M2.
The 3rd metal level M3 is positioned on the second dielectric layer 230.In one embodiment, the 3rd metal level M3 is pierced pattern, and pierced pattern comprises box-shaped pattern or palisade pattern.
It is upper that the 3rd dielectric layer 240 is covered in the 3rd metal level M3, and comprise one the 4th opening 2401a, one the 5th opening 2402a and one the 6th opening 2403a.The 4th opening 2401a is positioned at directly over the second opening 2301a.The 5th opening 2402a is positioned at directly over the 3rd opening 2302a.The 6th opening 2403a is positioned at the 3rd metal level M3 top.
The first transparent capacitance electrode layer TR1 is positioned on the second dielectric layer 230, and connects the 3rd metal level M3.
The second transparent capacitance electrode layer TR2 is positioned on the 3rd dielectric layer 240, see through the 5th opening 2402a and connect the second metal level M2, wherein the second transparent capacitance electrode layer TR2 and the first transparent capacitance electrode layer TR1 through-thickness storehouse and relative across the 3rd dielectric layer 240.Thus, the first transparent capacitance electrode layer TR1, the 3rd dielectric layer 240, the second transparent capacitance electrode layer TR2 can form an electric capacity.In addition, another part of the second transparent capacitance electrode layer TR2 connects respectively the first metal layer M1 and the 3rd metal level M3 through the 4th opening 2401a and the 6th opening 2403a.
As shown in Figure 9, another part that the first transparent capacitance electrode layer TR1 sees through the second transparent capacitance electrode layer TR2 connects the first metal layer M1, and receives the voltage that comes from the first metal layer M1.The second transparent capacitance electrode layer TR2 sees through the 5th opening 2402a and contacts the second metal level M2, and receives the voltage that comes from the second metal level M2.As long as the first transparent capacitance electrode layer TR1 and the second transparent capacitance electrode layer TR2 receive respectively the voltage of different layers, and do not limit its electric connection mode.
Figure 10 and Figure 11 are upward view and the generalized section of the capacitance structure of the utility model embodiment 7.In the present embodiment, the 3rd metal level M3 is a pierced pattern, as shown in figure 10.Pierced pattern has at least one opening can printing opacity.In other words, pierced pattern encloses the window type region of putting out and is transparent area TR.Because the surface resistance of metal is less than the surface resistance of transparent capacitance electrode layer, therefore metal pierced pattern is set, contribute to reduce resistance, and maintain certain light transmittance.Certainly, in practical application, can go out according to the Demand Design of light transmittance the shape of various pierced patterns, and be not limited to Figure 10 illustration person.
The illustrative capacitance structure difference of Figure 11 and Fig. 9 is, another part that the first transparent capacitance electrode layer TR1 sees through the second transparent capacitance electrode layer TR2 that is arranged in the 6th opening 2403a and the 5th opening 2402a connects the second metal level M2, and receives the voltage that comes from the second metal level M2.The second transparent capacitance electrode layer TR2 sees through the 4th opening 2401a and connects the first metal layer M1, and receives the voltage that comes from the first metal layer M1.And capacitance structure more comprises one the 3rd transparent capacitance electrode layer TR3 and the first transparent capacitance electrode layer TR1 through-thickness storehouse and relative across the first dielectric layer 220, the second dielectric layer 230, and connects the first metal layer M1.Thus, the 3rd transparent capacitance electrode layer TR3, the first dielectric layer 220, the second dielectric layer 230, the first transparent capacitance electrode layer TR1, the 3rd dielectric layer 240, the second transparent capacitance electrode layer TR2 can form an electric capacity.
Figure 12 is the generalized section of the capacitance structure (comprising four layers of transparent capacitance electrode layer) of the utility model embodiment 8.Be with the illustrative capacitance structure difference of Fig. 9, the capacitance structure of Figure 12 more comprises one the 3rd transparent capacitance electrode layer TR3 and one the 4th transparent capacitance electrode layer TR4.The 3rd transparent capacitance electrode layer TR3 and the first transparent capacitance electrode layer TR1 through-thickness storehouse, and connect the first metal layer M1.The 4th transparent capacitance electrode layer TR4 and the second transparent capacitance electrode layer TR2 through-thickness storehouse and relative with the 3rd dielectric layer 240 across the second dielectric layer 230, the first transparent capacitance electrode layer TR1, and connect the second metal level M2.Thus, the 3rd transparent capacitance electrode layer TR3, the first dielectric layer 220, the 4th transparent capacitance electrode layer TR4, the second dielectric layer 230, the first transparent capacitance electrode layer TR1, the 3rd dielectric layer 240, the second transparent capacitance electrode layer TR2 can form an electric capacity.
In several execution modes, the 3rd metal level M3 can be positioned at the first transparent capacitance electrode layer TR1 above or below, the first metal layer M1 can be positioned at the 3rd transparent capacitance electrode layer TR3 above or below, the second metal level M2 can be positioned at the 4th transparent capacitance electrode layer TR4 above or below.
Below, utilizing the capacitance structure of an end lock type thin-film transistor and Fig. 9 is example, and the embodiment of each layer is described in detail in detail.Figure 13-14 are respectively the utility model one and drive thin film transistor region TFT (Figure 13), the inferior pixel region P (Figure 13) of substrate and the generalized section of cabling district (Figure 14).TFT,Ci pixel region, thin film transistor region P, cabling district can be positioned at the active region AA of Fig. 1.As shown in figure 13, thin-film transistor comprises drain electrode M1', gate dielectric layer 220', semiconductor layer S, source electrode M2' and drain M2'', the first protective layer 230', shares transparency electrode TR1'', the second protective layer 240' and pixel electrode TR2''.As shown in figure 14, a common lines M3' is arranged at data line M2''' top, and has the first protective layer 230' to be located between common lines M3' and data wire M2'''.Common lines M3' can connect the shared transparency electrode TR1'' in Figure 13.
Referring to Fig. 9 and Figure 13, the embodiment of the part assembly of the part assembly of Fig. 9 (as the first metal layer M1, the first dielectric layer 220, the second metal level M2, the second dielectric layer 230) and Figure 13 (as drain electrode M1', gate dielectric layer 220', source electrode M2', the first protective layer 230') please refer to the embodiment of above-mentioned Fig. 2 and the corresponding assembly (being the assembly of same names) of Fig. 8.
Specifically, can form the first transparent capacitance electrode layer TR1 and shared transparency electrode TR1''(simultaneously be arranged in time pixel region P).In other words, the first transparent capacitance electrode layer TR1 is made by the material of sharing transparency electrode TR1''.The material of sharing transparency electrode TR1'' can be with reference to the embodiment of the shared transparency electrode TR2' material in figure 8.In addition, can form the second transparent capacitance electrode layer TR2 and pixel electrode TR2'' simultaneously.
And, can form the 3rd metal level M3 and common lines M3', as shown in Fig. 9 and Figure 14 simultaneously.In other words, the 3rd metal level M3 is made by the material of common lines M3'.The material of common lines M3' can be with reference to the embodiment of the drain electrode M1' material in figure 8.
In addition, can form the 3rd dielectric layer 240 and the second protective layer 240', as shown in Fig. 9 and Figure 13-14 simultaneously.The material of the 3rd dielectric layer 240 and the second protective layer 240' can be with reference to the embodiment of the gate dielectric layer 120' material in figure 8.
From the above, the capacitance structure of panel integration scanning drive circuit and the structure of thin-film transistor array of the execution mode that this is novel can form simultaneously, and can save the cost of drain drives IC.And the multi-layer transparent capacitance electrode layer of through-thickness storehouse can be equivalent to shunt capacitance and increase capacitance, reduce the area that electric capacity accounts for entire scan drive circuit, to reach the object that shortens border width.In addition, because the capacitance structure of printing opacity can reach certain light transmittance, and can be applicable to liquid crystal, splash into processing procedure, and more can save processing procedure time and cost.
Although the utility model discloses as above with execution mode; so it is not novel in order to limit this; anyly have the knack of this skill person; within not departing from these novel spirit and scope; when doing various changes and retouching, therefore this novel protection range when depending on after the attached claim person of defining be as the criterion.
Claims (16)
1. a capacitance structure for panel integration scanning drive circuit, is characterized in that: it comprises:
One the first metal layer;
One first dielectric layer, is covered on this first metal layer, and comprises one first opening, and this first opening exposes the part of this first metal layer;
One second metal level, is positioned on this first dielectric layer, and a part for this second metal level sees through this first opening and is connected with this first metal layer;
One second dielectric layer, is covered on this second metal level, and comprises one second opening, and this second opening is positioned at directly over this first opening, and exposes this part of this second metal level;
One first transparent capacitance electrode layer, is positioned on this first dielectric layer, and connects another part of this second metal level; And
One second transparent capacitance electrode layer, is positioned on this second dielectric layer, and connects this first metal layer through this second opening, wherein this second transparent capacitance electrode layer and this first transparent capacitance electrode layer through-thickness storehouse and relative across this second dielectric layer.
2. capacitance structure according to claim 1, is characterized in that: it also comprises one the 3rd transparent capacitance electrode layer and this first transparent capacitance electrode layer through-thickness storehouse and relative across this first dielectric layer, and connects this first metal layer.
3. capacitance structure according to claim 1, is characterized in that: described the second metal level be positioned at this first transparent capacitance electrode layer above or below.
4. capacitance structure according to claim 2, is characterized in that: described the first metal layer be positioned at the 3rd transparent capacitance electrode layer above or below.
5. capacitance structure according to claim 1, is characterized in that: described the first metal layer and this second metal level are a pierced pattern.
6. capacitance structure according to claim 1, it is characterized in that: described panel comprises a thin-film transistor, the drain electrode of this first metal layer and this thin-film transistor is made simultaneously, the source electrode of this second metal level and this thin-film transistor is made simultaneously, the transparency electrode of sharing of this second transparent capacitance electrode layer and this thin-film transistor is made simultaneously, and the pixel electrode of this first transparent capacitance electrode layer and this thin-film transistor is made simultaneously.
7. a capacitance structure for panel integration scanning drive circuit, is characterized in that: it comprises:
One the first metal layer;
One first dielectric layer, is covered on this first metal layer, and comprises one first opening, and this first opening exposes the part of this first metal layer;
One second metal level, is positioned on this first dielectric layer, and a part for this second metal level sees through this first opening and is connected with this first metal layer;
One second dielectric layer, is covered on this second metal level, and comprises one second opening and one the 3rd opening, and this second opening is positioned at directly over this first opening, and exposes this part of this second metal level, and the 3rd opening exposes another part of this second metal level;
One the 3rd metal level, is positioned on this second dielectric layer;
One the 3rd dielectric layer, be covered on the 3rd metal level, and comprise one the 4th opening, one the 5th opening and one the 6th opening, the 4th opening is positioned at directly over this second opening, the 5th opening is positioned at directly over the 3rd opening, and the 6th opening is positioned at the 3rd metal level top;
One first transparent capacitance electrode layer, is positioned on this second dielectric layer, and connects the 3rd metal level; And
One second transparent capacitance electrode layer, be positioned on the 3rd dielectric layer, and connect this first metal layer through the 4th opening, see through the 5th opening and connect this second metal level, see through the 6th opening and connect the 3rd metal level, wherein this second transparent capacitance electrode layer and this first transparent capacitance electrode layer through-thickness storehouse and relative across the 3rd dielectric layer.
8. capacitance structure according to claim 7, it is characterized in that: it also comprises one the 3rd transparent capacitance electrode layer and this first transparent capacitance electrode layer through-thickness storehouse and relative across this first dielectric layer, this second dielectric layer, and connects this first metal layer.
9. capacitance structure according to claim 7, is characterized in that: it also comprises one the 4th transparent capacitance electrode layer and this first transparent capacitance electrode layer through-thickness storehouse and relative across this second dielectric layer, and connects this second metal level.
10. capacitance structure according to claim 7, is characterized in that: the 3rd described metal level be positioned at this first transparent capacitance electrode layer above or below.
11. capacitance structures according to claim 8, is characterized in that: described the first metal layer be positioned at the 3rd transparent capacitance electrode layer above or below.
12. capacitance structures according to claim 9, is characterized in that: the second described metal level be positioned at the 4th transparent capacitance electrode layer above or below.
13. capacitance structures according to claim 7, is characterized in that: the 3rd described metal level is a pierced pattern.
14. capacitance structures according to claim 7, it is characterized in that: described panel comprises a thin-film transistor, the drain electrode of this first metal layer and this thin-film transistor is made simultaneously, the source electrode of this second metal level and this thin-film transistor is made simultaneously, and the pixel electrode of this second transparent capacitance electrode layer and this thin-film transistor is made simultaneously.
15. capacitance structures according to claim 14, is characterized in that: described panel more comprises a common lines, and the 3rd metal level and this common lines are made simultaneously.
16. capacitance structures according to claim 15, is characterized in that: described panel more comprises one and shares transparency electrode, and this first transparent capacitance electrode layer and this shared transparency electrode are made simultaneously.
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| CN201320208601.2U CN203434152U (en) | 2013-04-22 | 2013-04-22 | Capacitor structure of panel integrated scanning drive circuit |
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| CN201320208601.2U CN203434152U (en) | 2013-04-22 | 2013-04-22 | Capacitor structure of panel integrated scanning drive circuit |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104483771A (en) * | 2014-10-28 | 2015-04-01 | 上海中航光电子有限公司 | Thin Film Transistor (TFT) array substrate, display panel and display device |
| CN111370430A (en) * | 2018-12-26 | 2020-07-03 | 联华电子股份有限公司 | Integrated circuit device and method of forming an integrated circuit |
-
2013
- 2013-04-22 CN CN201320208601.2U patent/CN203434152U/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104483771A (en) * | 2014-10-28 | 2015-04-01 | 上海中航光电子有限公司 | Thin Film Transistor (TFT) array substrate, display panel and display device |
| US9620531B2 (en) | 2014-10-28 | 2017-04-11 | Shanghai Avic Optoelectronics Co., Ltd. | TFT array substrate, display panel and display device |
| CN111370430A (en) * | 2018-12-26 | 2020-07-03 | 联华电子股份有限公司 | Integrated circuit device and method of forming an integrated circuit |
| CN111370430B (en) * | 2018-12-26 | 2023-07-11 | 联华电子股份有限公司 | Integrated circuit device and method for forming integrated circuit |
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