CN203982752U - Gate driver circuit, array base palte and display device - Google Patents

Abstract

The utility model relates to the field of liquid crystal display manufacture, and specifically provides a gate drive circuit, an array substrate and a display device. Aiming at the problem that the TSP signal acquisition of each frame in the prior art is scanned at a fixed time, which may appear to the human eye, the problem of dark lines may appear. Control whether it works, so as to achieve the effect of staggering adjacent frame panels to suspend work for a predetermined time. The utility model can stagger the preset time of suspending work of the touch screen panel in the adjacent odd and even frames, thereby solving the problem of dark lines appearing to human eyes.

Description

Gate driving circuit, array substrate and display device

technical field

The utility model relates to the field of liquid crystal display manufacture, in particular to a grid drive circuit, an array substrate and a display device.

Background technique

In recent years, the development of liquid crystal displays has shown a trend of high integration and low cost. One of the very important technologies is the realization of mass production of GOA (Gate Driver on Array, array substrate row driver). The GOA technology is used to integrate the gate switching circuit on the array substrate of the liquid crystal display panel, thereby saving the part of the gate drive integrated circuit and reducing the product cost in terms of material cost and manufacturing process. The gate switch circuit integrated on the array substrate using GOA technology is also called a GOA gate drive circuit.

In the gate drive circuit applied to the touch screen panel (Touch Screen Panel, TSP), in order to store the gate line drive signal (also called GATE signal) between the shift register units that stops passing when the TSP signal is scanned, the A delay shift module is added between adjacent two-stage shift register units, which is used to temporarily store the gate line driving signal transmitted there, and continue to transmit backward after scanning the TSP signal.

However, since the position of the delay displacement module in the gate drive circuit is fixed, as shown in Figure 1(b), the delay displacement module includes a first shift register DUMMY1 and a second shift register DUMMY2, the first shift register The output terminals of the bit register DUMMY1 and the second shift register DUMMY2 are not connected to the gate line, so the shift register unit will suspend work at the same predetermined time during the transmission of the gate line driving signal in each frame. Therefore, a row of pixels corresponding to the gate driving circuit will periodically suspend light emission. As a result, there is a problem that dark lines appear to the human eye, so that the panel cannot be displayed normally.

Utility model content

(1) Solved technical problems

Aiming at the deficiencies of the prior art, the utility model provides a gate drive circuit, an array substrate and a display device, which can stagger the time when the touch screen panel suspends work in adjacent frames, thereby solving the problem of dark lines appearing to the human eye.

(2) Technical solutions

In order to achieve the above object, the utility model is realized through the following technical solutions:

A gate drive circuit, comprising a plurality of cascaded shift register units, characterized in that the gate drive circuit also includes:

At least two delay displacement modules and switch control modules respectively connected to the delay displacement modules, the delay displacement modules are located between adjacent shift register units, and there are also delay displacement modules between at least one cascaded shift register unit;

The switch control module is used to control two different delay displacement modules to be connected between adjacent shift register units between adjacent frames, and to skip the transmission of the gate line driving signal in each frame. Other delayed displacement modules not connected;

The delay displacement module is used to suspend the clock signal connected to the delay displacement module for a predetermined time when accessing the adjacent shift register unit, and store the clock signal from the adjacent shift register within the predetermined time of the suspension of the clock signal. The gate line driving signal of the previous stage shift register unit, and after the clock signal is recovered, the gate line driving signal is transmitted to the adjacent subsequent stage shift register unit.

Preferably, the switch control module includes a group of switch elements corresponding to each of the delay displacement modules, and each group of switch elements is used to output a switch control signal to the corresponding delay displacement module to control the delay displacement module It is connected between adjacent shift register units, or the transmission of the gate line driving signal skips the delay shift module.

Preferably, each group of switch elements includes a first switch element and a second switch element, and in one of the group of switch elements in which the corresponding delay displacement module is located between the N-1th stage and the Nth stage shift register unit, the first Both the first end of a switch element and the second switch element are connected to the output end of the N-1th stage shift register unit; and the second end of the first switch element is connected to the input end of the delay shift module; The output end of this time-delay displacement module is connected with the input end of the Nth stage shift register unit; the second end of the second switch element is connected with the output end of the Nth stage shift register unit; the first switch element The control end of the switch element is connected to the first control signal line, and the control end of the second switch element is connected to the second control signal line.

Preferably, the switching element is a thin film field effect transistor.

Preferably, the delay displacement module includes a cascaded first shift register unit and a second shift register unit, and the two shift register units are cascaded between the N-1th stage and the Nth stage shift register unit Between, the input terminal of the first shift register unit is used as the input terminal of the delay displacement module, the output terminal of the second shift register unit is used as the output terminal of the delay displacement module, and the input terminal of the first shift register unit is passed through The first switch element is connected to the output end of the N-1th stage shift register unit, and the output end of the first shift register unit, the reset end of the second shift register unit are connected to the Nth stage shift register unit The output terminal and the reset terminal of the N-1th shift register unit are connected to one point, and N is an integer not less than 2.

An array substrate, characterized in that the array substrate includes any one of the above-mentioned gate driving circuits.

A display device, characterized in that the array substrate includes any one of the above-mentioned array substrates.

(3) Beneficial effects

The utility model has at least the following beneficial effects:

The utility model mainly arranges delay displacement modules in at least two different positions, and controls whether they work by the corresponding switch control modules, so as to achieve the effect of staggering adjacent frame panels to suspend work for a predetermined time.

Specifically, in a circuit with two switching elements in each group, when one of them is in the conduction state, the gate line driving signal will directly skip the corresponding delay displacement module and transmit it backward; while the other switch element is in the conduction state When it is in the on state, the gate line driving signal will enter the delay displacement module, which means that it enters the normal working state. In this way, as long as the on and off of each group of switching elements is controlled by the control signal, its working state can be switched flexibly. Here, in order to stagger the positions of the delay shifting modules in adjacent frames, only one of the delay shifting modules can be made to work in odd frames, and the gate line driving signal directly skips other delay shifting modules; Specifically, only another delay shift module is operated in an even frame, and the gate line driving signal directly skips other delay shift modules except this delay shift module. In this way, the predetermined time for suspending work of the touch screen panel in adjacent odd and even frames is staggered, thereby solving the problem of dark lines appearing to human eyes.

Of course, any product implementing the present utility model does not necessarily need to achieve all the above-mentioned advantages at the same time.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the accompanying drawings that need to be used in the description of the embodiments or the prior art. Obviously, the appended drawings in the following description The drawings show some embodiments of the utility model, and those skilled in the art can also obtain other drawings according to these drawings without creative work.

Fig. 1(a), Fig. 1(b) and Fig. 1(c) are the cascading diagrams of some shift register units of the gate drive circuit in the prior art;

Fig. 2 is a circuit structure diagram of a gate drive circuit in an embodiment of the present invention;

Fig. 3 (a) is the circuit structure diagram of the first delay displacement module part of the gate drive circuit in one embodiment of the present invention;

Fig. 3 (b) is the circuit structure diagram of the second delay displacement module part of the gate drive circuit in one embodiment of the present invention;

Fig. 4 (a) Fig. 4 (b) is a partial circuit diagram of the preferred gate drive circuit in one embodiment of the present invention;

FIG. 5 is a working sequence diagram of a preferred gate drive circuit in an embodiment of the present invention.

in:

CK, CKB - clock signal, or the clock signal terminal of the shift register unit;

STV - the gate line drive signal, or the input end of the shift register unit;

Output——the output terminal of the shift register unit;

RST - the reset terminal of the shift register unit;

G1, G2, ..., GN, ..., GM, ...—the shift register unit number of the first stage, the second stage, ..., the Nth stage, ..., the Mth stage, ..., or its output signal;

GOA unit——shift register unit;

Q1——the first switching element; Q2——the second switching element;

Q3——the third switching element; Q4——the fourth switching element;

DUMMY1——the first shift register unit of the first delay displacement module, or its output signal; DUMMY2——the second shift register unit of the first delay displacement module, or its output signal; DUMMY3——the second delay The third shift register unit of the time shift module, or its output signal; DUMMY4——the fourth shift register unit of the second delay shift module, or its output signal;

CTL_A - the first control signal (line);

CTL_B - the second control signal (line).

Detailed ways

In order to make the purpose, technical solutions and advantages of the embodiments of the utility model more clear, the technical solutions in the embodiments of the utility model will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the utility model. Obviously, the described The embodiments are some embodiments of the present utility model, but not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the scope of protection of the present utility model.

Example 1

The embodiment of the utility model proposes a gate drive circuit, the gate drive circuit includes:

Multiple shift register units cascaded, see Figure 1(a), Figure 1(b) and Figure 1(c), Figure 1(a), Figure 1(b) and Figure 1(c) form a complete In the gate drive circuit, the clock signal terminal of each shift register unit has a corresponding clock signal input; the input terminal of the upper stage is connected to the output terminal of the next stage in turn, which means that the gate line drive signal is sequentially controlled by the clock signal It is transmitted in stages; and the output terminal of the next stage is also connected to the reset terminal of the previous stage, which means that after the next stage completes the transfer, the signal in the previous stage will be reset to prepare for the next signal transmission. It should be noted that the word "cascaded" in the gate drive circuit specifically refers to the connection relationship including the above-mentioned connection mode and similar connection modes, which are present in the shift register and gate drive circuit in the prior art. A technical term with a clear meaning.

Referring to Figure 2, the gate drive circuit also includes:

At least two delay displacement modules and switch control modules respectively connected to the delay displacement modules, the delay displacement modules are located between adjacent shift register units, and there are also delay displacement modules between at least one cascaded shift register unit;

The switch control module is used to control two different delay displacement modules to be connected between adjacent shift register units between adjacent frames, and to skip the transmission of the gate line driving signal in each frame. Other delayed displacement modules not connected;

The delay displacement module is used to suspend the clock signal connected to the delay displacement module for a predetermined time when accessing the adjacent shift register unit, and store the clock signal from the adjacent shift register within the predetermined time of the suspension of the clock signal. The gate line driving signal of the previous stage shift register unit, and after the clock signal is recovered, the gate line driving signal is transmitted to the adjacent subsequent stage shift register unit.

Wherein, the switch control module is realized by a group of switch elements correspondingly connected to each of the delay displacement modules. In FIG. Group switching elements as an example.

It can be seen that the gate drive circuit sets delay displacement modules at at least two different positions, and controls whether they work by the corresponding switch control module, so as to achieve the effect of staggering the predetermined time of suspending operation of adjacent frame panels.

Example 2

The embodiment of the utility model proposes a gate drive circuit with only two delay displacement modules, and the corresponding switch control module includes two sets of switching elements (two switching elements in each group), see Fig. 3(a) and Fig. 3(b ), Figure 3(a) and Figure 3(b) are a complete gate drive circuit, which includes, in addition to multiple cascaded shift register units:

The first delay displacement module 201, its input end is connected to the first end of the first switch element Q1, and its output end is connected to the input end of the Nth stage shift register unit;

The first switch element Q1, the second end of which is connected to the output end of the N-1th stage shift register unit;

The second switch element Q2, its first end is connected to the output end of the N-1st stage shift register unit, its second end is connected to the input end STV of the N+1st stage shift register unit, and the Nth stage shift register The output terminal connection of the unit;

The second delay displacement module 202, its input end is connected to the first end of the third switch element Q3, and its output end is connected to the input end of the Mth stage shift register unit;

The third switch element Q3, the second end of which is connected to the output end of the M-1th stage shift register unit;

The fourth switching element Q4, its first end is connected to the output end of the M-1th shift register unit, its second end is connected to the input end of the M+1th shift register unit, and the M-th shift register unit The output terminal connection;

Wherein, M and N are positive integers greater than 1, and M is greater than N.

The gate driving circuit provided by the embodiment of the present invention can stagger the preset time for suspending operation of the touch screen panel in adjacent odd and even frames, so as to solve the problem of dark lines appearing to human eyes.

The following introduces a more specific preferred gate drive circuit, see Figure 4(a) and Figure 4(b), Figure 4(a) and Figure 4(b) are a complete gate drive circuit, in the above gate drive Based on the circuit:

The first delay displacement module includes sequentially cascaded first shift register unit DUMMY1 and second shift register unit DUMMY2, and the input terminal STV of the first shift register unit is used as the input of the first delay displacement module terminal, the output terminal Output of the second shift register unit is used as the output terminal of the first delay shift module, the output terminals of the first shift register unit DUMMY1 and the second shift register unit DUMMY2 are connected in vain, and the corresponding gate lines are not connected .

The second delay displacement module includes a third shift register unit DUMMY3 and a fourth shift register unit DUMMY4 cascaded in sequence, and the input terminal STV of the third shift register unit is used as the input of the second delay displacement module terminal, the output terminal Output of the second shift register unit is used as the output terminal of the second delay shift module, the output terminals of the third shift register unit DUMMY3 and the fourth shift register unit DUMMY4 are connected in vain, and the corresponding gate lines are not connected .

For the first delay displacement module, the output terminal Output of the first shift register unit, the reset terminal RST of the second shift register unit, the output terminal Output of the Nth stage shift register unit, and the N-1 stage shift The reset terminal RST of the bit register unit is connected at one point; for the second delay displacement module, the output terminal Output of its third shift register unit DUMMY3, the reset terminal RST of the fourth shift register unit DUMMY4, the Mth stage shift register The output terminal Output of the unit is connected to the reset terminal RST of the shift register unit of the M-1st stage at one point.

The gate drive circuit further includes: a first control signal line CTL_A, which is connected to the control terminals of the first switching element Q1 and the third switching element Q3; a second control signal line CTL_B, which is connected to the second switching element Q2 and the control terminals of the third switching element Q3. The control terminal of the fourth switching element Q4.

Under preferred conditions, the switching element is a field effect transistor. At this time, preferably the first end of the switching element is the drain of the field effect transistor, the second end of the switching element is the source of the field effect transistor, and the control end of the switching element is the gate of the field effect transistor . More preferably, the field effect transistor is a thin film field effect transistor TFT (Thin Film Transistor).

For this delay displacement module, when the TSP signal acquisition process starts, the clock signals CK and CKB will stop working (change to a constant low level), and the corresponding gate line drive signal will be kept in its first shift register unit In DUMMY1. After the acquisition process is finished, the clock signals CK and CKB continue to work, and the gate line driving signal driven by them will continue to be transmitted to the next-level shift register unit. Because the clock position where the TSP signal acquisition starts is uncertain, abnormal gate line drive signal transmission may occur during the clock stop or reset process (the gate line drive signal is transmitted backward when encountering rising and falling edges), Therefore, the two shift register units here play a role of buffering, so that the transfer position of the gate line driving signal before and after TSP signal acquisition corresponds to the clock signal.

The working principle of the preferred gate drive circuit is as follows:

The circuit structures of Figure 4(a) and Figure 4(b) are explained in conjunction with the timing of Figure 5, where "Odd Frame" represents odd frames, "Even Frame" represents even frames, and "TSP work time" represents the TSP signal acquisition time period . It can be seen that the gate line start signal is initially input from the STV, and under the action of the clock signals CK and CKB, the shift register unit sequentially transmits the gate line drive signals.

On odd frames:

When the output signal GN-1 of the N-1th stage shift register unit is high level, CTL_A outputs high level, CTL_B outputs low level, Q1 is turned on, Q2 is turned off, at this time the N-1st shift The GN-1 high-level signal output by the bit register unit is transmitted to the input terminal STV of the first shift register unit DUMMY1, but at this time CK and CKB stop working, the shift register unit stops the transmission of the gate line drive signal, and the TSP signal starts collection.

When the TSP signal acquisition ends, CK and CKB resume work, and CTL_A still outputs a high level at this time, and the input terminal STV of the first shift register unit DUMMY1 receives the high level output signal GN- 1, and output a high-level signal when the clock signal is at a high level, and transmit it to the input terminal STV of the second shift register unit DUMMY2, and then CTL_A returns to a low level. Because the circuit is designed with the connection of the reset terminal, after each stage outputs a high-level signal, it will automatically reset the signal in the shift register unit of the previous stage. The reset terminal RST of the Nth stage shift register unit Output, and the reset terminal RST of the N-1st stage shift register unit are connected at one point, when the output terminal GN of the Nth stage shift register unit outputs a high voltage Normally, the N-1th shift register unit and the first shift register unit DUMMY1 and the second shift register unit DUMMY2 are reset.

When the shift register unit continues to work down to GM-1, CTL_A outputs low level, CTL_B outputs high level, Q3 tube is turned off, and Q4 tube is turned on. At this time, CK and CKB continue to work, and the gate line driving signal skips DUMMY3 and DUMMY4 to the GM input terminal and continues to be transmitted downward. After GM outputs high level, CTL_B returns to low level.

Correspondingly, on even frames:

When the output signal GN-1 of the shift register unit of the N-1st stage is at a high level, CTL_A outputs a low level, CTL_B outputs a high level, the Q1 tube is turned off, and the Q2 tube is turned on. At this time, CK and CKB continue to work, and the gate line driving signal skips DUMMY1 and DUMMY2 to the GN input terminal and continues to be transmitted downward. After GN outputs a high level, CTL_B returns to a low level.

When the output signal GM-1 of the M-1 shift register unit is at high level, CTL_A outputs high level, CTL_B outputs low level, Q3 is turned on, and Q4 is turned off. At this time, the GM-1 high-level signal output by the M-1 shift register unit is transmitted to the input terminal STV of the third shift register unit DUMMY3, but at this time, the CK and CKB signals stop working, and the shift register unit stops the gate. Line drive signal transmission, TSP part of the signal began to collect.

When the TSP signal acquisition ends, CK and CKB resume work, and CTL_A still outputs a high level at this time, and the input terminal STV of the third shift register unit DUMMY3 receives the high level output signal GM- of the shift register unit of the M-1st stage 1, and output a high-level signal when the clock signal is at a high level, and transmit it to the input terminal STV of the fourth shift register unit DUMMY4, and then CTL_A returns to a low level. Because the circuit is designed with the connection of the reset terminal, after each stage outputs a high-level signal, it will automatically reset the signal in the shift register unit of the previous stage. The reset terminal RST of the M-th stage shift register unit, the output terminal Output of the M-th stage shift register unit, and the reset terminal RST of the M-1-th stage shift register unit are connected at one point, when the output terminal GN of the M-th stage shift register unit outputs a high voltage Usually, the shift register unit of stage M-1, the third shift register unit DUMMY3 and the fourth shift register unit DUMMY4 are reset.

After going through such a series of processes, when the gate drive circuit is in odd frames, the first delay displacement module stops working and collects TSP signals. While in even frames, the second delay displacement module stops working and collects TSP signals. That is to say, the predetermined time for suspending work of the panel in adjacent odd and even frames is staggered, so that the moment when there are dark lines in each frame period seen by human eyes is staggered, so that the problem of possible dark lines can be solved.

Of course, only two time-delay displacement modules in different positions are used in the embodiment of the utility model, and those skilled in the art can set a plurality of time-delay displacement modules in different positions under the same idea to further improve the problem of possible dark lines, or The time-delay displacement module or switch control module of other structures can also be selected to realize the same function, which does not depart from the spirit and scope of the technical solution of the present utility model.

Example 3

The embodiment of the present utility model proposes an array substrate, which includes a GOA (Gate On Array, grid array) area and a display area, and any gate driving circuit described in Embodiment 1 or 2 is arranged in the above-mentioned GOA area.

Example 4

Based on the same concept of the utility model, the embodiment of the utility model proposes a display device, the display device includes any one of the array substrates described in Embodiment 3, and the display device can be: a liquid crystal panel, an electronic paper, an OLED panel, Mobile phones, tablet PCs, TV sets, monitors, laptops, digital photo frames, navigators and any other products or components with display functions.

In order to illustrate the technical solution of the present invention more clearly, here, corresponding to the above gate drive circuit, a driving method applied to the gate drive circuit as described in Embodiment 1 is given, wherein the method includes:

Between adjacent frames, two different delay displacement modules are controlled by the switch control module to be connected between adjacent shift register units;

In each frame, the transmission of the gate line driving signal is skipped by the switch control module to other delay displacement modules that are not connected.

That is to say, on the basis of the gate drive circuit described in Embodiment 1, the following control is realized through the switch control module:

First, only one delay displacement module is connected in each frame; second, two different delay displacement modules are connected between adjacent frames; third, when the delay displacement module is connected, the delay displacement The module is located between two adjacent shift registers; fourthly, in each frame, the transmission of the gate line driving signal is skipped over other delay shift modules that are not connected.

Thereby, the delay displacement modules connected in adjacent frames are all in different positions, which can stagger the scheduled time of suspending work in adjacent frames; at the same time, because only one delay displacement module is connected to each frame, each frame The overall time for is unchanged. Therefore, the design can solve the problem that the screen appears dark lines to human eyes when it is applied to a display device.

Preferably, when the delay displacement module is connected to the adjacent shift register unit, the clock signal connected to the delay displacement module is suspended for a predetermined time, and the touch control is entered within the predetermined time of the clock signal suspension. scanning phase.

Wherein, the position of the clock signal CK pause predetermined time in the timing diagram is schematically referred to in FIG. 5 , it can be seen that the position of the delay shift module relative to the multiple cascaded shift register units corresponds to the time period of the clock signal pause in each frame. The position of the scheduled start time relative to the clock signal throughout the process. That is to say, in order to make the gate line drive signal reach the corresponding delay displacement module at the predetermined time when the clock signal is suspended, so as to realize its function, it is necessary to design the time of the clock signal suspension and the location of the delay displacement module accordingly. Location.

Preferably, the switch control module includes a group of switch elements corresponding to each of the delay displacement modules, each group of switch elements includes a first switch element and a second switch element, and the corresponding delay displacement module is located at the Nth -In one group of switch elements between the 1st stage and the Nth stage shift register unit, the first end of the first switch element and the second switch element are connected to the output end of the N-1st stage shift register unit connected; and the second end of the first switching element is connected to the gate line drive signal input end of the delay shift module; the gate line drive signal output end of the delay shift module is connected to the input of the Nth stage shift register unit The second end of the second switching element is connected to the output end of the Nth stage shift register unit; the control end of the first switching element is connected to the first control signal line, and the control end of the second switching element is connected to the first 2. Control signal line connection;

Said between adjacent frames, through the switch control module to control two different delay displacement modules to be connected between adjacent shift register units specifically includes:

In one frame, at the start moment when the clock signal is suspended for a predetermined time, the output terminal of the N-1 stage shift register unit is controlled by the first switch element to conduct with the input terminal of the delay displacement module, and the delay displacement module is connected input between adjacent shift registers, and other delay displacement modules control the conduction between the output end of the N-1th stage shift register and the input end of the Nth stage shift register through the second switch element.

Preferably, when the delay displacement module is connected between adjacent shift register units, the first control signal line CTL_A controls the first switch element to be turned on before the clock signal is suspended for one clock cycle, that is, as As shown in Figure 5, taking the signal of the first control signal line CTL_A as an example, when the clock signal CK is a high level signal at GN-1, CTL_A starts to change to a high level, and the control signal is controlled after the clock signal resumes output for one clock cycle. The first switch element is turned on, that is, the clock signal CKB returns to a low level after DUMMY1 outputs a high level signal. Such setting of the first control signal line CTL_A can ensure the effective transmission of signals.

That is to say, the first switch control signal line can control the opening (the first terminal is connected with the second terminal) or closing (the first terminal is disconnected with the second terminal) of all the first switching elements in the switch control module; the second switch The control signal line can control all the second switch elements in the switch control module to be turned on (the first terminal is connected to the second terminal) or closed (the first terminal is disconnected from the second terminal). Therefore, when the delay displacement module is connected, the first switch element is turned on (the second switch element is turned off), and when the delay displacement module is not connected, the second switch element is turned on (the first switch element is turned off). In this way, only two switch control signal lines can be used to realize the function of the switch control module, which is beneficial to the simplification of the layout of the gate drive circuit and the reduction of the overall size.

Each frame of the gate driving circuit includes a display phase and a touch scanning phase, and the touch scanning phase is included in a predetermined time when the clock signal is suspended. That is to say, here, the gate drive circuit is specifically applied to the touch display device, and its touch scanning phase (corresponding to the above-mentioned TSP signal acquisition process) is designed within the predetermined time when the clock signal is suspended, It realizes the staggering of the predetermined time of suspending the work of the touch screen panel in adjacent odd and even frames, thereby solving the problem of dark lines appearing to human eyes.

To sum up, the utility model sets delay displacement modules at different positions, and at least two groups of switch elements in the switch control module control whether they work, so as to achieve the effect of staggering adjacent frame panels to suspend work for a predetermined time. The utility model can stagger the position where the touch screen panel suspends work for a predetermined time in adjacent odd and even frames, thereby solving the problem of dark lines appearing to human eyes.

It should be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is a relationship between these entities or operations. There is no such actual relationship or order between them. Moreover, the term "comprises", "comprises" or any other variation thereof is intended to cover a non-exclusive inclusion such that an article or device comprising a set of elements includes not only those elements but also other elements not expressly listed, Or also include elements inherent in the article or device. Without further limitations, an element defined by the phrase "comprising a" does not exclude the presence of additional identical elements in the article or device comprising said element.

The above embodiments are only used to illustrate the technical solutions of the present utility model, and are not intended to limit it; although the utility model has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: it can still be applied to the foregoing embodiments The technical solutions described in the examples are modified, or some of the technical features are equivalently replaced; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims (7)

1. a gate driver circuit, comprises and it is characterized in that multiple shift register cells of cascade, and described gate driver circuit also comprises:

At least two time delay displacement modules and the switch control module being connected with described time delay displacement module respectively, described time delay displacement module, between adjacent shift register cell, and also has the shift register cell of at least one cascade between described time delay displacement module;

Described switch control module is for being linked between adjacent shift register cell controlling two different time delay displacement modules between consecutive frame, and in each frame, makes grid line drive the transmission of signal to skip the time delay displacement module that other do not access;

Described time delay displacement module for suspending the schedule time by the clock signal being connected with described time delay displacement module in the time accessing adjacent shift register cell, and in the schedule time of suspending in described clock signal, storage drives signal from the described grid line of adjacent previous stage shift register cell, and drive signal to pass to the shift register cell of adjacent rear one-level described grid line after recovering clock signals.

2. gate driver circuit according to claim 1, it is characterized in that, described switch control module comprises one group of on-off element corresponding to each described time delay displacement module, every group of on-off element is used for to the time delay displacement module output switch control signal corresponding with it, control this time delay displacement module and be linked between adjacent shift register cell, or make grid line drive the transmission of signal to skip this time delay displacement module.

3. gate driver circuit according to claim 2, it is characterized in that, every group of on-off element comprises the first on-off element and second switch element, in wherein one group of on-off element at corresponding time delay displacement module between N-1 level and N level shift register cell, the first end of the first on-off element, second switch element is all connected with the output terminal of described N-1 level shift register cell; And the second end of the first on-off element is connected with the input end of this time delay displacement module; The output terminal of this time delay displacement module is connected with the input end of described N level shift register cell; The second end of second switch element is connected with the output terminal of described N level shift register cell; The control end of the first on-off element is connected with the first control signal wire, and the control end of second switch element is connected with the second control signal wire.

4. according to the gate driver circuit described in claim 2 or 3, it is characterized in that, described on-off element is thin film field-effect pipe.

5. gate driver circuit according to claim 3, it is characterized in that, described time delay displacement module comprises the first shift register cell and second shift register cell of cascade, two shift register cell levels are coupled between N-1 level and N level shift register cell, the input end of the first shift register cell is as the input end of this time delay displacement module, the output terminal of the second shift register cell is as the output terminal of this time delay displacement module, the input end of the first shift register cell is connected with the output terminal of N-1 level shift register cell by the first on-off element, and the output terminal of the first shift register cell, the output terminal of the reset terminal of the second shift register cell and described N level shift register cell, the reset terminal of N-1 level shift register cell is connected in a bit, described N is not less than 2 integer.

6. an array base palte, is characterized in that, this array base palte comprises the gate driver circuit as described in any one in claim 1 to 5.

7. a display device, is characterized in that, this display device comprises array base palte as claimed in claim 6.