CN214068732U

CN214068732U - Array substrate and display device

Info

Publication number: CN214068732U
Application number: CN202022411309.3U
Authority: CN
Inventors: 马健; 任文明
Original assignee: BOE Technology Group Co Ltd; Hefei Xinsheng Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Hefei Xinsheng Optoelectronics Technology Co Ltd
Priority date: 2020-10-23
Filing date: 2020-10-23
Publication date: 2021-08-27
Anticipated expiration: 2030-10-23

Abstract

The present application discloses an array substrate and a display device, which belong to the technical field of display. The array substrate includes: a substrate, and a TFT, a first passivation layer and a transparent display electrode on the substrate. There is only a first passivation layer between the transparent display electrode and the active layer pattern in the TFT. In this way, there is no organic insulating layer in the array substrate, which effectively simplifies the film layer structure of the array substrate and further simplifies the array substrate. The manufacturing process of the substrate and the manufacturing cost of the array substrate are reduced. And because the orthographic projection of the transparent display electrode on the substrate and the orthographic projection of the active layer pattern in the TFT on the substrate do not have an overlapping area, even if the distance between the transparent display electrode and the active layer pattern is small , the voltage loaded on the transparent display electrode has little effect on the turn-on and turn-off of the TFT.

Description

Array substrate and display device

Technical Field

The present disclosure relates to display technologies, and particularly to an array substrate and a display device.

Background

With the development of the display technology field, various products with display functions, such as mobile phones, tablet computers, televisions, notebook computers, digital photo frames, navigators and the like, are present in daily life, and the display panels need to be assembled on the products without exception.

Currently, most display panels may include an array substrate, a color filter substrate, and a liquid crystal layer located between the array substrate and the color filter substrate. The array substrate may include: the Thin Film Transistor (TFT) comprises a Thin Film Transistor (TFT), a first passivation layer for coating the TFT, and an organic insulating layer, a common electrode, a second passivation layer and a pixel electrode which are stacked on the first passivation layer, wherein the pixel electrode can be electrically connected with the TFT.

However, the number of film structures on the array substrate is large, which results in a complicated manufacturing process and a high manufacturing cost.

SUMMERY OF THE UTILITY MODEL

The embodiment of the application provides an array substrate and a display device. The problems that the manufacturing of the current array substrate is complex and the manufacturing cost is high can be solved, and the technical scheme is as follows:

in one aspect, an array substrate is provided, including:

a substrate;

a thin film transistor on the substrate, the thin film transistor comprising: an active layer pattern;

the first passivation layer is positioned on the thin film transistor and wraps the thin film transistor;

the transparent display electrode is positioned on the first passivation layer, is in contact with one side, far away from the thin film transistor, of the first passivation layer, and has a hollow area, and the orthographic projection of the active layer pattern on the substrate is positioned in the orthographic projection of the hollow area on the substrate, wherein the transparent display electrode is a common electrode or a pixel electrode;

and the no-load protection electrode is positioned in the hollow-out area and separated from the transparent display electrode, the no-load protection electrode has conductivity, the no-load protection electrode is in contact with one side of the first passivation layer, which is far away from the thin film transistor, and an overlapping area exists between the orthographic projection of the no-load protection electrode on the substrate and the orthographic projection of the active layer pattern on the substrate.

Optionally, an orthographic projection of the active layer pattern on the substrate is located within an orthographic projection of the idle protection electrode on the substrate.

Optionally, the transparent display electrode and the idle load protection electrode are arranged in the same layer and made of the same material.

Optionally, the thin film transistor is a bottom gate thin film transistor or a top gate thin film transistor.

Optionally, a minimum distance between a boundary of an orthographic projection of the unloaded guard electrode on the substrate and a boundary of an orthographic projection of the active layer pattern on the substrate is greater than or equal to 2 micrometers.

Optionally, the thin film transistor further includes: the grid electrode is positioned on one side, close to the substrate, of the active layer pattern, the grid electrode insulating layer is positioned between the grid electrode and the active layer pattern, the source drain electrode is positioned on one side, far away from the substrate, of the active layer pattern, and the source drain electrode is in lap joint with the active layer pattern;

the transparent display electrode is a common electrode, and the array substrate further includes: and the common electrode wire is arranged on the same layer as the grid electrode, the grid electrode insulating layer and the first passivation layer are provided with first through holes, and the common electrode wire is lapped with the common electrode through the first through holes.

Optionally, the array substrate further includes: the second passivation layer is positioned on the transparent display electrode and the no-load protection electrode, the pixel electrode is positioned on the second passivation layer, the pixel electrode is in contact with one side, far away from the common electrode, of the second passivation layer, the first passivation layer and the second passivation layer are provided with second through holes, and the pixel electrode is electrically connected with the source and the drain electrodes through the second through holes.

In another aspect, an array substrate is provided, including:

a substrate;

the transparent display electrode is positioned on the first passivation layer, is in contact with one side, far away from the thin film transistor, of the first passivation layer, and has a hollow area, and the orthographic projection of the active layer pattern on the substrate is positioned in the orthographic projection of the hollow area on the substrate, wherein the transparent display electrode is a common electrode or a pixel electrode.

Optionally, a minimum distance between a boundary of an orthographic projection of the hollowed-out region on the substrate and a boundary of an orthographic projection of the active layer on the substrate is greater than or equal to 2 micrometers.

In still another aspect, there is provided a display device including: the array substrate is provided.

The beneficial effects brought by the technical scheme provided by the embodiment of the application at least comprise:

the array substrate may include: the display device comprises a substrate, and a TFT, a first passivation layer, a transparent display electrode and a no-load protection electrode which are positioned on the substrate. Only the first passivation layer exists between the transparent display electrode and the active layer pattern in the TFT, so that an organic insulating layer does not exist in the array substrate, the film structure of the array substrate is effectively simplified, the manufacturing process of the array substrate is further simplified, and the manufacturing cost of the array substrate is reduced. And because there is no overlapping area between the orthographic projection of the transparent display electrode on the substrate and the orthographic projection of the active layer pattern in the TFT on the substrate, even if the distance between the transparent display electrode and the active layer pattern is small, the voltage loaded on the transparent display electrode has little influence on the on and off of the TFT. Therefore, the influence of the charging rate when the pixel electrode is charged subsequently is small, so that the brightness of a subsequent display picture is high, and the display effect of the subsequent display picture is effectively improved. Meanwhile, the no-load protection electrode is separated from the transparent display electrode, and the voltage loaded on the transparent display electrode cannot be transmitted to the no-load protection electrode, so that the no-load protection electrode with the conductive performance can play a certain shielding role on an external electric field, the probability of interference of the external electric field on the TFT is effectively reduced, the electrical performance of the TFT is further improved, the charging rate of the pixel electrode during subsequent charging is improved, and the display effect of the subsequent display picture is further improved.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is a top view of an array substrate;

FIG. 2 is a schematic diagram of a film structure of the array substrate shown in FIG. 1 at A-A';

FIG. 3 is a schematic view of another film structure of the array substrate shown in FIG. 1 at A-A';

fig. 4 is an equivalent schematic view of a TFT in the array substrate shown in fig. 3;

fig. 5 is a characteristic graph when different voltages are applied to two gates in the TFT shown in fig. 4;

fig. 6 is a timing diagram of voltages applied to respective electrodes in the array substrate of fig. 2 and 3;

fig. 7 is a top view of an array substrate according to an embodiment of the present disclosure;

FIG. 8 is a schematic view of a film structure of the array substrate shown in FIG. 7 at A-A';

FIG. 9 is a schematic diagram of a position relationship between a transparent display electrode and an idle-load protection electrode according to an embodiment of the present disclosure;

FIG. 10 is a schematic diagram of a position relationship between another transparent display electrode and an idle-load protection electrode provided in an embodiment of the present application;

fig. 11 is a top view of another array substrate provided in the embodiments of the present application;

FIG. 12 is a schematic view of a film structure of the array substrate shown in FIG. 11 at A-A';

fig. 13 is a top view of an array substrate according to another embodiment of the present application;

FIG. 14 is a schematic view of a film structure of the array substrate shown in FIG. 13 at A-A';

fig. 15 is a top view of another array substrate according to another embodiment of the present application;

fig. 16 is a schematic view of a film structure of the array substrate shown in fig. 15 at a-a'.

Detailed Description

To make the objects, technical solutions and advantages of the present application more clear, embodiments of the present application will be described in further detail below with reference to the accompanying drawings.

Referring to fig. 1 and 2, fig. 1 is a top view of an array substrate, and fig. 2 is a schematic diagram of a film structure of the array substrate shown in fig. 1 at a-a'. The array substrate may include: the liquid crystal display device includes a substrate 01, and a TFT02, a first passivation layer 03, an organic insulating layer 04, a common electrode 05, a second passivation layer 06, and a pixel electrode 07 which are stacked on the substrate 01.

The TFT02 may include: a gate electrode 021, a gate insulating layer 022, an active layer pattern 023, a source electrode 024, and a drain electrode 025. The gate insulating layer 022 is disposed between the gate electrode 021 and the active layer pattern 023, and the source electrode 024 and the drain electrode 025 are electrically connected to the active layer pattern 023. The pixel electrode 07 may be electrically connected to one of the source 024 and the drain 025 in the TFT 02.

In order to simplify the manufacturing method of the array substrate shown in fig. 1 and reduce the cost of the array substrate, as shown in fig. 3, the organic insulating layer in the array substrate may be removed. However, after the organic insulating layer in the array substrate is removed, the distance between the common electrode 05 and the active layer pattern 023 in the TFT02 is small, and the voltage loaded on the common electrode 05 influences the turn-on and turn-off of the TFT 02.

For example, in fig. 2, the distance between the common electrode 05 and the active layer pattern 023 in the TFT02 is the sum of the thickness of the first passivation layer 03 (about 3000 angstroms) and the thickness of the organic insulating layer 04 (about 25000 angstroms), and the distance between the common electrode 05 and the active layer pattern 023 is large, which does not affect the TFT 02. In fig. 3, the distance between the common electrode 05 and the active layer pattern 023 in the TFT02 is only the thickness of the first passivation layer 03, and the distance between the common electrode 05 and the active layer pattern 023 is small, which may affect the TFT 02.

When the distance between the common electrode 05 and the active layer pattern 023 in the TFT02 is small, the TFT02 is equivalent to a TFT of a dual gate type. Referring to fig. 4, fig. 4 is an equivalent schematic diagram of a TFT in the array substrate shown in fig. 3. The TFT02 has two gates (gate 021 and common electrode 05, respectively). According to the operating principle of the double-gate TFT, when the voltages applied to the two gates of the double-gate TFT are both greater than 0, the TFT02 has a promoting effect on charging the pixel electrode; when the voltages loaded on the two gates in the double-gate type TFT are both less than 0, the TFT02 has a suppression effect on the leakage current between the source 024 and the drain 025; when the product of the voltages applied to the two gates in the dual-gate TFT is smaller than 0, that is, the voltage applied to one gate is larger than 0, and the voltage applied to the other gate is smaller than 0, the two gates are inhibited from each other, which may affect the on and off of the TFT 02.

Referring to fig. 5, fig. 5 is a graph showing characteristics when different voltages are applied to two gates of the TFT shown in fig. 4. The abscissa represents a constant voltage (potential: volts) applied to the gate electrode 021, and the ordinate represents a channel current in the active layer pattern 023 in the TFT. The three curves in fig. 5 are represented as: when the common electrode 05 is applied with a constant voltage greater than 0 (e.g., +4.6 volts), the characteristic curve of the TFT; when the common electrode 05 is applied with a constant voltage less than 0 (e.g., -4.6 volts), the characteristic curve of the TFT; when the common electrode 05 is not applied with a voltage, the characteristic curve of the TFT.

As can be seen from fig. 5, when the common electrode 05 is not applied with a voltage, it does not affect the TFT02, and when the TFT02 normally operates, the TFT02 is turned on when a positive voltage is applied to the gate 023. If a positive voltage is applied to the common electrode 05, the TFT02 is subjected to the positive voltage applied to the common electrode 05 before being controlled by the gate 023, so that the TFT02 is turned on early; if a negative voltage is applied to the common electrode 05, the TFT02 is delayed to be turned on by the negative voltage applied to the common electrode 05 before being controlled by the gate 023.

As can be seen from the above, when the distance between the common electrode 05 and the active layer pattern 023 in the TFT02 is small, the voltage loaded on the common electrode 05 affects the TFT02 to turn on and off.

If the on and off of the TFT02 is affected by the common electrode 05, the TFT02 may affect the charging rate of the pixel electrode 07.

For example, referring to fig. 6, fig. 6 is a timing diagram of voltages applied to each electrode in the array substrate of fig. 2 and 3.

Vg represents the voltage applied to the gate 021 in the TFT 02. The Vg can determine the turn-on and turn-off of the TFT02, for example, when it is high, the TFT02 is turned on; when it is low, the TFT02 is turned off.

Vcom represents the voltage applied to the common electrode. The Vcom is typically a constant voltage.

Vd represents the voltage applied to the drain 025 in the TFT 02. The Vd is used to charge the pixel electrode 07. When Vd is at a high level, after the pixel electrode 07 is charged, the liquid crystal molecules can be deflected in one direction by the combined action of the pixel electrode 07 and the common electrode 06; when Vd is at a low level, liquid crystal molecules can be deflected in the other direction by the pixel electrode 07 and the common electrode 06 after the pixel electrode 07 is charged.

Vs represents the voltage applied to the source electrode in the TFT02, and when the TFT02 is conductive, the signal Vs gradually transitions from the same voltage applied to the common electrode to the same voltage applied to the drain electrode to effect charging of the pixel electrode 07.

In connection with the timing of the voltages applied to the respective electrodes in the array substrate shown in fig. 6, it is assumed that the values of the voltages applied to the respective electrodes in the first charging period and the second charging period are as shown in table 1.

TABLE 1

	Vg (Unit: volt)	Vcom (Unit: volt)	Vd (Unit: volt)	Vg (Unit: volt)
					First charge cycle	20	4.6	9.4	4.6→9.4
Second charge cycle	20	4.6	0.2	4.6→0.2

As can be seen from table 1, in the first charging period, Vg is 20 v, the TFT is turned on, Vd is 9.4 v, and Vg can be gradually changed from 4.6 v to 9.4 v, so that the voltage on the pixel electrode 07 can be 9.4 v, and the liquid crystal molecules are deflected in one direction under the combined action of the pixel electrode 07 and the common electrode 05 with the voltage of 4.6 v. In the second charging period, Vg is 20 v, the TFT is turned on, Vd is 0.2 v, and Vg can be gradually changed from 4.6 v to 0.2 v, so that the voltage on the pixel electrode 07 can be 0.2 v, and the liquid crystal molecules are deflected toward the other direction under the combined action of the pixel electrode 07 and the common electrode 05 with the voltage of 4.6 v.

For the array substrate shown in fig. 2 and 3, when the voltage timing shown in fig. 6 is applied to each electrode in the array substrate, the values of the channel current of the TFT02 in the array substrate at the initial time and the pixel electrode 07 charged by 50% are shown in table 2.

TABLE 2

As can be seen from table 2, for the first charging period, when the channel current of the TFT02 in the array substrate shown in fig. 2 starts to reach a value of 50% of the charging time of the pixel electrode 07, the channel current is reduced from 3.5 microampere to 1.8 microampere, and the channel current is lost by 49%; the channel current of the TFT02 in the array substrate shown in fig. 2 is initially reduced from 2.7 microampere to 0.8 microampere by 50% of the charging time of the pixel electrode 07, and 70% of the channel current is lost.

Therefore, if the array substrate is not provided with the organic insulating layer, the common electrode 05 in the array substrate is closer to the active layer pattern 023 in the TFT02, and a voltage applied to the common electrode 05 affects on and off of the TFT02, so that a channel current of the TFT02 is greatly lost in a process of charging the pixel electrode 07, and thus, a charging rate is insufficient when the pixel electrode 07 is charged, and finally, luminance of a subsequently displayed picture is low.

For example, as shown in table 2, the brightness of the display device manufactured by using the array substrate shown in fig. 2 is 410 nits when the gray scale is 255 pictures; the brightness of the display device manufactured by using the array substrate shown in fig. 3 is 360 nits when the gray scale is 255 pictures. Therefore, after the organic insulating layer is removed, the luminance of the subsequent display screen is lost by about 12% under the influence of the common electrode 05.

Referring to fig. 7 and 8, fig. 7 is a top view of an array substrate according to an embodiment of the present disclosure, and fig. 8 is a schematic diagram of a film structure of the array substrate shown in fig. 7 at a-a'. The array substrate 000 may include:

a substrate 100, and a TFT 200, a first passivation layer 300, a transparent display electrode 400, and a dummy protection electrode 500 on the substrate 100.

The TFT 200 may include: an active layer pattern 201.

The first passivation layer 300 may be on the TFT 200, and the passivation layer 300 may cover the TFT 200.

The transparent display electrode 400 may be positioned on the first passivation layer 300, and the transparent display electrode 400 may be in contact with a side of the first passivation layer 300 away from the TFT 200. In the present application, the transparent display electrode 400 may have a hollow area 400 a. An orthogonal projection of the active layer pattern 201 in the TFT 200 on the substrate 100 may be located within an orthogonal projection of the hollow area 400a in the transparent display electrode 400 on the substrate 100. As such, there is no overlapping area of the orthographic projection of the transparent display electrode 400 on the substrate 100 and the orthographic projection of the active layer pattern 201 in the TFT 200 on the substrate 100.

In this application, the transparent display electrode 400 may be a common electrode in the array substrate 000, or may be a pixel electrode in the array substrate 000. For example, when the transparent display electrode 400 is a common electrode, the pixel electrode in the array substrate 000 is located on a side of the transparent display electrode 400 away from the substrate 100; when the transparent display electrode 400 is a pixel electrode, the common electrode in the array substrate 000 is located on a side of the transparent display electrode 400 away from the substrate 100.

The dummy protection electrode 500 has a conductive property, the dummy protection electrode 500 may be on the first passivation layer 300, and the dummy protection electrode 500 may contact a side of the first passivation layer 300 away from the TFT 200. For example, the idle-load protection electrode 500 may be located in the hollow area 400a, and the idle-load protection electrode 500 is isolated from the transparent display electrode 400. An overlapping region may exist between an orthographic projection of the idle protection electrode 500 on the substrate 100 and an orthographic projection of the active layer pattern 201 in the TFT 200 on the substrate 100.

In the embodiment of the present application, there is no overlap region due to the orthographic projection of the transparent display electrode 400 on the substrate 100 and the orthographic projection of the active layer pattern 201 in the TFT 200 on the substrate 100. Therefore, even if the insulating layer between the transparent display electrode 400 and the active layer pattern 201 is only the first passivation layer 300 (i.e., the distance between the transparent display electrode 400 and the active layer pattern 201 is small), the voltage applied to the transparent display electrode 400 has a small influence on the turn-on and turn-off of the TFT 200. Therefore, the influence of the charging rate when the pixel electrode is charged subsequently is small, so that the brightness of a subsequent display picture is high, and the display effect of the subsequent display picture is effectively improved.

In the present application, the idle-driving protection electrode 500 is isolated from the transparent display electrode 400, and therefore, the voltage applied to the transparent display electrode 400 is not transmitted to the idle-driving protection electrode 500. In a possible implementation manner, the idle protection electrode 500 is not only isolated from the transparent display electrode 400, but also isolated from any conductive medium in the array substrate 000, so that no voltage is loaded in the idle protection electrode 500, which has a small influence on the turn-on and turn-off of the TFT 200. In another possible implementation manner, the dummy protection electrode 500 may overlap with a conductive medium in the array substrate 000 for connecting to a ground terminal, so that even if the dummy protection electrode 500 is connected to the conductive medium in the array substrate 000, the dummy protection electrode 500 is grounded through the conductive medium, and a voltage of 0 v is applied to the dummy protection electrode 500, which has a small influence on the turn-on and turn-off of the TFT 200.

Since the no-load protection electrode 500 has conductive performance, the no-load protection electrode 500 can shield an external electric field to a certain extent, so as to effectively reduce the probability of interference of the external electric field on the TFT 200, and further improve the electrical performance of the TFT 200, so as to improve the charging rate when the pixel electrode is subsequently charged, and further improve the display effect when a subsequent display screen is subsequently displayed.

To sum up, the array substrate provided by the embodiment of the present application includes: the display device comprises a substrate, and a TFT, a first passivation layer, a transparent display electrode and a no-load protection electrode which are positioned on the substrate. Only the first passivation layer exists between the transparent display electrode and the active layer pattern in the TFT, so that an organic insulating layer does not exist in the array substrate, the film structure of the array substrate is effectively simplified, the manufacturing process of the array substrate is further simplified, and the manufacturing cost of the array substrate is reduced. And because there is no overlapping area between the orthographic projection of the transparent display electrode on the substrate and the orthographic projection of the active layer pattern in the TFT on the substrate, even if the distance between the transparent display electrode and the active layer pattern is small, the voltage loaded on the transparent display electrode has little influence on the on and off of the TFT. Therefore, the influence of the charging rate when the pixel electrode is charged subsequently is small, so that the brightness of a subsequent display picture is high, and the display effect of the subsequent display picture is effectively improved. Meanwhile, the no-load protection electrode is separated from the transparent display electrode, and the voltage loaded on the transparent display electrode cannot be transmitted to the no-load protection electrode, so that the no-load protection electrode with the conductive performance can play a certain shielding role on an external electric field, the probability of interference of the external electric field on the TFT is effectively reduced, the electrical performance of the TFT is further improved, the charging rate of the pixel electrode during subsequent charging is improved, and the display effect of the subsequent display picture is further improved.

Alternatively, as shown in fig. 7 and 8, an orthogonal projection of the active layer pattern 201 in the TFT 200 in the array substrate 000 on the substrate 100 may be located in an orthogonal projection of the idle reduction electrode 500 on the substrate 100. Thus, the idle-load protection electrode 500 can better protect the TFT 200 from being interfered by an external electric field.

To clearly see the position relationship between the transparent display electrode 400 and the idle protection electrode 500 in the array substrate 000, please refer to fig. 9 and 10, fig. 9 is a schematic diagram of a position relationship between the transparent display electrode and the idle protection electrode according to an embodiment of the present disclosure, and fig. 10 is a schematic diagram of a position relationship between the transparent display electrode and the idle protection electrode according to another embodiment of the present disclosure. The minimum distance between the boundary of the orthographic projection of the dummy guard electrode 500 on the substrate 100 and the boundary of the orthographic projection of the active layer pattern 201 in the TFT 200 on the substrate 100 is greater than or equal to 2 μm. In this case, even if there is a manufacturing deviation in each film layer during the manufacturing process of the array substrate, it is possible to ensure that there is no overlapping area of the orthographic projection of the transparent display electrode 400 on the substrate 100 with the orthographic projection of the active layer pattern 201 on the substrate 100. Note that the distance between the boundary of the orthographic projection of the idle reduction electrode 500 on the substrate 100 and the boundary of the orthographic projection of the active layer pattern 201 in the TFT 200 on the substrate 100 is generally required to be less than or equal to 5 μm.

It should be noted that there are various structures of the idle-loaded guard electrode 500 in the array substrate 000, and the embodiment of the present application is schematically illustrated by taking the following two possible implementation manners as examples:

in a first possible implementation, as shown in fig. 9, the idle protection electrode 500 may be a planar electrode.

In a second possible implementation, as shown in fig. 10, the idle protection electrode 500 may be a patterned electrode. Illustratively, the idle guard electrode 500 may have a slit structure 501 thereon.

Note that, since the common electrode in the array substrate 000 is generally a planar electrode, the pixel electrode is generally a patterned electrode, and the pixel electrode is also generally provided with a slit structure. Therefore, in order to simplify the patterning process, when the transparent display electrode 400 on the first passivation layer 300 is a common electrode, the structure of the idle-load protection electrode 500 on the first passivation layer 300 may be the structure in the first possible implementation manner; when the transparent display electrode 400 on the first passivation layer 300 is a pixel electrode, the dummy protection electrode 500 on the first passivation layer 300 may have the structure of the second possible implementation manner.

Alternatively, the material of the active layer pattern 201 in the TFT 200 may include: oxide semiconductor material, for example. The oxide semiconductor material may be: indium Gallium Zinc Oxide (IGZO).

In an alternative implementation, the idle protection electrode 500 on the first passivation layer 300 is disposed on the same layer as the transparent display electrode 400 and is made of the same material. Thus, the transparent display electrode 400 and the dummy protection electrode 500 are formed by the same patterning process, which can further simplify the manufacturing process of the array substrate 000 and reduce the manufacturing cost of the array substrate 000.

In this case, since the material of the transparent display electrode 400 is usually selected from transparent conductive materials with conductive properties, for example, the material of the transparent display electrode 400 usually includes Indium Tin Oxide (ITO), and thus the material of the idle reduction protection electrode 500 also includes ITO. And ITO has better absorption effect on ultraviolet rays with shorter wavelength. In this way, when there is an overlapping region between the orthographic projection of the dummy protection electrode 500 on the substrate 100 and the orthographic projection of the active layer pattern 201 on the substrate 100, the dummy protection electrode 500 can absorb ultraviolet rays, so as to prevent the active layer pattern 201 made of an oxide semiconductor material from being directly irradiated by the ultraviolet rays, thereby reducing the probability of the influence of the light rays on the on and off of the TFT 200.

In another possible implementation, the idle protection electrode 500 on the first passivation layer 300 is generally disposed with the transparent display electrode 400, but the material of the transparent display electrode 500 may be different from that of the idle protection electrode 400.

In this case, the idle protection electrode 400 may be made of a conductive material having a light shielding property, for example, the idle protection electrode 400 may include a metal material. Thus, when there is an overlapping region between the orthographic projection of the idle protection electrode 500 on the substrate 100 and the orthographic projection of the active layer pattern 201 on the substrate 100, the idle protection electrode 500 can shield external light, so as to prevent the external light from directly irradiating the active layer pattern 201 made of the oxide semiconductor material, thereby reducing the probability of influence of the light on the on and off of the TFT 200.

Optionally, the TFT 200 in the array substrate 000 in the present application may be a bottom gate TFT or a top gate TFT. The following embodiments are schematically illustrated by taking the TFT 200 in the array substrate 000 as a bottom gate type TFT and the transparent display electrode 400 in the array substrate 000 as a common electrode.

Referring to fig. 11 and 12, fig. 11 is a top view of another array substrate provided in an embodiment of the present application, and fig. 12 is a schematic diagram of a film structure of the array substrate shown in fig. 11 at a-a'. The TFT 200 in the array substrate 000 may further include: a gate 202, a gate insulating layer 203, and source and drain electrodes 204 (also referred to as source and drain). The gate electrode 202 in the TFT 200 is located on a side of the active layer pattern 201 close to the substrate 100, and the gate insulating layer 203 is located between the gate electrode 202 and the active layer pattern 201. The source and drain electrodes 204 are located on a side of the active layer pattern 201 away from the substrate 100, and the source and drain electrodes 204 overlap the active layer pattern 201.

In an embodiment of the present application, the array substrate 000 may further include: a gate line 600 electrically connected to the gate electrode 202 of the TFT 200 and disposed at the same layer as the gate electrode, and a data line 700 electrically connected to the source and drain electrodes 204 and disposed at the same layer as the source and drain electrodes. For example, the data line 700 may be electrically connected to one of the source and drain electrodes. The extending direction of the data line 700 may cross the extending direction of the gate line 600.

In this application, the array substrate 000 may further include: a second passivation layer 800 on the transparent display electrode 400 and the idle protection electrode 500, and a pixel electrode 900 on the second passivation layer 800. The pixel electrode 900 may be in contact with a side of the second passivation layer 800 away from the transparent display electrode 400. The first passivation layer 300 and the second passivation layer 800 in the array substrate 000 have the second via hole V2. The pixel electrode 900 may be electrically connected to the source and drain electrodes 204 in the TFT02 through the second via hole V2. For example, the pixel electrode 900 may be electrically connected to the other of the source and drain electrodes through the second via hole V2.

In the array substrate 000, the number of the gate lines 600, the number of the data lines 700, and the number of the pixel electrodes 900 are all plural. Also, the plurality of gate lines 600 may be arranged in parallel, and the plurality of data lines 700 may also be arranged in parallel. Each pixel electrode 900 may be located in an area surrounded by any two adjacent gate lines 600 and any two adjacent data lines 700.

Optionally, the material of the pixel electrode 900 in the array substrate 000 may include: and (3) ITO. In this application, the pixel electrode 900 has a plurality of stripe-shaped slit structures 901. In this way, the slit structure 901 can improve the transmittance of light emitted from the array substrate 000.

In the embodiment of the present application, when the insulating layer between the transparent display electrode 400 and the active layer pattern 201 is only the first passivation layer 300, the distance between the transparent display electrode 400 and the data line 700 is small, and the voltage applied to the data line 700 may affect the voltage applied to the transparent display electrode 400, so that the voltages at various positions on the transparent display electrode 400 may have differences, and the uniformity of the voltage applied to the transparent display electrode 400 is poor.

In order to improve the uniformity of the voltage applied to the transparent display electrode 400, the array substrate 000 may further include: and a common electrode line 1000 disposed in layer with the gate 202. The gate insulating layer 203 and the first passivation layer 300 in the array substrate 000 have a first via V1, and the common electrode line 1000 in the array substrate 000 may overlap the transparent display electrode 400 through the first via V1. The common electrode line 1000 may be made of a metal material having a relatively low resistivity, so that the common electrode line 1000 applies a voltage to the transparent display electrode 400, thereby reducing voltage differences at various positions on the transparent display electrode 400, and improving uniformity of the voltage applied to the transparent display electrode 400.

Alternatively, in the array substrate 000, the extending direction of the common electrode line 1000 may be parallel to the extending direction of the gate line 600.

Alternatively, in the array substrate 000, the gate electrode 202, the common electrode line 1000, and the gate line 600 in the TFT 200 are fabricated from the same conductive layer. That is, the gate electrode 202, the common electrode line 1000, and the gate line 600 are formed through the same patterning process. Thus, the manufacturing process of the array substrate 000 can be further simplified, and the manufacturing cost of the array substrate 000 can be reduced. In the array substrate 000, the source and drain electrodes 203 in the TFT 200 are fabricated from the same conductive layer as the data line 700. That is, the source and drain electrodes 203 and the data line 700 are formed through the same patterning process. Thus, the manufacturing process of the array substrate 000 can be further simplified, and the manufacturing cost of the array substrate 000 can be reduced.

In the embodiment of the present application, the data line 700 in the display panel 000 may include: a data line body 701 and a jumper data line 702 connected to each other. There is an overlapping area between the orthogonal projection of the cross data line 702 on the substrate 100 and the orthogonal projection of the common electrode line 1000 or the gate line 600 on the substrate. The width of the jumper data line 702 is greater than the width of the data line body 701. In the present application, when the width of the cross-over data line 702 in the data line 700, which is used to overlap with the gate line 600 or the common electrode line 1000, is large, the risk of line breakage of the data line 700 at the overlapping position with the gate line 600 or the common electrode line 1000 can be effectively reduced.

Referring to fig. 13 and 14, fig. 13 is a top view of an array substrate according to another embodiment of the present disclosure, and fig. 14 is a schematic diagram of a film structure of the array substrate shown in fig. 13 at a-a'. The array substrate 000 may include:

a substrate 100, and a TFT 200, a first passivation layer 300, and a transparent display electrode 400 on the substrate 100.

The transparent display electrode 400 may be positioned on the first passivation layer 300, and the transparent display electrode 400 may be in contact with a side of the first passivation layer 300 away from the TFT 200. In the present application, the transparent display electrode 400 may have a hollow area 400 a. An orthogonal projection of the active layer pattern 201 in the TFT 200 on the substrate 100 may be located within an orthogonal projection of the hollow area 400a on the substrate 100. As such, there is no overlapping area of the orthographic projection of the transparent display electrode 400 on the substrate 100 and the orthographic projection of the active layer pattern 201 in the TFT 200 on the substrate 100.

To sum up, the array substrate provided by the embodiment of the present application includes: the display device includes a substrate, and a TFT, a first passivation layer and a transparent display electrode on the substrate. Only the first passivation layer exists between the transparent display electrode and the active layer pattern in the TFT, so that an organic insulating layer does not exist in the array substrate, the film structure of the array substrate is effectively simplified, the manufacturing process of the array substrate is further simplified, and the manufacturing cost of the array substrate is reduced. And because there is no overlapping area between the orthographic projection of the transparent display electrode on the substrate and the orthographic projection of the active layer pattern in the TFT on the substrate, even if the distance between the transparent display electrode and the active layer pattern is small, the voltage loaded on the transparent display electrode has little influence on the on and off of the TFT. Therefore, the influence of the charging rate when the pixel electrode is charged subsequently is small, so that the brightness of a subsequent display picture is high, and the display effect of the subsequent display picture is effectively improved.

Alternatively, as shown in fig. 13 and 14, a minimum distance between a boundary of an orthogonal projection of the hollow area 400a in the transparent display electrode 400 on the first passivation layer 300 on the substrate 100 and a boundary of an orthogonal projection of the active layer pattern 201 in the TFT 200 on the substrate 100 is greater than or equal to 2 micrometers. In this case, even if there is a manufacturing deviation in each film layer during the manufacturing process of the array substrate, it is possible to ensure that there is no overlapping area of the orthographic projection of the transparent display electrode 400 on the substrate 100 with the orthographic projection of the active layer pattern 201 on the substrate 100. Note that, the distance between the boundary of the orthographic projection of the hollow area 400a on the substrate 100 and the boundary of the orthographic projection of the active layer pattern 201 in the TFT 200 on the substrate 100 is generally required to be less than or equal to 5 micrometers.

Referring to fig. 15 and 16, fig. 15 is a top view of another array substrate according to another embodiment of the present disclosure, and fig. 16 is a schematic diagram of a film structure of the array substrate shown in fig. 15 at a-a'. The TFT 200 in the array substrate 000 may further include: a gate 202, a gate insulating layer 203, and source and drain electrodes 204 (also referred to as source and drain). The gate electrode 202 in the TFT 200 is located on a side of the active layer pattern 201 close to the substrate 100, and the gate insulating layer 203 is located between the gate electrode 202 and the active layer pattern 201. The source and drain electrodes 204 are located on a side of the active layer pattern 201 away from the substrate 100, and the source and drain electrodes 204 overlap the active layer pattern 201.

In this application, the array substrate 000 may further include: a second passivation layer 800 on the transparent display electrode 400, and a pixel electrode 900 on the second passivation layer 800. The pixel electrode 900 may be in contact with a side of the second passivation layer 800 away from the transparent display electrode 400. The first passivation layer 300 and the second passivation layer 800 in the array substrate 000 have the second via hole V2. The pixel electrode 900 may be electrically connected to the source and drain electrodes 204 in the TFT02 through the second via hole V2. For example, the pixel electrode 900 may be electrically connected to the other of the source and drain electrodes through the second via hole V2.

The embodiment of the application provides a manufacturing method of an array substrate. The manufacturing method of the array substrate is used for manufacturing the array substrate shown in fig. 7. The manufacturing method of the array substrate may include:

step a1, a TFT is formed on a substrate. The TFT may include: an active layer pattern.

Step B1, forming a first passivation layer on the TFT. The first passivation layer covers the TFT.

And step C1, forming a transparent display electrode on the first passivation layer. The transparent display electrode is in contact with one side, far away from the TFT, of the first passivation layer, the transparent display electrode is provided with a hollow area, and the orthographic projection of the active layer pattern in the TFT on the substrate is located in the orthographic projection of the hollow area on the substrate.

And D1, forming an idle protection electrode separated from the transparent display electrode in the hollow area. The no-load protection electrode has a conductive performance, the no-load protection electrode is in contact with one side, away from the thin film transistor, of the first passivation layer, and an overlapping region exists between an orthographic projection of the no-load protection electrode on the substrate and an orthographic projection of the active layer pattern on the substrate.

Optionally, the embodiment of the application provides another method for manufacturing an array substrate. The method for manufacturing the array substrate is used for manufacturing the array substrate shown in fig. 11. The manufacturing method of the array substrate may include:

step a2, a first conductive pattern is formed on a substrate.

Optionally, the material of the first conductive pattern may include: molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al) or alloy material. The first conductive pattern may include: a gate electrode, a gate line and a common electrode line.

For example, a first conductive film may be formed on a substrate by any one of a variety of methods such as deposition, coating, sputtering, and the like, and then a one-time patterning process may be performed on the first conductive film to form a first conductive pattern, and the one-time patterning process may include: photoresist coating, exposure, development, etching and photoresist stripping.

Step B2, a gate insulating layer is formed on the first conductive pattern.

Alternatively, the material of the gate insulating layer may be silicon dioxide, silicon nitride, or a high dielectric constant material.

For example, a gate insulating film may be formed on the substrate on which the first conductive pattern is formed by any one of a variety of means such as deposition, coating, sputtering, and the like, and then a one-time patterning process may be performed on the gate insulating film to form a gate insulating layer, and the one-time patterning process may include: photoresist coating, exposure, development, etching and photoresist stripping.

Step C2, an active layer pattern is formed on the gate insulating layer.

Optionally, the active layer pattern material may include: and (3) IGZO.

For example, an active layer thin film may be formed on the substrate on which the gate insulating layer is formed by any of various means such as deposition, coating, sputtering, etc., and then a patterning process may be performed on the active layer thin film once to form an active layer pattern. The one-time patterning process may include: photoresist coating, exposure, development, etching and photoresist stripping.

Step D2, forming a second conductive pattern on the active layer pattern.

Optionally, the material of the second conductive pattern may include: metal Mo, metal Ti, metal Cu, metal aluminum Al or alloy material. The second conductive pattern may include: source and drain electrodes and data lines.

For example, a second conductive film may be formed on the substrate on which the active layer pattern is formed by any of a variety of means such as deposition, coating, sputtering, and the like, and then a patterning process may be performed on the second conductive film to form a second conductive pattern, and the patterning process may include: photoresist coating, exposure, development, etching and photoresist stripping.

Step E2, forming a first passivation layer on the second conductive pattern.

Optionally, the material of the first passivation layer may be silicon dioxide, silicon nitride, or a high dielectric constant material.

For example, a first passivation film may be formed on the substrate on which the second conductive pattern is formed by any one of a variety of methods such as deposition, coating, sputtering, and the like, and then a one-time patterning process may be performed on the first passivation film to form the first passivation layer, and the one-time patterning process may include: photoresist coating, exposure, development, etching and photoresist stripping.

Step F2, forming a third conductive pattern on the first passivation layer.

Optionally, the material of the third conductive pattern may include: and (3) ITO. The third conductive pattern may include: a common electrode and a dummy electrode.

For example, a third conductive film may be formed on the substrate on which the first passivation layer is formed by any one of a plurality of methods such as deposition, coating, sputtering, and the like, and then a patterning process may be performed on the third conductive film to form a third conductive pattern, and the patterning process may include: photoresist coating, exposure, development, etching and photoresist stripping.

And G2, forming a second passivation layer on the third conductive pattern.

Optionally, the material of the second passivation layer may be silicon dioxide, silicon nitride, or a high dielectric constant material.

For example, a second passivation film may be formed on the substrate on which the third conductive pattern is formed by any one of a variety of methods such as deposition, coating, sputtering, and the like, and then a one-time patterning process may be performed on the second passivation film to form the second passivation layer, and the one-time patterning process may include: photoresist coating, exposure, development, etching and photoresist stripping.

Step H2, forming a pixel electrode on the second passivation layer.

Optionally, the material of the pixel electrode may include: and (3) ITO.

For example, a pixel electrode thin film may be formed on the substrate on which the third passivation layer is formed by any one of a plurality of methods, such as deposition, coating, sputtering, and the like, and then a patterning process may be performed on the pixel electrode thin film to form a pixel electrode, and the patterning process may include: photoresist coating, exposure, development, etching and photoresist stripping.

Another embodiment of the present application provides a method for manufacturing an array substrate. The method for manufacturing the array substrate is used for manufacturing the array substrate shown in fig. 13. The manufacturing method of the array substrate may include:

step a3, a TFT is formed on a substrate. The TFT may include: an active layer pattern.

Step B3, forming a first passivation layer on the TFT. The first passivation layer covers the TFT.

And step C3, forming a transparent display electrode on the first passivation layer. The transparent display electrode is in contact with one side, far away from the TFT, of the first passivation layer, the transparent display electrode is provided with a hollow area, and the orthographic projection of the active layer pattern in the TFT on the substrate is located in the orthographic projection of the hollow area on the substrate.

Optionally, another embodiment of the present application further provides another method for manufacturing an array substrate. The method for manufacturing the array substrate is used for manufacturing the array substrate shown in fig. 16. The manufacturing method of the array substrate may include:

step a4, a first conductive pattern is formed on a substrate.

For the step a4, reference may be made to the step a2, which is not described herein again in this embodiment of the present application.

Step B4, a gate insulating layer is formed on the first conductive pattern.

For the step B4, reference may be made to the step B2, which is not described herein again in this embodiment of the present application.

Step C4, an active layer pattern is formed on the gate insulating layer.

For the step C4, reference may be made to the step C2, which is not described herein again in this embodiment of the present application.

Step D4, forming a second conductive pattern on the active layer pattern.

For the step D4, reference may be made to the step D2, which is not described herein again in this embodiment of the present application.

Step E4, forming a first passivation layer on the second conductive pattern.

For the step E4, reference may be made to the step E2, which is not described herein again in this embodiment of the present application.

Step F4, forming a common electrode on the first passivation layer.

Optionally, the material of the common electrode may include: and (3) ITO. The common electrode pattern may have a hollowed-out region.

For example, a common electrode thin film may be formed on a substrate on which a first passivation layer is formed by any one of a plurality of methods such as deposition, coating, sputtering, and the like, and then a patterning process may be performed on the common electrode thin film to form a common electrode, and the patterning process may include: photoresist coating, exposure, development, etching and photoresist stripping.

And G4, forming a second passivation layer on the third conductive pattern.

For the step G4, reference may be made to the step G2, which is not described herein again in this embodiment of the present application.

Step H4, forming a pixel electrode on the second passivation layer.

For the step H4, reference may be made to the step H2, which is not described herein again in this embodiment of the present application.

It can be clearly understood by those skilled in the art that, for convenience and brevity of description, the working principle and the connection relationship of each structure in the array substrate described above may refer to the corresponding content in the embodiment of the structure of the array substrate, and are not described herein again.

The embodiment of the application also provides a display device which comprises any one of the array substrates. The display device may be: the display device comprises any product or component with a display function, such as a liquid crystal panel, electronic paper, a mobile phone, a tablet personal computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.

It is noted that in the drawings, the sizes of layers and regions may be exaggerated for clarity of illustration. Also, it will be understood that when an element or layer is referred to as being "on" another element or layer, it can be directly on the other element or layer or intervening layers may also be present. In addition, it will be understood that when an element or layer is referred to as being "under" another element or layer, it can be directly under the other element or intervening layers or elements may also be present. In addition, it will also be understood that when a layer or element is referred to as being "between" two layers or elements, it can be the only layer between the two layers or elements, or there can be more than one intermediate layer or element. Like reference numerals refer to like elements throughout.

In this application, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. The term "plurality" means two or more unless expressly limited otherwise.

The above description is intended to be exemplary only, and not to limit the present application, and any modifications, equivalents, improvements, etc. made within the spirit and scope of the present application are intended to be included therein.

Claims

1. An array substrate, comprising:

a substrate;

2. The array substrate of claim 1,

the orthographic projection of the active layer pattern on the substrate is positioned in the orthographic projection of the idle load protection electrode on the substrate.

3. The array substrate of claim 1,

the transparent display electrode and the no-load protection electrode are arranged on the same layer and are made of the same material.

4. The array substrate of claim 1,

the thin film transistor is a bottom gate type thin film transistor or a top gate type thin film transistor.

5. The array substrate of claim 1,

the minimum distance between the boundary of the orthographic projection of the idle-loaded protection electrode on the substrate and the boundary of the orthographic projection of the active layer pattern on the substrate is greater than or equal to 2 microns.

6. The array substrate of any one of claims 1 to 5,

the thin film transistor further includes: the grid electrode is positioned on one side, close to the substrate, of the active layer pattern, the grid electrode insulating layer is positioned between the grid electrode and the active layer pattern, the source drain electrode is positioned on one side, far away from the substrate, of the active layer pattern, and the source drain electrode is in lap joint with the active layer pattern;

7. The array substrate of claim 6,

the array substrate further includes: the second passivation layer is positioned on the transparent display electrode and the no-load protection electrode, the pixel electrode is positioned on the second passivation layer, the pixel electrode is in contact with one side, far away from the common electrode, of the second passivation layer, the first passivation layer and the second passivation layer are provided with second through holes, and the pixel electrode is electrically connected with the source and the drain electrodes through the second through holes.

8. An array substrate, comprising:

a substrate;

9. The array substrate of claim 8,

the minimum distance between the boundary of the orthographic projection of the hollow area on the substrate and the boundary of the orthographic projection of the active layer pattern on the substrate is greater than or equal to 2 microns.

10. A display device, comprising: an array substrate as claimed in any one of claims 1 to 9.