CN215265534U - GIP compensation circuit - Google Patents
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- CN215265534U CN215265534U CN202120462021.0U CN202120462021U CN215265534U CN 215265534 U CN215265534 U CN 215265534U CN 202120462021 U CN202120462021 U CN 202120462021U CN 215265534 U CN215265534 U CN 215265534U
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Abstract
The utility model relates to a GIP compensation circuit technical field, in particular to GIP compensation circuit, including transistor T1, transistor T2, transistor T3, transistor T4, transistor T5, transistor T6, transistor T7, transistor T8, transistor T9, electric capacity C1, electric capacity C2 and electric capacity C3, the grid of transistor T5 is connected with the drain-source resistance of transistor T8, the grid of transistor T9, the drain-source resistance of transistor T7 and the one end of electric capacity C3 electricity respectively, the source-source resistance of transistor T8 is connected with the drain-source resistance of transistor T9 electricity, the grid of transistor T7 is connected with the source-source resistance of transistor T7 electricity, the grid of transistor T8 connects the second grid, make so that can utilize the compensation part that transistor T7 in the GIP compensation circuit, transistor T8, the compensation part that transistor T9 and electric capacity C3 constitute, thereby solve the Vth skew problem of some in the GIP compensation circuit and cause the circuit.
Description
Technical Field
The utility model relates to a GIP compensating circuit technical field, in particular to GIP compensating circuit.
Background
In recent decades, with the progress of the era and the development of information technology, people have increasingly demanded electronic consumer products, which has promoted the development of the liquid crystal display industry, and with the development of the era, electronic products are continuously developed toward light, thin and power saving.
In the display industry, liquid crystal display (lcd) is important, each pixel of the lcd has a TFT (Thin Film Transistor), a Gate (Gate) of the TFT is connected to a horizontal scanning line, a Source (Drain) of the TFT is connected to a vertical data line, and a Source (Source) of the TFT is connected to a pixel electrode. If a positive voltage is applied to one of the horizontal scan lines, all the TFTs on that line are turned on, and the pixel electrodes on that line are connected to the vertical data lines to write the video signal voltages on the data lines into the pixels, thereby controlling the transmittance of different liquid crystals and further achieving the effect of controlling color.
When driving a gate circuit, there are two main methods at present: firstly, an IC is bound outside a panel; another is by GIP (i.e. Gate In Panel) technique. However, as the times grow, people have more and more high requirements on the display of high screen ratio of the panel, and the GIP technology is already the main way of driving the gate circuit. The basic concept of GIP is to integrate the gate driver of LCD Panel on a glass substrate instead of externally connecting a silicon wafer to form the scan drive to the Panel. Compared with the traditional COF (the technology is called Chip On Film, and is often called a Chip On Film, and is a crystal grain soft Film packaging technology for fixing an Integrated Circuit (IC) On a flexible circuit board) and a COG (Chip On Glass, namely the Chip is directly bound On Glass) process, the technology not only saves cost, but also can save the process of binding in the grid direction, is very beneficial to improving the productivity, and improves the integration level of the TFT-LCD panel. Therefore, the GIP technique reduces the usage of the gate driver IC, reduces power consumption and cost, and simultaneously can reduce the frame of the display panel to realize the design of a narrow frame, which is a valued technique.
Since the GIP circuit is a circuit formed by combining TFT devices integrated on an Array substrate, the TFT devices are susceptible to frequency, voltage and temperature, resulting in a shift in the threshold voltage Vth of the TFT devices. In the GIP circuit, because the GIP pull-down voltage stabilizing circuit is subjected to the action of a high-frequency signal for a long time, Vth of a TFT device on the GIP circuit is easy to shift, and the shift can cause the abnormity of the GIP circuit, so that the gate signal Gn output by the GIP circuit is abnormal.
SUMMERY OF THE UTILITY MODEL
The utility model discloses the technical problem that will solve is: a GIP compensation circuit is provided to solve the problem of circuit failure caused by Vth shift of some TFTs in the GIP compensation circuit.
In order to solve the technical problem, the utility model discloses a technical scheme be:
a GIP compensation circuit comprises a transistor T1, a capacitor C1 and a capacitor C1, wherein a source of the transistor T1 is electrically connected with a gate of the transistor T1, a source of the transistor T1, a drain of the transistor T1, one end of the capacitor C1 and a gate of the transistor T1 respectively, a drain of the transistor T1 is electrically connected with a gate of the transistor T1 and one end of the capacitor C1 respectively, a source of the transistor T1 is electrically connected with a source of the transistor T1, a source of the transistor T1 and a source of the transistor T1, a source of the transistor T1 is electrically connected with the other end of the capacitor C1 and a drain of the transistor T1 respectively, and a gate of the transistor T1 is electrically connected with a drain of the transistor T1, a drain of the transistor T1 and one end of the capacitor C1 respectively. The source of the transistor T8 is electrically connected to the drain of the transistor T9, the gate of the transistor T7 is electrically connected to the source of the transistor T7, the gate of the transistor T7 and the source of the transistor T7 are both connected to the first gate trace, the gate of the transistor T8 is connected to the second gate trace, the gate of the transistor T1 is connected to the third gate trace, and the gate of the transistor T6 is connected to the fourth gate trace.
The beneficial effects of the utility model reside in that:
by electrically connecting the source of the transistor T2 with the gate of the transistor T2, the source of the transistor T6, the drain of the transistor T3, one end of the capacitor C2 and the gate of the transistor T4, respectively, the drain of the transistor T2 is electrically connected with the gate of the transistor T3 and one end of the capacitor C1, respectively, the source of the transistor T2 is electrically connected with the source of the transistor T3, the source of the transistor T9 and the source of the transistor T5, the source of the transistor T4 is electrically connected with the other end of the capacitor C2 and the drain of the transistor T5, respectively, the gate of the transistor T5 is electrically connected with the drain of the transistor T8, the gate of the transistor T9, the drain of the transistor T7 and one end of the capacitor C3, the source of the transistor T8 is electrically connected with the drain of the transistor T9, the gate of the transistor T7 is electrically connected with the source of the transistor T7 and the gate of the transistor T7 and the source of the transistor T7 are all routed to the first gate, the gate of the transistor T8 is connected with the second gate wire, the gate of the transistor T1 is connected with the third gate wire, and the gate of the transistor T6 is connected with the fourth gate wire, so that a Vth compensation part consisting of the transistor T7, the transistor T8, the transistor T9 and the capacitor C3 in the GIP compensation circuit can be utilized, and the problem of circuit failure caused by Vth deviation of some TFTs in the GIP compensation circuit is solved.
Drawings
Fig. 1 is a schematic circuit diagram of a GIP compensation circuit according to the present invention;
fig. 2 is a timing diagram of a GIP compensation circuit according to the present invention;
fig. 3 is a schematic circuit diagram of a GIP compensation circuit according to the present invention;
fig. 4 is a schematic circuit diagram of a GIP compensation circuit according to the present invention;
fig. 5 is a schematic circuit diagram of a GIP compensation circuit according to the present invention;
fig. 6 is a schematic circuit diagram of a GIP compensation circuit according to the present invention;
fig. 7 is a schematic circuit diagram of a GIP compensation circuit according to the present invention;
fig. 8 is a schematic circuit diagram of a GIP compensation circuit according to the present invention;
fig. 9 is a schematic circuit diagram of a GIP compensation circuit according to the present invention;
fig. 10 is a schematic circuit diagram of a GIP compensation circuit according to the present invention.
Detailed Description
In order to explain the technical content, the objects and the effects of the present invention in detail, the following description is made with reference to the accompanying drawings in combination with the embodiments.
Referring to fig. 1, the present invention provides a technical solution:
a GIP compensation circuit comprises a transistor T1, a capacitor C1 and a capacitor C1, wherein a source of the transistor T1 is electrically connected with a gate of the transistor T1, a source of the transistor T1, a drain of the transistor T1, one end of the capacitor C1 and a gate of the transistor T1 respectively, a drain of the transistor T1 is electrically connected with a gate of the transistor T1 and one end of the capacitor C1 respectively, a source of the transistor T1 is electrically connected with a source of the transistor T1, a source of the transistor T1 and a source of the transistor T1, a source of the transistor T1 is electrically connected with the other end of the capacitor C1 and a drain of the transistor T1 respectively, and a gate of the transistor T1 is electrically connected with a drain of the transistor T1, a drain of the transistor T1 and one end of the capacitor C1 respectively. The source of the transistor T8 is electrically connected to the drain of the transistor T9, the gate of the transistor T7 is electrically connected to the source of the transistor T7, the gate of the transistor T7 and the source of the transistor T7 are both connected to the first gate trace, the gate of the transistor T8 is connected to the second gate trace, the gate of the transistor T1 is connected to the third gate trace, and the gate of the transistor T6 is connected to the fourth gate trace.
From the above description, the beneficial effects of the present invention are:
by electrically connecting the source of the transistor T2 with the gate of the transistor T2, the source of the transistor T6, the drain of the transistor T3, one end of the capacitor C2 and the gate of the transistor T4, respectively, the drain of the transistor T2 is electrically connected with the gate of the transistor T3 and one end of the capacitor C1, respectively, the source of the transistor T2 is electrically connected with the source of the transistor T3, the source of the transistor T9 and the source of the transistor T5, the source of the transistor T4 is electrically connected with the other end of the capacitor C2 and the drain of the transistor T5, respectively, the gate of the transistor T5 is electrically connected with the drain of the transistor T8, the gate of the transistor T9, the drain of the transistor T7 and one end of the capacitor C3, the source of the transistor T8 is electrically connected with the drain of the transistor T9, the gate of the transistor T7 is electrically connected with the source of the transistor T7 and the gate of the transistor T7 and the source of the transistor T7 are all routed to the first gate, the gate of the transistor T8 is connected with the second gate wire, the gate of the transistor T1 is connected with the third gate wire, and the gate of the transistor T6 is connected with the fourth gate wire, so that a Vth compensation part consisting of the transistor T7, the transistor T8, the transistor T9 and the capacitor C3 in the GIP compensation circuit can be utilized, and the problem of circuit failure caused by Vth deviation of some TFTs in the GIP compensation circuit is solved.
Furthermore, the other end of the capacitor C1 and the drain of the transistor T4 are both connected to the first clock signal, and the other end of the capacitor C3 is connected to the second clock signal.
Further, the drain of the transistor T1 is connected to the positive electrode of the power supply.
Further, the drain of the transistor T6, the source of the transistor T2, the source of the transistor T3, the source of the transistor T9 and the source of the transistor T5 are all connected to the negative pole of the power supply.
Further, the transistor T1, the transistor T2, the transistor T3, the transistor T4, the transistor T5, the transistor T6, the transistor T7, the transistor T8, and the transistor T9 are all N-channel MOS transistors.
From the above description, the output waveform of the GIP compensation circuit can be further stabilized by the MOS transistor with the N-channel, so that the cost for improving the GIP process is saved, and the display effect of the display screen is optimized.
Referring to fig. 1 to 10, a first embodiment of the present invention is:
referring to fig. 1, a GIP compensation circuit includes a transistor T1, a capacitor C1, and a capacitor C1, wherein a source of the transistor T1 is electrically connected to a gate of the transistor T1, a source of the transistor T1, a drain of the transistor T1, one end of the capacitor C1, and a gate of the transistor T1, a drain of the transistor T1 is electrically connected to the gate of the transistor T1 and one end of the capacitor C1, a source of the transistor T1 is electrically connected to the source of the transistor T1, and the source of the transistor T1, a source of the transistor T1 is electrically connected to the other end of the capacitor C1 and the drain of the transistor T1, a gate of the transistor T1 is electrically connected to the drain of the transistor T1, the capacitor C1 and one end of the capacitor C1, the source of the transistor T8 is electrically connected to the drain of the transistor T9, the gate of the transistor T7 is electrically connected to the source of the transistor T7, the gate of the transistor T7 and the source of the transistor T7 are both connected to the first gate trace, the gate of the transistor T8 is connected to the second gate trace, the gate of the transistor T1 is connected to the third gate trace, and the gate of the transistor T6 is connected to the fourth gate trace.
The other end of the capacitor C1 and the drain of the transistor T4 are both connected to a first clock signal, and the other end of the capacitor C3 is connected to a second clock signal.
The drain of the transistor T1 is connected to the positive electrode of the power supply.
The drain electrode of the transistor T6, the source electrode of the transistor T2, the source electrode of the transistor T3, the source electrode of the transistor T9 and the source electrode of the transistor T5 are all connected with the negative pole of the power supply.
The transistor T1, the transistor T2, the transistor T3, the transistor T4, the transistor T5, the transistor T6, the transistor T7, the transistor T8 and the transistor T9 are all N-channel MOS transistors.
Referring to fig. 1, in the GIP compensation circuit of 9T3C, there are 9 TFTs and 3 capacitors, wherein, the Vth compensation portion composed of transistor T7, transistor T8, transistor T9 and capacitor C3, the output precharge portion composed of transistor T1 and capacitor C2, the output portion composed of transistor T4, and the pull-down portion composed of transistor T2, transistor T3, transistor T5, transistor T6 and capacitor C1 are four portions in total.
Fig. 2 is a timing diagram of the GIP compensation circuit designed by this scheme: in the timing chart, it is divided into seven periods, i.e., a compensation precharge period t1, a compensation period t2, an output precharge period t3, an output period t4, a pull-down output period t5, a pull-down Q-point period t6, and a pull-down voltage stabilization period t 7.
Fig. 3 is a schematic diagram of the compensation precharge stage of the GIP compensation circuit designed in this scheme: in this phase (i.e., the compensation precharge phase t1), Gn-6 is high VH, Gn-4, Gn-2, Gn +4, CK1 and CK7 are low VL; at this time, the transistor T7 is turned on, the P1 of the capacitor C3 is changed from the low potential to the high potential V1 through the transistor T7, and since the P1 is at the high potential V1 at this time, the transistor T5 and the transistor T9 are turned on, Gn is pulled down by VGL and maintained at the low potential VL; since CK7 is at a low potential at this time, the other end of the capacitor C1 is at VL.
Fig. 4 is a schematic diagram of the compensation stage of the GIP compensation circuit designed by the scheme: in this phase (i.e., the compensation phase t2), Gn-4 and P1 are high VH, Gn-6, Gn-2, Gn +4, CK1 and CK7 are low VL; gn maintains VL voltage through the transistor T5, P1 is connected with VGL through the opened transistor T8 and the opened transistor T9, so that the potential at the point P1 is pulled down by VGL until the transistor T9 is closed, the potential at the point P1 is reduced to VL + Vth from V1, the transistor T5 and the transistor T9 are closed, Vth of the transistor T9 is stored on the capacitor C3, the potential at the point P1 is VL + Vth, and the other end of the capacitor C3 is maintained at VGL potential by CK 7.
Fig. 5 is a schematic diagram of the output precharge stage of the GIP compensation circuit designed in this scheme: in this stage (i.e., the output precharge stage t3), Gn-2 and CK7 are high VH, Gn-6, Gn-4, Gn +4 and CK1 are low VL; at this time, the Q point is charged from VGH to VH by the transistor T1, and since the Q point is at high level, the transistor T2 and the transistor T4 are turned on, Gn is maintained at VL by the transistor T4, and P2 is maintained at VL by being pulled down by the turned-on transistor T2. Since the end of CK7 connected to the capacitor C3 rises to VH at this time, the other end P1 of the capacitor C3 rises to VH + Vth through the capacitive coupling potential, the transistor T9 and the transistor T5 are turned on at this time, and Gn can be maintained at the low potential VL through the pull-down of the transistor T5.
Fig. 6 is a schematic diagram of the output stage of the GIP compensation circuit designed by the scheme: in this phase (i.e., the output phase t4), Q and CK1 are high VH, Gn-6, Gn-4, Gn-2, Gn +4 and CK7 are low VL; since the Q point is at a high potential at this time, the transistor T4 is turned on, Gn outputs a high potential VH by the high potential output from CK1 through the transistor T4, and the Q point voltage is raised by the coupling action of the capacitor C2, stabilizing the output of Gn. At the same time, since the transistor T2 is also turned on at this time, P2 is pulled down to be maintained at VL through the turned-on transistor T2. Since the end of CK7 connected to the capacitor C3 rises to VL at this time, the other end P1 of the capacitor C3 rises to VL + Vth by the capacitive coupling potential, and the transistor T9 and the transistor T5 are turned off at this time, and the output L of Gn is stabilized.
Fig. 7 is a schematic diagram of the pull-down output stage of the GIP compensation circuit designed by the present scheme: in this stage (i.e., the pull-down output stage t5), Q is a high potential VH, and Gn-6, Gn-4, Gn-2, Gn +4, CK1 and CK7 are low potentials VL; since the Q point is high at this time, the transistor T4 is turned on, and Gn is pulled down from the high potential VH to the low potential VL by the low potential outputted from CK1 through the transistor T4. At the same time, since the transistor T2 is also turned on at this time, P2 is pulled down to be maintained at VL through the turned-on transistor T2. Since the end of CK7 to which the capacitor C3 is connected is still VL at this time, the other end P1 of the capacitor C3 is still maintained at VL + Vth.
Fig. 8 is a schematic diagram of the pull-down Q-point phase of the GIP compensation circuit designed by the present scheme: in this phase (i.e., pull-down Q-point phase t6), Gn +4 is high VH, Gn-6, Gn-4, Gn-2, Gn, CK1 and CK7 is low VL; since the Q point is at the high level at this time, the transistor T2 is turned on, and Q is pulled down from the high level VH to the low level VL by the VGL signal through the transistor T2. Since the end of CK7 to which the capacitor C3 is connected is still VL at this time, the other end P1 of the capacitor C3 is still maintained at VL + Vth.
The pull-down voltage stabilization phase t7 is divided into two phases, and fig. 9 is a schematic diagram of the pull-down voltage stabilization phase of the GIP compensation circuit designed by the present scheme: in this stage, CK7 is high potential VH, and Gn-6, Gn-4, Gn-2, Gn and CK1 are low potential VL; due to the fact thatAt this time, one end of CK7 connected to capacitor C3 rises to VH, so that the other end P1 of capacitor C3 rises to VH + Vth, at this time, transistor T5 is turned on, and a low potential of Gn is maintained, so that a voltage stabilizing effect is achieved, Vth shift is easily caused due to the gate of transistor T5 being driven by a high frequency voltage, stability of the GIP compensation circuit is affected, and Vgs of transistor T5 at this stage is equal to VH + Vth-VL due to the P1 point potential being VH + Vth, and I (linear region) is equal to μ C (W/L) { (Vgs-Vth) Vds- (1/2) Vds2}; i (saturation region) 1/2 μ Cox (W/L) (Vgs-Vth)2(where Vth is a threshold voltage, Vgs is a gate-to-source voltage difference, Vds is a drain-to-source voltage difference, W is a tft channel width, L is a tft channel length, μ is an electron mobility, Cox is a gate insulating layer unit area capacitance, VH is a high potential, and VL is a low potential), Vth of both regions can be cancelled, thereby preventing Vth of the transistor T5 from drifting to affect the stability of the GIP compensation circuit.
Fig. 10 is a schematic diagram of the voltage stabilization phase two of the GIP compensation circuit designed in this scheme: in this stage, CK1 is high potential VH, Gn-6, Gn-4, Gn-2, Gn +4 and CK7 are low potential VL; due to the capacitive coupling effect of CK1 at the high voltage C1, the voltage rises to the high voltage VH, so that the transistor T3 is turned on, keeping the Q point pulled down to the low voltage VL, and preventing the Q point from being coupled to the high voltage of CK1 by the parasitic capacitance of the transistor T4.
In summary, the present invention provides a GIP compensation circuit, wherein a source of a transistor T2 is electrically connected to a gate of a transistor T2, a source of a transistor T6, a drain of a transistor T3, one end of a capacitor C2 and a gate of a transistor T4, a drain of a transistor T2 is electrically connected to a gate of a transistor T3 and one end of a capacitor C1, a source of a transistor T2 is electrically connected to a source of a transistor T3, a source of a transistor T9 and a source of a transistor T5, a source of a transistor T4 is electrically connected to the other end of a capacitor C2 and a drain of a transistor T5, a gate of a transistor T5 is electrically connected to a drain of a transistor T8, a gate of a transistor T9, a drain of a transistor T7 and one end of a capacitor C3, a source of the transistor T8 is electrically connected to a drain of a transistor T9, a gate of a transistor T7 is electrically connected to a source of a transistor T7 and a gate of a transistor T7 and a source of a transistor T7 are electrically connected to a gate of a transistor T7, the gate of the transistor T8 is connected with the second gate wire, the gate of the transistor T1 is connected with the third gate wire, and the gate of the transistor T6 is connected with the fourth gate wire, so that a Vth compensation part consisting of the transistor T7, the transistor T8, the transistor T9 and the capacitor C3 in the GIP compensation circuit can be utilized, and the problem of circuit failure caused by Vth deviation of some TFTs in the GIP compensation circuit is solved.
The above mentioned is only the embodiment of the present invention, and not the limitation of the patent scope of the present invention, all the equivalent transformations made by the contents of the specification and the drawings, or the direct or indirect application in the related technical field, are included in the patent protection scope of the present invention.
Claims (5)
1. A GIP compensation circuit is characterized by comprising a transistor T1, a transistor T2, a transistor T3, a transistor T4, a transistor T5, a transistor T6, a transistor T7, a transistor T8, a transistor T9, a capacitor C1, a capacitor C2 and a capacitor C3, wherein a source of the transistor T2 is electrically connected with a gate of the transistor T2, a source of the transistor T6, a drain of the transistor T3, one end of the capacitor C2 and a gate of the transistor T4 respectively, a drain of the transistor T2 is electrically connected with a gate of the transistor T3 and one end of the capacitor C1 respectively, a source of the transistor T2 is electrically connected with a source of the transistor T3, a source of the transistor T9 and a source of the transistor T5 respectively, a source of the transistor T4 is electrically connected with the other end of the capacitor C2 and a drain of the transistor T5 respectively, and a gate of the transistor T5 is electrically connected with a drain of the transistor T8 and a gate of the transistor T9 respectively, The drain of the transistor T7 is electrically connected to one end of the capacitor C3, the source of the transistor T8 is electrically connected to the drain of the transistor T9, the gate of the transistor T7 is electrically connected to the source of the transistor T7, the gates of the transistor T7 and the transistor T7 are both connected to the first gate trace, the gate of the transistor T8 is connected to the second gate trace, the gate of the transistor T1 is connected to the third gate trace, and the gate of the transistor T6 is connected to the fourth gate trace.
2. The GIP compensation circuit of claim 1, wherein the other terminal of the capacitor C1 and the drain of the transistor T4 are both connected to a first clock signal, and the other terminal of the capacitor C3 is connected to a second clock signal.
3. The GIP compensation circuit of claim 1, wherein a drain of the transistor T1 is connected to an anode of a power supply.
4. The GIP compensation circuit of claim 1, wherein the drain of the transistor T6, the source of the transistor T2, the source of the transistor T3, the source of the transistor T9 and the source of the transistor T5 are all connected to the negative terminal of a power supply.
5. The GIP compensation circuit of claim 1, wherein the transistor T1, the transistor T2, the transistor T3, the transistor T4, the transistor T5, the transistor T6, the transistor T7, the transistor T8 and the transistor T9 are all N-channel MOS transistors.
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| CN202120462021.0U CN215265534U (en) | 2021-03-03 | 2021-03-03 | GIP compensation circuit |
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| CN202120462021.0U CN215265534U (en) | 2021-03-03 | 2021-03-03 | GIP compensation circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113160766A (en) * | 2021-03-03 | 2021-07-23 | 福建华佳彩有限公司 | GIP compensation circuit and control method thereof |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113160766A (en) * | 2021-03-03 | 2021-07-23 | 福建华佳彩有限公司 | GIP compensation circuit and control method thereof |
| CN113160766B (en) * | 2021-03-03 | 2025-06-13 | 福建华佳彩有限公司 | A GIP compensation circuit and control method thereof |
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