CN215954316U - Power management framework and chip - Google Patents

Abstract

The utility model discloses a power management architecture and a chip, wherein the architecture sends enabling signals through a first reset pin and a second reset pin to respectively awaken a first power domain power module and a second power domain power module, so that the power architecture is recovered from a state that power cannot be supplied because the first power domain power module and the second power domain power module suspend working, the functionality of the power architecture is improved, and the power architecture is stronger and more stable; the VDD1 power module and the VDD2 power module are awakened by interactive operation, so that the power supply module is powerful in function; the low-power-consumption power domain and the high-power-consumption power domain are independent of each other, do not influence each other, and have stronger robustness.

Description

Power management framework and chip

Technical Field

The utility model relates to the field of circuit design, in particular to a power management architecture and a chip.

Background

With the continuous expansion of the domestic chip consumption market demand, the chip self-sufficiency rate is continuously improved, SOC and MCU products corresponding to various application demands are in the endlessly, and the SOC and MCU products continuously replace foreign products; a power management module (PMU) is used as a core part of chip power supply and is vital to a good product; along with the continuous promotion of electronic product performance, the requirement of various chips to the consumption also continuously promotes, and various new power management frameworks are born as one's own accord, and current power framework's stability is relatively poor, and certain components and parts in the circuit can't the during operation, can't awaken up, lead to the unable power supply of power.

SUMMERY OF THE UTILITY MODEL

In order to solve the above problems, the present invention provides a power management architecture and a chip, which can reduce the power consumption of the power management architecture, enhance the stability of the power management architecture, and recover the operating state according to an external signal when the power management architecture cannot operate. The specific technical scheme of the utility model is as follows:

a power management architecture comprising a first power domain interface, a second power domain interface, a first power domain power module, a second power domain power module, a VDD1 power domain, a VDD2 power domain, and a power select switch; the first power domain interface and the second power domain interface are connected with a first power domain power module through a power selection switch, and the first power domain power module is connected with a VDD1 power module; the second power domain interface is connected with a second power domain power module, and the second power domain power module is connected with a VDD2 power module; the first power domain power supply module is provided with a first reset pin, and the first reset pin and the VDD2 power supply module are used for sending an enable signal to wake up the first power domain power supply module; the second power domain power module is provided with a second reset pin, and the second reset pin and the VDD1 power module are used for sending an enable signal to wake up the second power domain power module.

Compared with the prior art, the technical scheme of the application simultaneously sends the enabling signals through the first reset pin and the second reset pin to respectively awaken the first power domain power module and the second power domain power module, or sends the enabling signals through one of the first reset pin and the second reset pin to awaken the corresponding power domain power module, and then awakens the other power domain power module through the VDD1 power module or the VDD2 power module, so that the power architecture is recovered from the state that the first power domain power module and the second power domain power module cannot supply power due to work suspension, the functionality of the power architecture is improved, and the power architecture is stronger and more stable; the VDD1 power module and the VDD2 power module are awakened by interactive operation, so that the power supply module is powerful in function; the low-power-consumption power domain and the high-power-consumption power domain are independent of each other, do not influence each other, and have stronger robustness.

Further, the first power domain power supply module comprises a low-power-consumption band-gap reference source, a first power supply comparator, a first awakening module, a first low-dropout linear regulator and a first source follower; the low-power-consumption band-gap reference source is respectively connected with the first power supply comparator, the first low-dropout linear voltage regulator and the first source follower; the first awakening module is respectively connected with the first power supply comparator, the first low dropout linear regulator and the first source follower; the output ends of the first low dropout regulator and the first source follower are connected with a VDD1 power module together and used for outputting a voltage VDD1 to a VDD1 power module so that the VDD1 power module generates a low voltage power domain.

Further, first module of awakening up includes 5 inputs and 2 outputs, the input of first module of awakening up links to each other with first pin, first power comparator, VDD1 power module and VDD2 power module that resets respectively, just 2 inputs link to each other with VDD1 power module in the input of first module of awakening up, the output of first module of awakening up links to each other with first low dropout linear regulator and first source follower respectively.

Further, the VDD1 power module includes a logic circuit, the logic circuit includes 3 output ends, 2 output ends of the logic circuit are respectively connected to the first wake-up module, and are configured to send a signal to adjust states of the first low dropout regulator and the first source follower, and another output end of the logic circuit is connected to the second power domain power module, and is configured to send a signal to wake up the second power domain power module. Compared with the prior art, the external wake-up mechanism can completely shut off the logic power supply so as to realize lower power consumption.

Furthermore, the first power comparator comprises an input end and an output end, the input end of the first power comparator is connected with the low-power-consumption band-gap reference source, the output end of the first power comparator is connected with the first awakening module, and the first power comparator is used for comparing the reference voltage generated by the received low-power-consumption band-gap reference source with the input voltage input by the first power domain interface or the second power domain interface and outputting a voltage signal to the first awakening module according to the comparison result.

Further, the second power domain power supply module comprises a band gap reference source, a second power supply comparator, a second wake-up module, a second low dropout linear regulator and a second source follower; the band-gap reference source is respectively connected with the second power supply comparator, the second low-dropout linear voltage regulator and the second source follower; the second awakening module is respectively connected with the second power supply comparator, the second low dropout linear regulator and the second source follower; the output ends of the second low dropout regulator and the second source follower are connected with a VDD2 power module together and used for outputting a voltage VDD2 to a VDD2 power module, so that the VDD2 power module generates a low voltage power domain.

Further, the second awakens up the module and includes 5 inputs and 2 outputs, the output of the second awakens up the module and resets pin, second power comparator, VDD1 power module and VDD2 power module with the second respectively and links to each other, just 2 inputs link to each other with VDD2 power module in the input of the second awakens up the module, the output of the second awakens up the module and links to each other with second low dropout linear regulator and second source follower respectively.

Further, the VDD2 power module includes a logic circuit, the logic circuit includes 3 output ends, 2 output ends of the logic circuit are respectively connected to the second wake-up module, and are configured to send a signal to adjust states of the second low dropout regulator and the second source follower, and another output end of the logic circuit is connected to the first power domain power module, and is configured to send a signal to wake up the first power domain power module.

Furthermore, the second power supply comparator comprises an input end and an output end, the input end of the second power supply comparator is connected with the band-gap reference source, the output end of the second power supply comparator is connected with the second awakening module, and the second power supply comparator is used for comparing the reference voltage generated by the received band-gap reference source with the input voltage input by the second power supply domain interface and outputting a voltage signal to the second awakening module according to the comparison result.

Furthermore, the first power domain interface and the second power domain interface are both connected with a high-voltage power domain, the first power domain interface is used for being connected with an energy storage power domain, and the second power domain interface is used for being connected with an external power domain.

Further, the power selection switch is configured to select a power domain for supplying power according to output voltages of the first power domain interface and the second power domain interface, and if the output voltage of the second power domain interface is within a set range, the power selection switch selects the second power domain interface to supply power to the first power domain power module. The external power domain is preferentially used for supplying power, so that the stored power can be efficiently stored, and the practicability is high.

A chip comprises the power management architecture.

Drawings

Fig. 1 is a schematic structural diagram of a power management architecture according to an embodiment of the present invention.

Fig. 2 is a circuit diagram of a wake-up module according to another embodiment of the utility model.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more clear, the present invention will be described and illustrated below with reference to the accompanying drawings and embodiments. It should be understood that the following specific examples are illustrative only and are not intended to limit the utility model. Moreover, it should be understood that the technical disclosure of the present invention may be modified by those skilled in the art by a conventional method, and it should not be understood that the technical disclosure of the present invention is not limited thereto.

Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this application belongs. Reference to the words "a," "an," "the," and "the" in this application are not to be construed as limiting in number, and may mean singular or plural. The use of the terms "including," "comprising," "having," and any variations thereof herein, is intended to cover non-exclusive inclusions, such as: a process, method, system product or apparatus that comprises a list of steps or modules is not limited to the listed steps or elements but may include additional steps or elements not listed or inherent to such process, method, product or apparatus. Reference throughout this application to the terms "first," "second," "third," and the like are only used for distinguishing between similar references and not intended to imply a particular ordering for the objects.

In an embodiment of the present invention, a POWER management architecture is provided, as shown in fig. 1, the architecture includes a first POWER DOMAIN interface VCC1, a second POWER DOMAIN interface VCC2, a first POWER DOMAIN POWER module VSL POWER DOMAIN, a second POWER DOMAIN POWER module VCC2 POWER DOMAIN, a VDD1 POWER module VDD1 POWER DOMAIN, a VDD2 POWER module VDD2 POWER DOMAIN, and a POWER selection SWITCH POWER SWITCH; the first POWER DOMAIN interface VCC1 and the second POWER DOMAIN interface VCC2 are connected with a first POWER DOMAIN POWER module VSL POWER DOMAIN through a POWER selection SWITCH, and the first POWER DOMAIN POWER module VSL POWER DOMAIN is connected with a VDD1 POWER module VDD1 POWER DOMAIN; the second POWER DOMAIN interface VCC2 is connected to a second POWER DOMAIN POWER module VCC2 POWER DOMAIN, and the second POWER DOMAIN POWER module VCC2 POWER DOMAIN is connected to a VDD2 POWER module VDD2 POWER DOMAIN; the first POWER DOMAIN POWER module VSL POWER DOMAIN is provided with a first reset pin nRSTA, and the first reset pin nRSTA and the VDD2 POWER module VDD2 POWER DOMAIN are used for sending an enable signal to wake up the first POWER DOMAIN POWER module VSL POWER DOMAIN; the second POWER DOMAIN POWER module VCC2 POWER DOMAIN is provided with a second reset pin nRSTB, and the second reset pin nRSTB and the VDD1 POWER module VDD1 POWER DOMAIN are used for sending an enable signal to wake up the second POWER DOMAIN POWER module VCC2 POWER DOMAIN. According to the technical scheme, the first reset pin and the second reset pin simultaneously send the enabling signals to respectively awaken the first power domain power module and the second power domain power module, or the first reset pin or the second reset pin sends the enabling signals to awaken the corresponding power domain power module, and then the VDD1 power module or the VDD2 power module awakens the other power domain power module, so that the power architecture is recovered from the state that power cannot be supplied due to the fact that the first power domain power module and the second power domain power module suspend working, the functionality of the power architecture is improved, and the power architecture is stronger and more stable; the VDD1 power module and the VDD2 power module are awakened by interactive operation, so that the power supply module is powerful in function; the low-power-consumption power domain and the high-power-consumption power domain are independent of each other, do not influence each other, and have stronger robustness.

A stepped power management method is characterized in that a first power domain interface VCC1 and a second power domain interface VCC2 are connected with a high-voltage power domain, the first power domain interface VCC1 is used for being connected with an energy storage power domain, generally is a power supply source with limited energy such as a battery, is related to the standby capability of a product, and has higher requirement on low power consumption; the second power domain interface VCC2 is used for connecting to an external power domain, and generally, the adapter supplies power through an external LDO or DC-DC, and generally, the power domain has relatively large power consumption and provides power when the chip operates in a normal high-performance mode. The POWER selection SWITCH is used for selecting a POWER supply DOMAIN for POWER supply according to output voltages of the first POWER DOMAIN interface VCC1 and the second POWER DOMAIN interface VCC2, and if the output voltage of the second POWER DOMAIN interface VCC2 is within a set range, the POWER selection SWITCH selects the second POWER DOMAIN interface VCC2 to supply POWER for the first POWER DOMAIN POWER module VSL POWER DOMAIN. Under the condition that the first POWER DOMAIN interface VCC1 and the second POWER DOMAIN interface VCC2 are simultaneously turned on, as long as the second POWER DOMAIN interface VCC2 is not lower than a certain voltage value, the first POWER DOMAIN POWER module VSL POWER DOMAIN always selects the second POWER DOMAIN interface VCC2 to supply POWER, otherwise selects the first POWER DOMAIN interface VCC1 to supply POWER, thereby saving the energy of the battery providing the first POWER DOMAIN interface VCC 1. The external power domain is preferentially used for supplying power, so that the stored power can be efficiently stored, and the practicability is high.

Specifically, under the condition that the second POWER DOMAIN interface VCC2 is not powered and the first POWER DOMAIN interface VCC1 is powered, the first POWER DOMAIN POWER module VSL POWER DOMAIN selects the first POWER DOMAIN interface VCC1 to supply POWER through the POWER selection SWITCH POWER SWITCH, the first POWER DOMAIN POWER module VSL POWER DOMAIN only has one low-POWER bandgap reference source LPBG and the POWER comparator POWER CMP, and the two modules can achieve nA-level POWER consumption according to the existing technology. On the basis, the first low dropout regulator LDO1 can be awakened by the external first reset pin nRSTA to generate the voltage VDD1 for POWER supply, and the LOGIC circuit LOGIC of the VDD1 POWER module VDD1 POWER DOMAIN can perform subsequent LOGIC control operation. Under the condition that the second POWER DOMAIN interface VCC2 supplies POWER and the first POWER DOMAIN interface VCC1 does not supply POWER, the first POWER DOMAIN POWER module VSL POWER DOMAIN selects the second POWER DOMAIN interface VCC2 to supply POWER through the POWER selection SWITCH POWER SWITCH, at this time, the above operations can be performed in the first POWER DOMAIN POWER module VSL POWER DOMAIN, and the second POWER comparator POWER CMP2DMOS2 and the second low dropout linear regulator LDO2 can be simultaneously turned off and do not work, and only the external second reset pin nRSTB or the LOGIC circuit LOGIC of the VDD1 POWER module VDD1 POWER DOMAIN needs to send an enable signal, turn on the second low dropout linear regulator LDO2, generate the VDD2, and perform subsequent LOGIC control. Under the framework, a VDD1 POWER module VDD1 POWER DOMAIN and a VDD2 POWER module VDD2 POWER DOMAIN under a first POWER DOMAIN POWER module VSL POWER DOMAIN and a second POWER DOMAIN POWER module VCC2 POWER DOMAIN respectively have four states, DMOS/LPLDO and LDO are not switched on, only DMOS is switched on or only LDO is switched on, and DMOS and LDO are switched on. Can be freely combined according to the load demand condition. Compared with the prior art, the technical scheme of the application sends the enabling signals to awaken the first POWER DOMAIN POWER module VSL POWER DOMAIN and the second POWER DOMAIN POWER module VCC2 POWER DOMAIN respectively through the first reset pin nRSTA and the second reset pin nRSTB, so that the POWER architecture is recovered from the state that the POWER supply cannot be supplied because the first POWER DOMAIN POWER module VSL POWER DOMAIN and the second POWER DOMAIN POWER module VCC2 POWER DOMAIN suspend working, the functionality of the POWER architecture is improved, and the POWER architecture is stronger and more stable; the VDD1 POWER module VDD1 POWER DOMAIN and the VDD2 POWER module VDD2 Power DOMAIN wake up each other through interactive operation, and the POWER module is powerful; the low-power-consumption power domain and the high-power-consumption power domain are independent of each other, do not influence each other, and have stronger robustness.

As one embodiment, the first POWER DOMAIN POWER MODULE VSL POWER DOMAIN includes a low POWER bandgap reference source LPBG, a first POWER comparator POWER CMP1, a first wake-up MODULE wake, a first low dropout linear regulator LDO1, and a first source follower dmo 1; the low-POWER-consumption band-gap reference source LPBG is provided with 3 output ends, and the 3 output ends are respectively connected with a first POWER comparator POWER CMP1, a first low-dropout linear regulator LDO1 and a first source follower DMOS 1; the first POWER comparator POWER CMP1 includes an input terminal and an output terminal, the input terminal of the first POWER comparator POWER CMP1 is connected to the low POWER bandgap reference source LPBG, the output terminal of the first POWER comparator POWER CMP1 is connected to the wake up MODULE, and the first POWER comparator POWER CMP1 is configured to compare a reference voltage generated by receiving the low POWER bandgap reference source LPBG with an input voltage input by the first POWER domain interface VCC1 or the second POWER domain interface VCC2, and output a voltage signal to the wake up MODULE according to a comparison result.

Specifically, the first power domain interface VCC1 and the second power domain interface VCC2 may be powered on individually or jointly; when the first POWER DOMAIN interface VCC1 is independently powered on, the first POWER DOMAIN POWER module VSL POWER supply DOMAIN is always powered on, the first POWER DOMAIN POWER module VSL POWER supply DOMAIN selects the first POWER DOMAIN interface VCC1 as a POWER supply through the POWER selection SWITCH POWER SWITCH, the low POWER consumption bandgap reference source LPBG is self-started, and the first POWER comparator POWER CMP1 judges whether the first POWER DOMAIN interface VCC1 is powered on to a required voltage level by using a reference voltage generated by the low POWER consumption bandgap reference source LPBG, and then generates a VSL _ OK signal. The VSL _ OK signal generated by the first POWER comparator POWER CMP1 is sent to the first wake-up MODULE, the first wake-up MODULE makes the first low dropout regulator LDO1 generate the low voltage POWER DOMAIN VDD1 through the SR flip-flop under the VSL POWER DOMAIN of the first POWER DOMAIN POWER MODULE, and thereafter the state of the first source follower DMOS1 or the first low dropout regulator 1 can be adjusted through the LOGIC circuit LOGIC in the POWER DOMAIN VDD1, and the first source follower DMOS1 and the first low dropout regulator LDO1 can be turned off, turned on, or turned on only one of them at the same time.

Specifically, the first wake-up MODULE is connected to the first POWER comparator POWER CMP1, the first low dropout regulator LDO1, and the first source follower DMOS1, respectively; the output ends of the first low dropout linear regulator LDO1 and the first source follower DMOS1 are connected to a VDD1 POWER module VDD1 POWER DOMAIN together, and are used for outputting a voltage VDD1 to a VDD1 POWER module VDD1 POWER DOMAIN, so that the VDD1 POWER module VDD1 POWER DOMAIN generates a low voltage POWER DOMAIN. The first wake-up MODULE includes 5 input terminals and 2 output terminals, the output terminals of the first wake-up MODULE are respectively connected to the first reset pin nRSTA, the first POWER comparator POWER CMP1, the VDD1 POWER MODULE VDD1 POWER DOMAIN, and the VDD2 POWER MODULE VDD2 POWER DOMAIN, and 2 of the input terminals of the first wake-up MODULE are connected to the VDD1 POWER MODULE VDD1 POWER DOMAIN, and the output terminals of the first wake-up MODULE are respectively connected to the first low dropout linear regulator LDO1 and the first source follower DMOS 1.

Specifically, the VDD1 POWER MODULE VDD1 POWER DOMAIN includes a LOGIC circuit LOGIC, which includes 3 output terminals, 2 output terminals of the LOGIC circuit LOGIC are respectively connected to the first wake-up MODULE, for sending signals to adjust the states of the first low dropout linear regulator LDO1 and the first source follower DMOS1, and another output terminal of the LOGIC circuit LOGIC is connected to the second POWER DOMAIN POWER MODULE VCC2 POWER DOMAIN, for sending signals to wake up the second POWER DOMAIN POWER MODULE VCC2 POWER DOMAIN. Compared with the prior art, the external wake-up mechanism can completely shut off the logic power supply so as to realize lower power consumption.

For one embodiment, the second POWER DOMAIN POWER MODULE VCC2 POWER DOMAIN includes a bandgap reference BG, a second POWER comparator POWER CMP2, a second wake-up MODULE, a second low dropout regulator LDO2, and a second source follower DMOS 2; the band-gap base source BG is provided with 3 output ends, and the 3 output ends are respectively connected with a second POWER comparator POWER CMP2, a second low dropout regulator LDO2 and a second source follower DMOS 2; the second POWER comparator POWER CMP2 includes an input terminal and an output terminal, the input terminal of the second POWER comparator POWER CMP2 is connected to the bandgap reference source BG, the output terminal of the second POWER comparator POWER CMP2 is connected to the second wake-up MODULE, and the second POWER comparator POWER CMP2 is configured to compare a reference voltage generated by receiving the bandgap reference source BG with an input voltage input by the second POWER domain interface VCC2, and output a voltage signal to the second wake-up MODULE according to a comparison result.

Specifically, when the first POWER DOMAIN interface VCC2 is powered on, the first POWER DOMAIN POWER module VSL POWER DOMAIN selects the first POWER DOMAIN interface VCC1 as a POWER supply through the POWER selection SWITCH POWER SWITCH, and operates according to the above-mentioned workflow when the first POWER DOMAIN interface VCC1 is powered on. The bandgap reference BG of the second POWER DOMAIN POWER module VCC2 POWER DOMAIN starts itself, and the second POWER comparator POWER CMP2 determines whether the second POWER DOMAIN interface VCC2 is powered up to a required voltage level by using the reference voltage generated by the bandgap reference BG, and generates a VCC2_ OK signal. The VCC2_ OK signal generated by the second POWER comparator POWER CMP2 is sent to the second wake-up MODULE, the second wake-up MODULE makes the second low dropout regulator LDO2 generate the low voltage POWER DOMAIN VDD2 through the SR flip-flop under the second POWER DOMAIN POWER MODULE VCC2 POWER DOMAIN, and then the state of the second source follower DMOS2 or the second low dropout regulator LDO2 can be changed through the LOGIC circuit LOGIC in the VDD2 POWER MODULE VDD2 POWER DOMAIN, and the second source follower DMOS2 and the second low dropout regulator LDO2 can be turned off, on, or turned on only one of them at the same time.

Specifically, the second wake-up MODULE is connected to the second POWER comparator POWER CMP2, the second low dropout regulator LDO2, and the second source follower DMOS2, respectively; the output ends of the second low dropout regulator LDO2 and the second source follower DMOS2 are connected to a VDD2 POWER module VDD2 POWER DOMAIN together, and are configured to output a voltage VDD2 to a VDD2 POWER module VDD2 POWER DOMAIN, so that the VDD2 POWER module VDD2 POWER DOMAIN generates a low voltage POWER DOMAIN. The second wake-up MODULE includes 5 input terminals and 2 output terminals, the output terminals of the second wake-up MODULE are respectively connected to the second reset pin nRSTB, the second POWER comparator POWER CMP2, the VDD1 POWER MODULE VDD1 POWER DOMAIN, and the VDD2 POWER MODULE VDD2 POWER DOMAIN, and 2 of the input terminals of the second wake-up MODULE are connected to the VDD2 POWER MODULE VDD2 POWER DOMAIN, and the output terminals of the second wake-up MODULE are respectively connected to the second low dropout linear regulator LDO2 and the second source follower DMOS 2.

Specifically, the VDD2 POWER MODULE VDD2 POWER DOMAIN includes a LOGIC circuit LOGIC, which includes 3 output terminals, wherein 2 output terminals of the LOGIC circuit LOGIC are respectively connected to the second wake-up MODULE for sending signals to adjust the states of the second low dropout linear regulator LDO2 and the second source follower DMOS2, and another output terminal of the LOGIC circuit LOGIC is connected to the first POWER DOMAIN POWER MODULE VSL POWER DOMAIN for sending signals to wake up the first POWER DOMAIN POWER MODULE VSL POWER DOMAIN. The structures of the VDD1 POWER module VDD1 POWER DOMAIN and the VDD2 POWER module VDD2 Power DOMAIN are the same. The first low dropout regulator LDO1 and the second low dropout regulator LDO2 can be replaced by DC-DC switching power supply structures to accommodate different power requirements.

As shown in fig. 2, fig. 2 is a circuit structure diagram of the wake-up MODULE, and the first wake-up MODULE and the second wake-up MODULE have the same structure and the same working content. In the circuit, the EN _ LDO _ I and EN _ DMOS _ I interfaces are connected to EN _ LDO and EN _ DMOS in the PMU top layer architecture, that is, for receiving an enable signal from the LOGIC circuit LOGIC of a POWER module, then the WAKEUP interface is for receiving an enable signal of another POWER module (EN _ LDO2 in the LOGIC circuit LOGIC of VDD1 POWER module VDD1 POWER DOMAIN, EN _ LDO1 in the LOGIC circuit LOGIC of VDD2 POWER module VDD2 POWER DOMAIN), VCC _ OK is a voltage detection signal for POWER-up, which is generated by the POWER comparator POWER CMP, and VCC _ OK is equal to 1, which indicates that POWER-up is complete. The nRST interface is a control signal to the reset pin.

A chip comprises the power management architecture.

Obviously, the above-mentioned embodiments are only a part of embodiments of the present invention, not all embodiments, and the technical solutions of the embodiments may be combined with each other. In the above embodiments of the present invention, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments. In the embodiments provided in the present invention, it should be understood that the disclosed technical contents can be implemented in other manners. The above-described embodiments of the apparatus are merely illustrative, and for example, the division of the circuit may be a logical division, and in actual implementation, there may be another division, for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not executed.

It should be noted that the various features described in the above embodiments may be combined in any suitable manner without departing from the scope of the utility model. In order to avoid unnecessary repetition, the embodiments of the present invention will not be described separately for the various possible combinations.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the utility model has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims (12)

1. A power management architecture, the architecture comprising a first power domain interface, a second power domain interface, a first power domain power module, a second power domain power module, a VDD1 power module, a VDD2 power module, and a power selection switch;

the first power domain interface and the second power domain interface are connected with a first power domain power module through a power selection switch, and the first power domain power module is connected with a VDD1 power module;

the second power domain interface is connected with a second power domain power module, and the second power domain power module is connected with a VDD2 power module;

the first power domain power supply module is provided with a first reset pin, and the first reset pin and logic generated in the VDD2 power supply module are used for sending an enable signal to wake up the first power domain power supply module;

the second power domain power module is provided with a second reset pin, and the second reset pin and logic generated in the VDD1 power module are used for sending an enable signal to wake up the second power domain power module.

2. The power management architecture of claim 1, wherein the first power domain power module comprises a low power bandgap reference source, a first power comparator, a first wake-up module, a first low dropout linear regulator, and a first source follower;

the low-power-consumption band-gap reference is respectively connected with the first power supply comparator, the first low-dropout linear regulator and the first source follower;

the first awakening module is respectively connected with the first power supply comparator, the first low dropout linear regulator and the first source follower;

the output ends of the first low dropout regulator and the first source follower are connected with a VDD1 power module together and used for outputting a voltage VDD1 to a VDD1 power module so that the VDD1 power module generates a low voltage power domain.

3. The power management architecture of claim 2, wherein the first wake-up module comprises 5 inputs and 2 outputs, the inputs of the first wake-up module are respectively connected to the first reset pin, the first power comparator, the VDD1 power module, and the VDD2 power module, and 2 of the inputs of the first wake-up module are connected to the VDD1 power module, and the outputs of the first wake-up module are respectively connected to the first low dropout linear regulator and the first source follower.

4. The power management architecture of claim 3, wherein the VDD1 power module comprises a logic circuit, the logic circuit comprises 3 output terminals, 2 output terminals of the logic circuit are respectively connected to the first wake-up module for sending signals to adjust the states of the first low dropout linear regulator and the first source follower, and another output terminal of the logic circuit is connected to the second power domain power module for sending signals to wake-up the second power domain power module.

5. The power management architecture of claim 2, wherein the first power comparator comprises an input terminal and an output terminal, the input terminal of the first power comparator is connected to the low power bandgap reference source, the output terminal of the first power comparator is connected to the first wake-up module, and the first power comparator is configured to compare a reference voltage generated by the received low power bandgap reference source with an input voltage input by the first power domain interface or the second power domain interface, and output a voltage signal to the first wake-up module according to a comparison result.

6. The power management architecture of claim 1, wherein the second power domain power module comprises a bandgap reference source, a second power comparator, a second wake-up module, a second low dropout linear regulator, and a second source follower;

the band-gap reference source is respectively connected with the second power supply comparator, the second low-dropout linear voltage regulator and the second source follower;

the second awakening module is respectively connected with the second power supply comparator, the second low dropout linear regulator and the second source follower;

the output ends of the second low dropout regulator and the second source follower are connected with a VDD2 power module together and used for outputting a voltage VDD2 to a VDD2 power module, so that the VDD2 power module generates a low voltage power domain.

7. The power management architecture of claim 6, wherein the second wake-up module comprises 5 inputs and 2 outputs, the outputs of the second wake-up module are respectively connected to the second reset pin, the second power comparator, the VDD1 power module, and the VDD2 power module, and 2 of the inputs of the second wake-up module are connected to the VDD2 power module, and the outputs of the second wake-up module are respectively connected to the second low dropout linear regulator and the second source follower.

8. The power management architecture of claim 7, wherein the VDD2 power module comprises a logic circuit, the logic circuit comprises 3 output terminals, 2 output terminals of the logic circuit are respectively connected to the second wake-up module for sending signals to adjust the states of the second low dropout linear regulator and the second source follower, and another output terminal of the logic circuit is connected to the first power domain power module for sending signals to wake-up the first power domain power module.

9. The power management architecture of claim 6, wherein the second power comparator comprises an input terminal and an output terminal, the input terminal of the second power comparator is connected to the bandgap reference source, the output terminal of the second power comparator is connected to the second wake-up module, and the second power comparator is configured to compare a reference voltage generated by the bandgap reference source with an input voltage input to the second power domain interface, and output a voltage signal to the second wake-up module according to a comparison result.

10. The power management architecture of claim 1, wherein the first power domain interface and the second power domain interface are both connected to a high voltage power domain, the first power domain interface is configured to connect to an energy storage power domain, and the second power domain interface is configured to connect to an external power domain.

11. The power management architecture as claimed in claim 10, wherein the power selection switch is configured to select a power domain to be powered according to output voltages of the first power domain interface and the second power domain interface, and if the output voltage of the second power domain interface is within a predetermined range, the power selection switch selects the second power domain interface to power the first power domain power module.

12. A chip characterised in that it comprises a power management architecture as claimed in any one of claims 1 to 11.

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