CN217087875U - A multi-level voltage IO unit and its chip - Google Patents

Abstract

The invention discloses a multi-level voltage IO unit and a chip thereof. The chip includes a multi-level voltage IO unit, and the multi-level voltage IO unit includes: an IO pin, a programmable DAC, a first switch, a second switch, a amplifier and ESD protection circuit; the input end of the programmable DAC inputs control signals and data signals, and the output end is connected to the positive input end of the operational amplifier; the first end of the first analog switch is connected to the output end of the programmable DAC, and the second end is connected to the IO pin ; The output terminal of the operational amplifier leads out the data signal line, the negative input terminal is connected to the output terminal of the ESD protection circuit, and the input terminal of the ESD protection circuit is connected to the IO pin; the first terminal of the second analog switch is connected to the operational amplifier output terminal, and the second terminal is connected to the output terminal of the operational amplifier. Connect IO pins. The utility model has the advantages of simple structure, small chip area and low cost, and supports multi-level voltage input and output.

Description

A multi-level voltage IO unit and its chip

technical field

The utility model belongs to the field of integrated circuit design, in particular to a multi-level voltage IO unit and a chip thereof.

Background technique

Digital logic chips and MCU chips generally use general IO units provided by Foundry manufacturers (specialized in manufacturing chip manufacturers) or third-party IP manufacturers to implement multiple IO pins for high-level or low-level digital signal input or output. The input state of this IO pin is only 0 (low level) or 1 (high level), and the output state is only 0 (low level) or 1 (high level) and the tri-state output is disabled. The existing general-purpose IO unit is shown in Figure 1.

The use of this general-purpose IO unit has the following drawbacks: On the one hand, this general-purpose IO is not suitable for a complex system of multi-voltage and multi-level multi-core interconnection. The conventional solution is to add an external level conversion chip, which leads to increased costs, such as converting its own 3.3V digital signal to 1.8V through an external chip before connecting to the target device, or vice versa. On the other hand, this kind of general-purpose IO is not very suitable for digital-analog hybrid chips and systems. Some peripherals need to provide them with multiple pull-up or pull-down currents, and some peripherals need the MCU to dynamically provide them with multiple reference voltages, or Sensing a variety of signal voltages generated by peripherals. The conventional solution requires multiple resistors, DACs, comparators, etc., which require many components, high cost, and large area, which is not conducive to IO layout. Therefore, this solution has not been adopted by the digital-analog hybrid MCU, nor has it been implemented in the IO unit library.

Chinese patent CN201910163902.X discloses that the programmable DAC in the multiplexing chip realizes the function of programmable pull-up resistor or programmable pull-down resistor, but it fails to expand the multi-level input and output of the IO unit.

SUMMARY OF THE INVENTION

Purpose of the invention: In order to solve the problems in the prior art that the chip supports multi-level voltage input and output, resulting in complex circuits, many components, high cost, and unfavorable commercial use, the present utility model provides a multi-level voltage IO unit and its chip.

Technical solution: a multi-level voltage IO unit, including:

IO pin;

Programmable DAC, the input terminal inputs control signals and data signals, and the output terminal is connected to the positive input terminal of the operational amplifier;

The first analog switch, the first end is connected to the programmable DAC output end, and the second end is connected to the IO pin;

The operational amplifier, the output terminal leads out the data signal line, the negative input terminal is connected to the output terminal of the ESD protection circuit, and the input terminal of the ESD protection circuit is connected to the IO pin;

For the second analog switch, the first end is connected to the output end of the operational amplifier, and the second end is connected to the IO pin.

Further, the input end of the programmable DAC includes a set of data signal lines and at least two mode control lines, the data signal lines input data signals, and the mode control lines input control signals.

Further, the operational amplifier is a rail-to-rail amplifier.

Further, it also includes a resistor, one end of the resistor is connected to the second end of the first analog switch, and the other end of the resistor is connected to the IO pin.

Further, the second end of the second analog switch is connected to the second end of the first analog switch.

Further, it also includes an analog signal comparison result digitizing module, the input end of the analog signal comparison result digitizing module is connected to the output end of the operational amplifier, and the other end leads out the data signal line.

Further, the second analog switch is embedded in the operational amplifier, the second analog switch includes a first PMOS transistor and a first NMOS transistor, the output end of the operational amplifier includes a second PMOS transistor and a second NMOS transistor, and the first PMOS transistors are connected in series At the drain terminal or source terminal of the second PMOS transistor, the first NMOS transistor is connected in series with the drain terminal or source terminal of the second NMOS transistor, and the gate terminals of the first PMOS transistor and the first NMOS transistor are connected to the three-state output control terminal of the operational amplifier .

Further, the second analog switch is embedded in the operational amplifier, and the second analog switch includes a third PMOS tube, a third NMOS tube, a first combination switch and a second combination switch; the output end of the operational amplifier includes a second PMOS tube and a second combination switch. The second NMOS transistor; the first combined switch and the second combined switch are respectively connected to the gate terminals of the second PMOS transistor and the second NMOS transistor; the source terminal of the third PMOS transistor is connected to the power supply, and the drain terminal is connected to the gate terminal of the second PMOS transistor ; The source terminal of the third NMOS transistor is grounded, and the drain terminal is connected to the gate terminal of the second NMOS transistor.

Further, it also includes at least one of a digital level input module and an output module; the input end of the digital level input module is connected to the output end of the ESD protection circuit, and the output end of the digital level input module leads out a data signal line; The output module includes an output terminal, a first input terminal and a second input terminal, the output terminal is connected to the IO pin, the first input terminal is connected to the enable output control terminal, and the second input terminal is connected to the data signal.

A chip containing a multi-level voltage IO unit, including the above-mentioned multi-level voltage IO unit and a mode control unit, the output end of the mode control unit is connected to the input end of the programmable DAC, the control end of the first analog switch and the second analog control terminal of the switch.

The utility model provides a multi-level voltage IO unit and a chip thereof. Compared with the prior art, the following beneficial effects exist:

(1) The structure is simple, only one op amp and two analog switches are added, and the functions of multi-level voltage comparison input and multi-level voltage buffer output are realized through a certain connection relationship and mode combination design.

(2) Using a programmable DAC, multiplexing the resistance of the DAC itself, and combining the control of two analog switches, multiple modes of multi-level input and output are realized through logical combination.

(3) Multiplexing of analog devices that are difficult to reduce with process improvement in the chip, such as multiplexing of resistors and op amps that cost more and occupy a larger area in the chip; increase the ease of use in the chip. Improved and reduced area digital devices, such as increased mode combination control. Under the effect of realizing multi-level voltage input and output, the increased area of the chip is reduced as much as possible, and the increased cost of the chip is reduced.

(4) Supports multi-level voltage input and output without adding a level conversion chip. It can provide multi-level voltage IO units for analog chips and digital-analog hybrid MCUs, which are suitable for digital-analog hybrid chips and systems, and improve the performance of the chip.

Description of drawings

Fig. 1 is the structural representation of existing IO unit;

2 is a schematic structural diagram of a multi-level voltage IO unit in Embodiment 1;

3 is a schematic structural diagram of the operational amplifier after the second analog switch is embedded in the second embodiment;

4 is a schematic diagram of the structure of the operational amplifier after the second analog switch is embedded in the third embodiment;

5 is a schematic structural diagram of a multi-level voltage IO unit in Embodiment 4;

FIG. 6 is a schematic structural diagram of a multi-level voltage IO unit according to the fifth embodiment.

Detailed ways

The present invention will be further explained below with reference to the accompanying drawings and specific embodiments.

Example 1:

A multi-level voltage IO unit, as shown in Figure 2, includes an IO pin PAD, a programmable DAC, a first analog switch K1, a second analog switch K2, an operational amplifier and an ESD protection circuit. The input end of the programmable DAC inputs control signals and data signals, and the output end is connected to the positive input end of the operational amplifier. The first end of the first analog switch is connected to the programmable DAC output end, and the second end is connected to the IO pin. The output terminal of the operational amplifier leads to the data signal line C0, the negative input terminal is connected to the output terminal of the ESD protection circuit, and the input terminal of the ESD protection circuit is connected to the IO pin. It is formed by adding GGNMOS or GRNMOS. In addition, there is also a first-level ESD protection connected to the IO pin PAD. The first end of the second analog switch is connected to the output end of the operational amplifier.

The input end of the programmable DAC includes a set of data signal lines DATA and at least two mode control lines PUE and PDE, the data signal lines input data signals, and the mode control lines input control signals for controlling which mode to enter.

The operational amplifier is a rail-to-rail amplifier, the input and output of the operational amplifier both support rail-to-rail, and the rail-to-rail operational amplifier supports input and output from 0 to the full range of power supply voltage.

A resistor R may also be included, one end of the resistor R is connected to the second end of the first analog switch, and the other end of the resistor R is connected to the IO pin. The resistance of the resistor is generally tens of ohms to hundreds of ohms. The MOS device of the first analog switch also serves as an ESD device, and together with the resistor R, it also serves as a secondary ESD protection for the positive input end of the operational amplifier. If the resistance value of R is small, the second terminal of the second analog switch can also be connected to the second terminal of the first analog switch, but it is usually directly connected to the IO pin. The resistor R is optional. If the positive input terminal of the op amp has a certain ESD tolerance, the resistor R can also be replaced by a short circuit.

A chip containing a multi-level voltage IO unit, especially a digital-analog hybrid MCU, includes the above-mentioned multi-level voltage IO unit and a mode control unit, the output end of the mode control unit is connected to the input end of the programmable DAC, the first The control terminals of the analog switch K1 and the second analog switch K2. The mode control unit outputs various mode control signals through combinational logic, and realizes various working modes by controlling the programmable DAC, the first analog switch and the second analog switch, including DAC direct output mode, DAC buffer output mode, and programmable pull-up resistor. mode, programmable pull-down resistor mode and multi-level input mode. Table 1 illustrates a series of combinational logics corresponding to various working mode tables, but is not limited to this combination. For analog devices whose area is difficult to reduce with process improvement, such as resistors and op amps, sufficient multiplexing is achieved through mode combination, and multiple functions can be realized with fewer devices and effective connection relationships.

Table 1 Various working modes

Embodiment 2:

The difference between the second embodiment and the first embodiment is that the second analog switch of the second embodiment is embedded in the operational amplifier. As shown in FIG. 3 , the second analog switch K2 includes a first PMOS transistor P1 and a first NMOS transistor N1, the output end of the operational amplifier includes a second PMOS transistor P2 and a second NMOS transistor N2, and the first PMOS transistor P1 is connected in series with the second PMOS transistor P2 and the second NMOS transistor N2. The drain terminal or source terminal of the PMOS transistor P2, the first NMOS transistor N1 is connected in series with the drain terminal or source terminal of the second NMOS transistor N2, and the gate terminals of the first PMOS transistor P1 and the first NMOS transistor N1 are connected to the three-state output of the operational amplifier The control terminal, the three-state output control terminal was originally used for enabling or disabling the three-state output of the operational amplifier. Now, the effect of controlling the opening or closing of the second analog switch can be realized through the enable or disable signal of the three-state output control terminal. In order to visually display the connection relationship of the second analog switch embedded in the operational amplifier. Figure 3 shows a simplified op amp structure, and an actual op amp is likely to be much more complex. In addition, with a slight technical adjustment, the positions of the above P1 and P2 can also be exchanged, and the positions of the above N1 and N2 can be exchanged, with the same effect. As shown in the figure, when the tri-state output control terminal is an open signal, it is equivalent to turning on the second analog switch, and when the tri-state output control terminal is a prohibiting signal, it is equivalent to turning off the second analog switch.

Embodiment three:

The second analog switch in the third embodiment is also embedded in the operational amplifier. Compared with the second embodiment, the difference lies in that the structure of the second analog switch is different, and the connection relationship with the operational amplifier is different. As shown in FIG. 4 , it is the way in which the second analog switch is embedded in the operational amplifier in the third embodiment. The second analog switch includes a third PMOS transistor P3, a third NMOS transistor N3 and two combination switches K3; the output end of the operational amplifier includes a second PMOS transistor P2 and a second NMOS transistor N2; the first combination switch and the second combination switch respectively connected to the gate terminal of the second PMOS transistor P2 and the second NMOS transistor N2; the source terminal of the third PMOS transistor P3 is connected to the power supply, and the drain terminal is connected to the gate terminal of the second PMOS transistor P2; the source terminal of the third NMOS transistor N3 is grounded , the drain terminal is connected to the gate terminal of the second NMOS transistor N2. The first combination switch and the second combination switch are both combination switches composed of a pair of PMOS transistors and NMOS transistors. The gate terminal of the second PMOS transistor P2 at the output end of the operational amplifier is controlled by the third PMOS transistor P3 and the first combined switch, and the gate terminal of the second NMOS transistor N2 is controlled by the third NMOS transistor N3 and the second combined switch. The switch control signal is shown as swon and swinv in the figure. When the two combined switches are turned on, it is equivalent to turning on the second analog switch, and the output of the operational amplifier is directly connected to the IO pin. When the third PMOS transistor P3 and the third NMOS transistor N3 are turned on, it is equivalent to the second analog switch. disconnect.

Although this method requires more devices, the current passing through the added MOS device is small, so the device size is small.

For the op amp embedded with the second analog switch, CO can be generated by another mirror output terminal of the op amp without tri-state control, or it can be derived from the previous stage of the multi-stage op amp.

Embodiment 4:

Compared with the first embodiment, the fourth embodiment adds an analog signal comparison result digitizing module, whose input end is connected to the output end of the operational amplifier, and the other end leads out a data signal line, as shown in FIG. 5 . The analog signal comparison result digitizing module can be implemented by several stages of inverters, or implemented by a level shift module. The op amp compares the voltages of the positive and negative input terminals, and the signal at the output terminal of the op amp produces a comparison result, either low level or high level. In theory, it can be used directly as a digital signal, but for better digital level matching effect, for example The operational amplifier works at 3.3V, and the digital core or the mode control unit expects the signal level to be 1.2V, then the analog signal comparison result digitization module can be added to achieve better digital matching effect.

Embodiment 5:

The fifth embodiment adds a digital level input module and an output module on the basis of the first embodiment or the second embodiment or the third embodiment or the fourth embodiment, or only one of them may be added independently.

As shown in FIG. 6 , the input end of the digital level input module is connected to the output end of the secondary ESD protection circuit, and the output end of the digital level input module leads out a data signal line to realize a single digital level input, which is used for compatibility with current There are general purpose IO units.

The output module includes an output end, a first input end and a second input end, the output end is connected to the IO pin, the first input end is connected to the enable output control end (select whether to use a single digital level output), and the second input end Connect the output data signal to achieve a single digital level output, which is compatible with existing general-purpose IO units.

The fourth embodiment can be compatible with the functions of the existing general-purpose IO unit, realize higher-speed single digital level input and output, and the MOS device of the output module can also serve as a first-level ESD protection device.

Claims (10)

1. a multi-level voltage IO unit, is characterized in that, comprises: IO pin; Programmable DAC, the input terminal inputs control signals and data signals, and the output terminal is connected to the positive input terminal of the operational amplifier; The first analog switch, the first end is connected to the programmable DAC output end, and the second end is connected to the IO pin; The operational amplifier, the output terminal leads out the data signal line, the negative input terminal is connected to the output terminal of the ESD protection circuit, and the input terminal of the ESD protection circuit is connected to the IO pin; For the second analog switch, the first end is connected to the output end of the operational amplifier, and the second end is connected to the IO pin. 2. The multi-level voltage IO unit according to claim 1, wherein the input end of the programmable DAC comprises a group of data signal lines and at least two mode control lines, the data signal lines input data signals, and the mode controls Line input control signal. 3. The multi-level voltage IO unit according to claim 1 or 2, wherein the operational amplifier is a rail-to-rail amplifier. 4. The multi-level voltage IO unit according to claim 1 or 2, further comprising a resistor, one end of the resistor is connected to the second end of the first analog switch, and the other end of the resistor is connected to the IO pin. 5. The multi-level voltage IO unit according to claim 4, wherein the second end of the second analog switch is connected to the second end of the first analog switch. 6. The multi-level voltage IO unit according to claim 1 or 2, further comprising an analog signal comparison result digitizing module, the input end of the analog signal comparison result digitizing module is connected to the operational amplifier output end, and the other end leads out data signal line. 7. The multi-level voltage IO unit according to claim 1 or 2, wherein the second analog switch is embedded in an operational amplifier, the second analog switch comprises a first PMOS transistor and a first NMOS transistor, and the operational amplifier The output end includes a second PMOS transistor and a second NMOS transistor. The first PMOS transistor is connected in series with the drain or source end of the second PMOS transistor, and the first NMOS transistor is connected in series with the drain or source end of the second NMOS transistor. The transistor and the gate terminal of the first NMOS transistor are connected to the three-state output control terminal of the operational amplifier. 8. The multi-level voltage IO unit according to claim 1 or 2, wherein the second analog switch is embedded in an operational amplifier, and the second analog switch comprises a third PMOS transistor, a third NMOS transistor, a first a combination switch and a second combination switch; the output end of the operational amplifier includes a second PMOS tube and a second NMOS tube; the first combination switch and the second combination switch are respectively connected to the gate ends of the second PMOS tube and the second NMOS tube; the The source terminal of the third PMOS tube is connected to the power supply, and the drain terminal is connected to the gate terminal of the second PMOS tube; the source terminal of the third NMOS tube is grounded, and the drain terminal is connected to the gate terminal of the second NMOS tube. 9. The multi-level voltage IO unit according to claim 1 or 2, further comprising at least one of a digital level input module and an output module; The input end of the digital level input module is connected to the output end of the ESD protection circuit, and the output end of the digital level input module leads out a data signal line; The output module includes an output terminal, a first input terminal and a second input terminal. The output terminal is connected to an IO pin, the first input terminal is connected to an enable output control terminal, and the second input terminal is connected to a data signal. 10. A chip containing a multi-level voltage IO unit, characterized in that it comprises the multi-level voltage IO unit and a mode control unit according to any one of claims 1 to 9, the output end of the mode control unit is connected to a programmable The input end of the DAC, the control end of the first analog switch and the control end of the second analog switch.

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