CN217821599U - Device for multiple hosts to share access memory - Google Patents

Abstract

The utility model discloses a device for sharing and accessing memory by multiple hosts. The device includes: a plurality of hosts, a bus, a plurality of control registers, a protection circuit and a plurality of memory spaces, wherein the plurality of control registers correspond to the plurality of memory spaces one by one, and the plurality of hosts write The bus and the read bus are connected to the bus, the bus is connected to the plurality of control registers and the protection circuit through a write bus, and the plurality of control registers and the plurality of memory spaces are connected to the bus through a read bus connected, the protection circuit is connected to the plurality of memory spaces. The utility model can combine the two steps of applying for writing permission and confirming writing permission into one step, which saves the access time of the host, and protects the uniqueness of the writing operation of each memory interval, which can protect the security of data.

Description

A device for multiple hosts to share access to memory

technical field

The utility model relates to the technical field of multi-host memory access, in particular to a device for multi-host shared memory access.

Background technique

Usually, in a multi-host access system, the host needs to perform the following operations to lock the memory access permission:

(1) The host writes the memory control register to apply for lock memory write permission.

(2) The host reads the status register of the memory, and checks whether the application for lock write permission is successful.

(3) If the application is successful, start the write operation, if the application is unsuccessful, return to (1) re-apply for the lock write memory permission.

In the above operation, at least two visits are required from applying for write permission to confirming write permission. For a high-speed access system, unnecessary waste of data bandwidth may be caused. Moreover, the security of all data depends on the value of the application permission register and the value of the status register for multi-hosts to read and write the memory. The host actively shields the write operation. If the host initiates the write operation by mistake, the data in the memory will still be changed by mistake, causing Unnecessary errors.

Contents of the invention

The purpose of the utility model is to provide a device for sharing memory access by multiple hosts, which combines the two steps of applying for write permission and confirming write permission into one step, saving the access time of the host, and protecting each memory interval. The uniqueness of the write operation can protect the security of the data.

The present application discloses a device for sharing and accessing memory by multiple hosts, including: multiple hosts, a bus, multiple control registers, protection circuits, and multiple memory spaces, wherein the multiple control registers and the multiple memory spaces In one-to-one correspondence, the multiple hosts are connected to the bus through a write bus and a read bus, the bus is connected to the multiple control registers and the protection circuit through a write bus, and the multiple control registers and the Multiple memory spaces are connected to the bus through a read bus, and the protection circuit is connected to the multiple memory spaces.

In a preferred example, each of the control registers includes: a first comparator, a second comparator, a first AND gate, a first selector and a flip-flop;

The first input terminal of the first comparator, the first input terminal of the first selector are connected to the output terminal of the flip-flop, the second input terminal of the first comparator is connected to a preset value, The output end of the first comparator is connected to the first input end of the first AND gate;

The first input end of the second comparator is connected to the read address signal, the second input end is connected to the register address, and the output end is connected to the second input end of the first AND gate;

The enable end of the first AND gate is connected to a read enable signal, and the output end is connected to the enable end of the first strobe;

The second input end of the first strobe is connected to the host serial number, the output end is connected to the data end of the flip-flop, and the enable end of the flip-flop is connected to a clock signal.

In a preferred example, the read enable signal is in an active state, and the output of the flip-flop in the current clock cycle of the clock signal is the preset value, and the value of the flip-flop is updated to the The host serial number, and the output of the next clock cycle of the clock signal is the host serial number.

In a preferred example, each of the control registers further includes: a third comparator, a fourth comparator, a second AND gate and a second selector;

The first input end of the third comparator, the first input end of the second selector are connected to the output end of the flip-flop, the second input end of the third comparator is connected to the host serial number, The output end of the third comparator is connected to the first input end of the second AND gate;

The first input end of the fourth comparator is connected to the write address signal, the second input end is connected to the register address, and the output end is connected to the second input end of the second AND gate;

The enable end of the second AND gate is connected to the write enable signal, and the output end is connected to the enable end of the second gate;

The second input end of the second gate is connected to a preset value, the output end is connected to the data end of the flip-flop, and the enable end of the flip-flop is connected to a clock signal.

In a preferred example, the write enable signal is in a valid state, and the output of the flip-flop in the current clock cycle of the clock signal is the serial number of the host, and the value of the flip-flop is updated to the the default value mentioned above.

In a preferred example, the protection circuit includes:

A multiplexer, the input end of the multiplexer is connected to the output end of each of the plurality of control registers, and the enable end is connected to the memory write address signal;

A fifth comparator, the first input terminal of the fifth comparator is connected to the output terminal of the multiplexer, and the second input terminal is connected to the serial number of the write access host; and

A third AND gate, the first input end of the third AND gate is connected to the output end of the fifth comparator, the second input end is connected to the memory write enable signal, and the output end is connected to the plurality of memory spaces.

In a preferred example, the enabling terminal of the multiplexer is connected to an interval judgment logic, and the interval judgment logic is used to judge and select one of the plurality of control registers according to the memory write address signal.

Compared with the prior art, the utility model implementation mode has the main difference and its effects in that:

(1) The host merges the two steps of applying for write permission and confirming write permission into one step through the read operation, saving the access time of the host.

(2) The memory range can be allocated freely, and more fine-grained management of read and write operations can be achieved.

(3) The hardware protection circuit compares the host access sequence number with the sequence number stored in the memory control register, protects the uniqueness of the write operation of each memory interval, and protects the security of data.

(4) The judgment of the serial number of the host computer by the hardware protection circuit is completed in one clock cycle, without additional delay, and the host access is more efficient.

It should be understood that within the scope of the present utility model, the above-mentioned technical features of the present utility model and the technical features specifically described in the following (such as embodiments) can be combined with each other to form new or preferred technical solutions . Due to space limitations, we will not repeat them here.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description These are only some embodiments of the utility model, and those skilled in the art can also obtain other drawings based on these drawings without creative work.

FIG. 1 is a schematic diagram of a device for sharing and accessing memory by multiple hosts in an example of the present invention.

Fig. 2 is a schematic diagram of the read logic of the control register in an example of the present invention.

FIG. 3 is a timing diagram of the read logic of the control register in an example of the present invention.

Fig. 4 is a schematic diagram of the writing logic of the control register in an example of the present invention.

Fig. 5 is a schematic diagram of a protection circuit in an example of the present invention.

In each attached drawing, each mark is as follows:

101.1, 101.2～101.m-host;

102-bus;

103.1, 103.2～103.n-control register;

104-protection circuit;

105.1, 105.2～105.n-memory space;

201 - the first comparator;

202 - second comparator;

203-the first AND gate;

204 - first gate;

205 - trigger;

301 - the third comparator;

302 - the fourth comparator;

303-the second AND gate;

304 - second gate;

401 - multiplexer;

402 - fifth comparator;

403-The third AND gate.

Detailed ways

In the following description, many technical details are proposed in order to enable readers to better understand the application. However, those skilled in the art can understand that the technical solutions claimed in this application can be realized even without these technical details and various changes and modifications based on the following implementation modes.

In order to make the purpose, technical solution and advantages of the present application clearer, the implementation manner of the present application will be further described in detail below in conjunction with the accompanying drawings.

The utility model provides a device for sharing and accessing a memory by multiple hosts. Typically, the device for sharing and accessing a memory by multiple hosts includes: multiple hosts, a bus, multiple control registers, protection circuits and multiple memory spaces. Wherein, the plurality of control registers are in one-to-one correspondence with the plurality of memory spaces, the plurality of hosts are connected to the bus through a write bus and a read bus, and the bus is connected to the plurality of control registers and the plurality of memory spaces through a write bus. The protection circuit is connected, the multiple control registers and the multiple memory spaces are connected to the bus through a read bus, and the protection circuit is connected to the multiple memory spaces.

Below in conjunction with specific embodiment, further illustrate the present invention. It should be understood that these examples are only used to illustrate the present invention and are not intended to limit the scope of the present invention. In addition, the drawings are schematic diagrams, so the device and equipment of the present invention are not limited by the size or scale of the schematic diagrams.

FIG. 1 is a schematic diagram of a device for sharing and accessing memory by multiple hosts in an example of the present invention. The device for sharing and accessing memory by multiple hosts includes: multiple hosts 101.1, 101.2-101.m, bus 102, multiple control registers 103.1, 103.2-103.n, protection circuit 104 and multiple memory spaces 105.1, 105.2-105.n . There is a one-to-one correspondence between multiple control registers 103.1, 103.2-103.n and multiple memory spaces 105.1, 105.2-105.n. A plurality of hosts 101.1, 101.2-101.N are connected to the bus 102 through a write bus and a read bus, and the bus 102 is connected to a plurality of control registers 103.1, 103.2-103.n and a protection circuit 104 through a write bus. A plurality of control registers 103.1, 103.2-103.n and a plurality of memory spaces 105.1, 105.2-105.n are connected to the bus through a read bus, and a protection circuit 104 is connected to a plurality of memory spaces 105.1, 105.2-105.n.

This solution is a hardware analysis read command to apply for write permission, and write protection through hardware logic, the whole memory is divided into multiple spaces, and each space independently controls read and write permissions through a memory control register. The bus module completes the read and write data and configures the register bus arbitration. After the arbitration, it will be converted into a read and write command with the serial number of the host.

In this application, the memory space is a storage module, which can realize flexible configuration of the number of memory intervals and the space size of each interval by setting different interval start addresses and interval sizes.

Fig. 2 is a schematic diagram of the read logic of the control register in an example of the present invention. Each control register includes: a first comparator 201 , a second comparator 202 , a first AND gate 203 , a first gate 204 and a flip-flop 205 . The first input end of the first comparator 201, the first input end of the first selector 204 and the output end of the flip-flop 205 are connected, and the second input end of the first comparator 201 is connected with a preset value (or default value) , the output end of the first comparator 202 is connected to the first input end of the first AND gate 203 . The first input end of the second comparator 202 is connected to the read address signal, the second input end is connected to the register address, and the output end is connected to the second input end of the first AND gate 203 . The enable end of the first AND gate 203 is connected to the read enable signal, and the output end is connected to the enable end of the first gate 204 . The second input end of the first selector 204 is connected to the host serial number, the output end is connected to the data end of the flip-flop 205 , and the enable end of the flip-flop is connected to the clock signal.

The control register module is a module for the host to apply for the write lock permission register, and each write permission register corresponds to the write permission of an interval memory. The default value of each write permission register is 0, which means that the corresponding memory range is not locked for write permission, and all hosts can write to this range. And all can apply for write permission lock.

The update of the register value can be completed by the host reading the register. If the value of the register is 0, the value of the register will be assigned as the serial number of the host during the read cycle, and the serial number of the host will be returned to the host at the same time, indicating that the host The application for write permission is successful, and the write operation of this memory range has been locked. As shown in Figure 3, the read enable signal is in an effective state, and the output of the flip-flop 205 in the current clock cycle of the clock signal is a preset value, the value of the flip-flop 205 is updated as the host serial number, and, in the clock signal The output of the next clock cycle is the host serial number.

If the register has been locked by other hosts, when the host reads the register, it will return the serial number of other hosts, indicating that the memory range has been locked by other hosts, and the host currently applying for write permission cannot apply for the write operation of this memory range.

Fig. 4 is a schematic diagram of the writing logic of the control register in an example of the present invention. Each control register includes: a third comparator 301 , a fourth comparator 302 , a second AND gate 303 , a second gate 304 and a flip-flop 305 . The first input end of the third comparator 301, the first input end of the second strobe 304 are connected with the output end of the flip-flop 305, the second input end of the third comparator 301 is connected with the host serial number, and the third comparator The output end of 301 is connected to the first input end of the second AND gate 303 . The first input terminal of the fourth comparator 302 is connected to the write address signal, the second input terminal is connected to the register address, and the output terminal is connected to the second input terminal of the second AND gate 303 . The enable end of the second AND gate 303 is connected to the write enable signal, and the output end is connected to the enable end of the second gate 304 . The second input terminal of the second selector 304 is connected to the preset value, the output terminal is connected to the data terminal of the flip-flop 305 , and the enable terminal of the flip-flop 305 is connected to the clock signal. It can be understood that the write logic in FIG. 2 and the read logic in FIG. 4 constitute the control register 103 of the present application.

The host that has applied for the write permission of this memory area can clear the serial number of the host stored in this register by writing to this register, and return the register to the default value. Other hosts that have not applied for the write permission of this memory area cannot change the value of this register by writing value. The write enable signal is in a valid state, and the output of the flip-flop 205 in the current clock cycle of the clock signal is the host serial number, and the value of the flip-flop 205 is updated to a preset value.

Fig. 5 is a schematic diagram of a protection circuit in an example of the present invention. The protection circuit includes: a multiplexer 401 , a fifth comparator 402 , and a third AND gate 403 . The input end of the multiplexer 401 is connected to the output end of each of the multiple control registers 103.1, 103.2˜103.n, and the enable end is connected to the memory write address signal. The first input terminal of the fifth comparator 402 is connected to the output terminal of the multiplexer 401 , and the second input terminal is connected to the serial number of the write access host. The first input end of the third AND gate 403 is connected to the output end of the fifth comparator 402, the second input end is connected to the memory write enable signal, and the output end is connected to a plurality of memory spaces 105.1, 105.2˜105.n. In one embodiment, the enabling terminal of the multiplexer 401 is connected to a section judgment logic, and the section judgment logic is used to judge and select one of the multiple control registers according to the memory write address signal. Interval judgment logic means that when the host issues a command to write memory space, it compares the value of the memory write address signal with the start address of each memory interval, determines the memory interval corresponding to the write command, and generates a memory control register selection signal. Using the memory register selection signal, the multiplexer 401 selects the control register corresponding to the memory interval, and outputs the serial number of the host with write permission.

The hardware write protection circuit is a mechanism to prevent the host from accidentally triggering to write the memory range that has not applied for write permission. After the hardware protection circuit receives the write command from the host, it first judges which memory interval to operate according to the memory write address signal, and then selects the value of the corresponding control register to compare with the host serial number of the write command. When the serial numbers are consistent, the memory write enable is valid, the write data is written into the memory area, and the write command is completed. The serial numbers are inconsistent, the memory write enable is invalid, the write data is discarded, and the write failure code is returned to the host through the write data interface, indicating that the write operation failed.

It should be noted that in the claims and description of this patent, relative terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or Any such actual relationship or order between such entities or operations is implied. Furthermore, the term "comprises", "comprises" or any other variation thereof is intended to cover a non-exclusive inclusion such that a process, method, article or apparatus comprising a set of elements includes not only those elements, but also includes elements not expressly listed. other elements of or also include elements inherent in such a process, method, article, or apparatus. Without further limitations, an element defined by the statement "comprising a" does not exclude the presence of additional identical elements in the process, method, article or apparatus comprising said element.

All documents mentioned in this application are incorporated by reference in this application as if each were individually incorporated by reference. In addition, it should be understood that after reading the above teaching content of the utility model, those skilled in the art can make various changes or modifications to the utility model, and these equivalent forms also fall within the scope defined by the appended claims of the application.

Claims (7)

1. A device for multi-host shared memory access, characterized in that it comprises: multiple hosts, a bus, multiple control registers, protection circuits, and multiple memory spaces, wherein the multiple control registers and the multiple One-to-one correspondence between memory spaces, the plurality of hosts are connected to the bus through a write bus and a read bus, the bus is connected to the plurality of control registers and the protection circuit through a write bus, and the plurality of control registers and The multiple memory spaces are connected to the bus through a read bus, and the protection circuit is connected to the multiple memory spaces. 2. The device for multi-host shared memory access according to claim 1, wherein each of said control registers comprises: a first comparator, a second comparator, a first AND gate, a first strobe and trigger; The first input terminal of the first comparator, the first input terminal of the first selector are connected to the output terminal of the flip-flop, the second input terminal of the first comparator is connected to a preset value, The output end of the first comparator is connected to the first input end of the first AND gate; The first input end of the second comparator is connected to the read address signal, the second input end is connected to the register address, and the output end is connected to the second input end of the first AND gate; The enable end of the first AND gate is connected to a read enable signal, and the output end is connected to the enable end of the first strobe; The second input end of the first strobe is connected to the host serial number, the output end is connected to the data end of the flip-flop, and the enable end of the flip-flop is connected to a clock signal. 3. The device for multi-host shared memory access according to claim 2, wherein the read enable signal is in an active state, and the output of the flip-flop in the current clock cycle of the clock signal is the The preset value, the value of the flip-flop is updated to the serial number of the host, and the output of the next clock cycle of the clock signal is the serial number of the host. 4. The device for multi-host shared memory access according to claim 2, wherein each of the control registers further comprises: a third comparator, a fourth comparator, a second AND gate and a second strobe ; The first input end of the third comparator, the first input end of the second selector are connected to the output end of the flip-flop, the second input end of the third comparator is connected to the host serial number, The output end of the third comparator is connected to the first input end of the second AND gate; The first input end of the fourth comparator is connected to the write address signal, the second input end is connected to the register address, and the output end is connected to the second input end of the second AND gate; The enable end of the second AND gate is connected to the write enable signal, and the output end is connected to the enable end of the second gate; The second input end of the second gate is connected to a preset value, the output end is connected to the data end of the flip-flop, and the enable end of the flip-flop is connected to a clock signal. 5. The device for multi-master shared memory access according to claim 4, wherein the write enable signal is in an active state, and the output of the flip-flop in the current clock cycle of the clock signal is the the serial number of the host, and the value of the trigger is updated to the preset value. 6. The device for multi-host shared memory access according to claim 1, wherein the protection circuit comprises: A multiplexer, the input end of the multiplexer is connected to the output end of each of the plurality of control registers, and the enable end is connected to the memory write address signal; A fifth comparator, the first input terminal of the fifth comparator is connected to the output terminal of the multiplexer, and the second input terminal is connected to the serial number of the write access host; and A third AND gate, the first input end of the third AND gate is connected to the output end of the fifth comparator, the second input end is connected to the memory write enable signal, and the output end is connected to the plurality of memory spaces. 7. The device for multi-host shared memory access according to claim 6, wherein the enabling end of the multiplexer is connected to an interval judgment logic, and the interval judgment logic is used to write address according to the memory The signal judgment gates one of the plurality of control registers.

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