CN218549896U

CN218549896U - Signal detection circuit and image sensor

Info

Publication number: CN218549896U
Application number: CN202221840068.7U
Authority: CN
Inventors: 杨光; 杨靖; 侯金剑; 任冠京; 莫要武
Original assignee: Sitway Shenzhen Electronic Technology Co ltd
Current assignee: Sitway Shenzhen Electronic Technology Co ltd
Priority date: 2022-07-14
Filing date: 2022-07-14
Publication date: 2023-02-28
Anticipated expiration: 2032-07-14

Abstract

The application provides a signal detection circuit and an image sensor, wherein the signal detection circuit comprises a reference voltage generator, a reference voltage generation circuit, a selection circuit, a signal quantization circuit and a comparison circuit; the reference voltage generator is used for generating a reference voltage; the reference voltage generating circuit is used for generating a reference voltage; the selection circuit is used for selecting a signal to be tested; the signal quantization circuit is used for carrying out digital quantization conversion on the signal to be detected according to the reference voltage and the reference voltage so as to obtain quantization information; the comparison circuit is used for generating a detection result of the signal to be detected according to whether the quantization information meets a preset condition. The signal detection circuit and the image sensor provided by the application realize the voltage and current compatible detection function by quantizing and judging the internal reference voltage and the internal reference current.

Description

Signal detection circuit and image sensor

Technical Field

The application relates to the technical field of signal detection, in particular to a signal detection circuit and an image sensor.

Background

In order to avoid unreasonable risks caused by hazards due to electrical system failure behaviors, electronic products for automotive applications need to meet the international standard requirements of ISO 26262. For an automobile chip, failure modes, influences and diagnosis analysis need to be performed on an internal functional safety module, and a module violating a functional safety target fails due to the fact that no corresponding functional safety mechanism exists, so that a single-point fault is formed, the fault diagnosis coverage rate is reduced, and even adverse influences on ASIL grade rating may be possibly generated. The power, ground, reference voltage generated internally within the chip (hereinafter referred to as internal reference voltage), and reference current generated internally (hereinafter referred to as internal reference current) signals are the basis for the normal operation of the chip.

During the process of designing and implementing the application, the applicant finds that at least the following problems exist: the abnormality of the internal reference voltage and the internal reference current may possibly cause the abnormality or even the loss of the whole function of the chip, thereby causing the functional safety risk, and the accuracy of the abnormality or the loss of the whole function of the chip needs to be monitored in the working process of the chip.

The foregoing description is provided for general background information and does not necessarily constitute prior art.

Disclosure of Invention

The application provides a signal detection circuit, a signal detection method, an image sensor and a storage medium, which are used for relieving the problem that a chip lacks voltage and current detection capability.

In one aspect, the present application provides a signal detection circuit, specifically, comprising a reference voltage generator, a reference voltage generation circuit, a selection circuit, a signal quantization circuit and a comparison circuit;

the reference voltage generator is used for generating a reference voltage;

the reference voltage generating circuit is used for generating a reference voltage;

the selection circuit is used for selecting a signal to be tested;

the signal quantization circuit is respectively connected with the reference voltage generator, the reference voltage generation circuit and the selection circuit and is used for carrying out digital quantization conversion on the signal to be detected according to the reference voltage and the reference voltage so as to obtain quantization information;

the comparison circuit is connected with the signal quantization circuit and used for generating a detection result of the signal to be detected.

Optionally, the signal quantization circuit in the signal detection circuit comprises a current conversion circuit, a sigma-delta ADC, and a counter;

the current conversion circuit comprises a reference current source for converting the reference voltage into reference current and a current source to be tested for converting the signal to be tested into current to be tested;

the sigma-delta ADC is used for performing analog-to-digital quantization conversion on the current to be measured according to the reference current and the reference voltage to acquire a quantization signal;

the counter is used for generating a counting result as the quantization information according to the quantization signal.

Optionally, the driving clock signal of the sigma-delta ADC and the quantized signal of the output in the signal detection circuit have a delay matching circuit.

Optionally, the counter in the signal detection circuit counts using a driving clock signal of the sigma-delta ADC.

Optionally, the signal quantization circuit in the signal detection circuit further includes a current amplification circuit, and when the signal to be detected selected by the selection circuit is a current signal, the current amplification circuit amplifies the current signal to be the current to be detected.

Optionally, the current amplification circuit in the signal detection circuit is selected by a current mirror and a switch to realize different current gains.

Optionally, the current conversion circuit in the signal detection circuit further includes a substrate current source for converting the reference voltage into a substrate current;

the substrate current source is connected with the current source to be tested in parallel.

Optionally, the signal quantization circuit in the signal detection circuit further includes a load capacitor and a first comparator, a first end of the load capacitor is grounded, and a second end of the load capacitor is connected to the current input end of the current source to be detected and the current output end of the reference current source; the first input end of the first comparator is connected with the second end of the load capacitor, and the reference voltage is input to the second input end of the first comparator.

Optionally, the signal quantization circuit in the signal detection circuit further includes a charge control switch, a first end of the charge control switch is connected to the output end of the reference current, a second end of the charge control switch is connected to the second end of the load capacitor, and a third end of the charge control switch is connected to the output end of the first comparator.

Optionally, the current conversion circuit in the signal detection circuit comprises a first conversion circuit comprising a second comparator, at least one first switching element, at least one second switching element, a third switching element and a first resistor;

the first input end of the second comparator inputs the reference voltage, the second input end of the second comparator is connected with the output end of the at least one first switching element, the output end of the second comparator is connected with the control end of the at least one first switching element and the control end of the at least one second switching element, and the second input end of the second comparator is grounded through the first resistor;

the control end of the at least one first switch piece and the input end of the at least one second switch piece are connected with a first preset voltage, the output end of the at least one second switch piece is connected with the control end and the input end of the third switch piece, and the output end of the third switch piece is grounded.

Optionally, the first switching circuit in the signal detection circuit further includes at least one first switch, and at least one first switch is correspondingly connected to the second input terminal of the second comparator through one first switch; and/or the first conversion circuit further comprises at least one second switch, and at least one second switch is correspondingly connected with the control end of the third switch through one second switch.

Optionally, the first switching circuit in the signal detection circuit further includes a third switch connected between a control terminal of the third switch element and ground.

Optionally, the current converting circuit in the signal detecting circuit comprises a second converting circuit, the second converting circuit comprising a third comparator, at least one fourth switching element, a fifth switching element, a sixth switching element and a second resistor;

a first input end of the third comparator inputs a voltage to be detected, a second input end of the third comparator is connected with an output end of the at least one fourth switching element, an output end of the third comparator is connected with a control end of the at least one fourth switching element and a control end of the fifth switching element, and a second input end of the third comparator is grounded through the second resistor;

the control end of the at least one fourth switching element and the input end of the fifth switching element are connected with a second preset voltage, the output end of the fifth switching element is connected with the control end and the input end of the sixth switching element, and the output end of the sixth switching element is grounded.

Optionally, the second conversion circuit in the signal detection circuit further includes at least one fourth switch, and at least one of the fourth switches is correspondingly connected to the second input terminal of the third comparator through one fourth switch.

Optionally, the second conversion circuit in the signal detection circuit further includes a voltage range selection circuit, where the voltage range selection circuit includes a fifth switch, a sixth switch, a seventh switch, a third resistor, a fourth resistor, a fifth resistor, and a sixth resistor;

first ends of the fifth switch, the sixth switch and the seventh switch are used for inputting the voltage to be measured, and a second end of the seventh switch is connected with a first input end of the third comparator;

the second end of the fifth switch is grounded through a third resistor and a fourth resistor which are connected in series, the common end of the third resistor and the fourth resistor is connected with the first input end of the third comparator, and/or the second end of the sixth switch is connected with a third preset voltage through a fifth resistor and a sixth resistor which are connected in series, and the common end of the fifth resistor and the sixth resistor is connected with the first input end of the third comparator.

Optionally, the second conversion circuit in the signal detection circuit implements different gains through a current mirror structure and switch selection.

In another aspect, the present application provides a signal detection method, in particular, for use in a signal detection circuit as described above, the signal detection method comprising:

s1: responding to the selection of the signal to be detected, and acquiring a reference voltage and a reference voltage;

s2: according to the reference voltage and the reference voltage, carrying out digital quantization conversion on the signal to be detected to obtain quantization information;

s3: and generating a detection result of the signal to be detected according to whether the quantitative information meets a preset condition.

Optionally, the step of performing digital quantization conversion on the signal to be detected according to the reference voltage and the reference voltage to obtain quantization information by the signal detection method includes:

s10: converting the signal to be measured into a current to be measured;

s20: discharging a load capacitor of the comparator by using the current to be detected;

s30: when the voltage of the load capacitor is smaller than the reference voltage, charging the load capacitor by using a reference current until the voltage of the load capacitor is larger than the reference voltage;

s40: and when the voltage of the load capacitor is greater than the reference voltage, disconnecting the reference current until the voltage of the load capacitor is less than the reference voltage, and returning to S30.

Optionally, the signal detection method, when performing the step of discharging the load capacitance of the comparator with the current to be measured, includes:

s21: discharging the load capacitor with a substrate current;

s22: when the voltage of the load capacitor is smaller than the reference voltage, charging the load capacitor by using the reference current until the voltage of the load capacitor is larger than the reference voltage;

s23: and when the voltage of the load capacitor is greater than the reference voltage, disconnecting the reference current until the voltage of the load capacitor is less than the reference voltage, and returning to S21.

and simultaneously discharging the load capacitor by using the substrate current and the current to be measured which are connected in parallel.

Optionally, before the step of charging the load capacitor with the reference current is performed, the signal detection method includes:

in response to obtaining a reference voltage, converting the reference voltage to the reference current, a substrate current, and/or the reference voltage.

Optionally, the step of generating a detection result of the signal to be detected according to whether the quantization information satisfies a preset condition in the signal detection method includes:

the step of charging the load capacitor by the reference current and the step of discharging the load capacitor of the comparator by the current to be measured are modulated according to a clock signal to form waveform information for describing the duty ratio of the quantization information, and the counter counts the quantization information according to the clock signal and outputs a counting result;

when the counting result is within a preset threshold interval, judging that the signal to be detected meets the working requirement;

and when the counting result exceeds the preset threshold interval, judging that the signal to be detected does not meet the working requirement.

Optionally, the signal to be detected in the signal detection method is selected from at least one of a voltage signal, a current signal, a power signal and a ground signal.

In another aspect, the present application provides an image sensor, in particular, comprising a signal detection circuit as described above;

or, the image sensor comprises a processor and a storage medium connected to each other, wherein:

the storage medium is used for storing a computer program;

the processor is used for executing the computer program to realize the electrical property detection method.

Optionally, the image sensor implements the electrical property detection method in at least one frame time in a time division multiplexing manner.

Optionally, the image sensor implements the electrical property detection method synchronously within an image quantization time.

Optionally, the image sensor sets a preset threshold interval through a register.

Optionally, when the detection result in the image sensor exceeds the preset threshold interval, the image sensor generates overrun report information.

In another aspect, the present application provides a storage medium, in particular, having stored thereon a computer program, which when executed by a processor, implements the signal detection method as described above.

As described above, the present application provides a signal detection circuit, a signal detection method, an image sensor, and a storage medium, which implement a voltage and current compatible detection function by quantizing and determining an internal reference voltage and an internal reference current.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and, together with the description, serve to explain the principles of the application. In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the description of the embodiments will be briefly described below, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.

Fig. 1 is a structural diagram of a signal detection circuit according to an embodiment of the present application.

Fig. 2 is a block diagram of a signal quantization circuit according to an embodiment of the present application.

Fig. 3 is a circuit diagram of a signal quantization circuit according to the embodiment of fig. 2.

Fig. 4 is a circuit diagram of a first conversion circuit of a current conversion circuit according to an embodiment of the present application.

Fig. 5 is a circuit diagram of a second conversion circuit of the current conversion circuit according to an embodiment of the present application.

FIG. 6 is a circuit diagram of a voltage range selection circuit based on the embodiment of FIG. 5.

Fig. 7 is a flowchart of a signal detection method according to an embodiment of the present application.

FIG. 8 is a timing diagram of input clock and output signals according to an embodiment of the present application.

Fig. 9 is a circuit diagram of a voltage/current detection circuit according to an embodiment of the present application.

The implementation, functional features and advantages of the objectives of the present application will be further explained with reference to the accompanying drawings. With the above figures, there are shown specific embodiments of the present application, which will be described in more detail below. The drawings and written description are not intended to limit the scope of the inventive concepts in any manner, but rather to illustrate the concepts of the application by those skilled in the art with reference to specific embodiments.

Detailed Description

Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.

It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising a … …" does not exclude the presence of additional like elements in a process, method, article, or apparatus that comprises the element, and further, components, features, elements, and/or steps that may be similarly named in various embodiments of the application may or may not have the same meaning, unless otherwise specified by its interpretation in the embodiment or by context with further embodiments.

It should be understood that the specific embodiments described herein are merely illustrative of and not restrictive on the broad application.

First embodiment

In one aspect, the present application provides a signal detection circuit, and fig. 1 is a structural diagram of the signal detection circuit according to an embodiment of the present application.

Referring to fig. 1, in an embodiment, the signal detection circuit includes a reference voltage generator 10, a reference voltage generation circuit 20, a selection circuit 30, a signal quantization circuit 40, and a comparison circuit 50.

The reference voltage generator 10 is used to generate a reference voltage.

Alternatively, the reference voltage is generated by a bandgap reference voltage source and still be considered a stable reference voltage if the process corner or supply voltage or temperature is different.

The reference voltage generating circuit 20 is used to generate a reference voltage.

Alternatively, the reference voltage may be configured by a register, a value within a voltage range is selected, an optimal value is selected according to the actual measurement result, and theoretically, the influence of the used reference voltage on the device performance is very small.

The selection circuit 30 is used to select a signal to be measured.

Optionally, the signal to be measured may be a voltage signal to be measured or a current signal to be measured, which is not limited in this application.

The signal quantization circuit 40 is respectively connected to the reference voltage generator 10, the reference voltage generation circuit 20, and the selection circuit 30, and is configured to perform digital quantization conversion on the signal to be measured according to the reference voltage and the reference voltage to obtain quantization information.

The comparing circuit 50 is connected to the signal quantizing circuit 10, and is configured to generate a detection result of the signal to be detected according to whether the quantized information satisfies a preset condition.

Optionally, the quantitative information is compared with an expected value to obtain a judgment result. The signal detection circuit realizes the voltage and current compatible detection function by quantizing and judging the internal reference voltage and the internal reference current.

Referring to fig. 2, in one embodiment, the signal quantization circuit 40 of the signal detection circuit includes a current conversion circuit 41, a sigma-delta ADC (42), and a counter 43.

The current conversion circuit 41 includes a reference current source for converting a reference voltage into a reference current, and a current source to be measured for converting a signal to be measured into a current to be measured.

Optionally, when different current sources to be detected are selected for detection, the size of the reference current source does not need to be switched, and a fixed transfer function from a signal to be detected to an output signal can be obtained through the fixed reference current source and the reference voltage.

The sigma-delta ADC (42) is used for carrying out analog-to-digital quantization conversion on the current to be measured according to the reference current and the reference voltage so as to obtain a quantization signal.

Optionally, the sigma-delta ADC (42) is comprised of an analog sigma-delta modulator and a digital decimator.

The counter 43 is configured to generate a count result as quantization information from the quantization signal.

In the present embodiment, the current conversion circuit 41 in the signal quantization circuit 40 is used to convert the reference voltage and the voltage signal to be measured into the reference current source and the current source to be measured, so that the sigma-delta ADC (42) and the counter 43 perform digital quantization conversion on the signal to be measured to obtain quantization information.

In one embodiment, the drive clock signal of the sigma-delta ADC (42) and the output quantized signal in the signal detection circuit have delay matching circuits.

Optionally, the delay matching circuit can prevent individual rising edges or falling edges of the lost clock, and improve detection accuracy.

In one embodiment, the counter 43 in the signal detection circuit counts using the driving clock signal of the sigma-delta ADC (42).

Alternatively, the counter 43 may be implemented by a digital circuit, and the counter 43 may count the digital signal output from the sigma-delta ADC (42) using the driving clock signal of the sigma-delta ADC (42), or may count the driving clock signal and the output digital signal separately using an additional clock.

Referring to fig. 2, in an embodiment, the signal quantization circuit 40 in the signal detection circuit further includes a current amplification circuit 44, and when the signal to be measured selected by the selection circuit 30 is a current signal, the current amplification circuit 44 amplifies the current signal to be a current to be measured.

Alternatively, when the signal to be measured is a current signal, the current amplification circuit 44 refers to current signal processing as a quantized current signal for quantization of the current signal to be measured by the signal quantization circuit 40.

In one embodiment, the current amplification circuit 44 in the signal detection circuit is selected by a current mirror and a switch to achieve different current gains.

Alternatively, the current amplifying circuit 44 may stabilize the load capability of the current to be measured by using the precise current mirror function of the mirror current source. Alternatively, the current amplifying circuit 44 selects different combinations of gain circuits through a switch selection circuit, thereby providing the circuit structure with the capability of gain selection.

In one embodiment, the signal quantization circuit 40 in the signal detection circuit further includes a load capacitor C and a first comparator D1. The first end of the load capacitor C is grounded, and the second end of the load capacitor C is connected with the current input end of the current source Itest to be tested and the current output end of the reference current source Iref. A first input terminal of the first comparator D1 is connected to the second terminal of the load capacitor C, and a reference voltage Vref is input to a second input terminal of the first comparator D1.

Optionally, the current source Itest to be tested discharges the load capacitor C at the first input terminal of the first comparator D1. The reference voltage Vref is coupled to the second input terminal of the first comparator D1, and the first comparator D1 operates to convert the currently selected voltage or current into a digital signal under the driving of the clock signal.

Referring to fig. 3, in an embodiment, the current converting circuit 41 of the signal detecting circuit further includes a substrate current source Iofs for converting the reference voltage into the substrate current. The substrate current source Iofs is connected in parallel with the current source Itest to be measured.

Optionally, the substrate current source Iofs discharges the load capacitor C at the first input terminal of the first comparator D1.

In this embodiment, the reference current source Iref is used to implement a function of measuring the current source Itest to be measured by charging the load capacitor C, and the base current source Iofs ensures that an output duty ratio obtained when a zero signal is measured has a base value other than 0 by discharging the load capacitor C. The current source Itest to be tested and the base current source Iofs realize discharging to the load capacitor C by extracting positive charges (supplementing negative charges) from the load capacitor C.

In an embodiment, the signal quantization circuit 40 in the signal detection circuit further includes a charge control switch S, a first terminal of the charge control switch S is connected to the output terminal of the reference current, a second terminal of the charge control switch S is connected to the second terminal of the load capacitor C, and a third terminal of the charge control switch S is connected to the output terminal of the first comparator D1.

Optionally, the reference current source Iref charges the load capacitor C at the first input terminal of the first comparator D1 under the control of the charging control switch S. The output of the first comparator D1 controls whether the front stage charges or discharges the load capacitor C node through DFF (D-type trigger) beating, the capacitance voltage of the load capacitor C node is compared with the reference voltage Vref of the first comparator D1 to judge whether the current capacitance voltage state is higher or lower than the reference voltage Vref, the charging control switch S controls the discharging to the load capacitor C when the current capacitance voltage state is higher than the reference voltage Vref, otherwise, the charging to the load capacitor C is carried out, and therefore the function of controlling the charging time of the load capacitor C is achieved. The basic function of the sigma-delta ADC can be referred to for specific implementation principles, and will not be described herein again. In another embodiment, the reference current source Iref is controlled to ground by the inverse signal of the charge control switch S.

Referring to fig. 4, in an embodiment, the current converting circuit 41 in the signal detecting circuit includes a first converting circuit, and the first converting circuit includes a second comparator D2, at least one first switch S1, at least one second switch S2, a third switch S3, and a first resistor R1.

Optionally, the application does not limit the number of the first switching pieces S1 and the second switching pieces S2. The number of the first switching elements S1 and the second switching elements S2 is selected to be suitable in consideration of the cost and the gain. The size of the first resistor R1 is not limited in the present application. And selecting a proper size of the first resistor R1 by comprehensively considering the cost and the gain.

A first input end of the second comparator D2 inputs the reference voltage Vbg, a second input end of the second comparator D2 is connected to an output end of the at least one first switching element S1, an output end of the second comparator D2 is connected to a control end of the at least one first switching element S1 and a control end of the at least one second switching element S2, and a second input end of the second comparator D2 is grounded through the first resistor R1.

The control end of the at least one first switching element S1 and the input end of the at least one second switching element S2 are connected to a first preset voltage V1, the output end of the at least one second switching element S2 is connected to the control end and the input end of a third switching element S3, and the output end of the third switching element S3 is grounded.

Optionally, the third switch S3 forms the left side of the first current mirror, and accordingly, the current source in fig. 3 may be the right side of the first current mirror, enabling a stable current output of the current source. The output terminal of the second switching element S2 outputs the first current signal as the reference current signal of the first current mirror. The first preset voltage V1 is not limited in size. And selecting the proper first preset voltage V1 by comprehensively considering the cost and the gain. Exemplarily, the first conversion circuit of the current conversion circuit 41 realizes the conversion of the reference voltage Vbg into the reference current source Iref.

Referring to fig. 4, in an embodiment, the first converting circuit in the signal detecting circuit further includes at least one first switch S10, and the at least one first switch S1 is correspondingly connected to the second input terminal of the second comparator D2 through the first switch S10. The first conversion circuit further comprises at least one second switch S20, and the at least one second switch S2 is correspondingly connected with the control end of the third switch S3 through the one second switch S20.

Optionally, the application does not limit the number of the first switch S10 and the second switch S20. The number of the first switches S10 and the second switches S20 may be equal to the number of the first switching pieces S1 and the second switching pieces S2. The number of the first switch S10 and the second switch S20 is selected to be suitable in consideration of cost and gain.

Referring to fig. 4, in an embodiment, the first conversion circuit of the signal detection circuit further includes a third switch S30, and the third switch S30 is connected between the control terminal of the third switch S3 and the ground.

Optionally, the substrate current source Iofs is controlled to ground potential through the third switch S30.

In this embodiment, the first conversion circuit realizes the conversion capability from the reference voltage Vbg to the reference current source Iref and the substrate current source Iofs, the conversion function of the substrate current source Iofs can be turned off by turning off the second switch S20, and the gain selection capability of the reference current source Iref and the substrate current source Iofs can also be realized by turning on and off the first switch S10 and the second switch S20.

Referring to fig. 5, in an embodiment, the current converting circuit 41 in the signal detecting circuit includes a second converting circuit, which includes a third comparator D3, at least one fourth switching device S4, a fifth switching device S5, a sixth switching device S6, and a second resistor R2.

Optionally, the number of the fourth switching elements S4 is not limited in the present application. And selecting the number of the suitable fourth switching elements S4 by comprehensively considering the cost and the gain. The second resistor R2 is not limited in size in the present application. And selecting the proper size of the second resistor R2 by comprehensively considering the cost and the gain.

A voltage Vtest to be measured is input to a first input end of the third comparator D3, a second input end of the third comparator D3 is connected to an output end of the at least one fourth switching element S4, an output end of the third comparator D3 is connected to a control end of the at least one fourth switching element S4 and a control end of the fifth switching element S5, and a second input end of the third comparator D3 is grounded through the second resistor R2.

The control end of at least one fourth switching element S4 and the input end of the fifth switching element S5 are connected to the second preset voltage V2, the output end of the fifth switching element S5 is connected to the control end and the input end of the sixth switching element S6, and the output end of the sixth switching element S6 is grounded.

Optionally, the sixth switching element S6 forms the left side of the second current mirror, and accordingly, the current source in fig. 3 may be the right side of the second current mirror, achieving a stable current output of the current source. The output terminal of the fifth switching element S5 outputs the second current signal as the reference current signal of the second current mirror. The second preset voltage V2 is not limited in size in the present application. And selecting the proper magnitude of the second preset voltage V2 by comprehensively considering the cost and the gain. Illustratively, the second conversion circuit of the current conversion circuit 41 realizes the conversion of the signal to be tested into the current source Itest to be tested. In another embodiment, the size of the second resistor R2 may be the same as that of the first resistor R1, so that the conversion of the voltage to be measured Vtest to the current source to be measured Itest has the same gain as the conversion of the reference voltage Vbg to the reference current source Iref, and the switch with the current mirror structure can control the additional gain.

In an embodiment, the second switching circuit in the signal detection circuit further includes at least one fourth switch S40, and the at least one fourth switch S4 is correspondingly connected to the second input terminal of the third comparator D3 through the fourth switch S40.

Optionally, the application does not limit the number of the fourth switches S40. The number of the fourth switches S40 may be correspondingly equal to the number of the fourth switching pieces S4. The number of the fourth switches S40 is selected to be suitable in consideration of the cost and the gain. The second conversion circuit has a switched controllable extra gain of the current mirror structure by switching on and off the at least one fourth switch S40.

Referring to fig. 6, in an embodiment, the second converting circuit in the signal detecting circuit further includes a voltage range selecting circuit, and the voltage range selecting circuit includes a fifth switch S50, a sixth switch S60, a seventh switch S70, a third resistor R3, a fourth resistor R4, a fifth resistor R5, and a sixth resistor R6.

First ends of the fifth switch S50, the sixth switch S60 and the seventh switch S70 input a voltage Vtest to be measured, and a second end of the seventh switch S70 is connected to a first input end of the third comparator D3.

Optionally, the seventh switch S70 is connected to the third comparator D3 in a conducting manner, and the voltage Vtest to be measured can be directly input.

A second end of the fifth switch S50 is grounded through a third resistor R3 and a fourth resistor R4 connected in series, and a common end of the third resistor R3 and the fourth resistor R4 is connected to a first input end of the third comparator D3. In another embodiment, the second terminal of the sixth switch S60 is connected to the third preset voltage V3 through a fifth resistor R5 and a sixth resistor R6 connected in series, and a common terminal of the fifth resistor R5 and the sixth resistor R6 is connected to the first input terminal of the third comparator D3.

Optionally, the third resistor R3, the fourth resistor R4, the fifth resistor R5, the sixth resistor R6, and the third preset voltage V3 are not limited in size in this application. And comprehensively considering the cost and the voltage range, and selecting the proper sizes of the third resistor R3, the fourth resistor R4, the fifth resistor R5, the sixth resistor R6 and the third preset voltage V3. For example, the second conversion circuit may have a resistance voltage division structure, and the voltage range selection circuit may implement a voltage conversion capability supporting a power supply voltage higher than one time and lower than a ground voltage by one time by controlling the fifth switch S50, the sixth switch S60, and the seventh switch S70, thereby compressing the voltage to be measured Vtest and improving the measurement range of the entire system.

In one embodiment, the second switching circuit in the signal detection circuit realizes different gains through the current mirror structure and the corresponding fourth switch selection. The second switching circuit has gain selection capability through the configuration of the current mirror and the switch selection circuit.

Second embodiment

On the other hand, the present application provides a signal detection method, and fig. 7 is a flowchart of the signal detection method according to an embodiment of the present application.

Referring to fig. 7, in an embodiment, a signal detection method is applied to the signal detection circuit described above, and includes:

s1: in response to selecting a signal to be measured, a reference voltage and a reference voltage are acquired.

Alternatively, the reference voltage is generated by a bandgap reference voltage source and can still be considered a stable reference voltage if the process corner or supply voltage or temperature is different. The reference voltage can be configured by a register, a value in a voltage range is selected, an optimal value is selected according to an actual measurement result, and theoretically, the influence of the used reference voltage on the performance is very small.

s3: and generating a detection result of the signal to be detected according to whether the quantization information meets a preset condition.

In the embodiment, the signal detection method realizes the voltage and current compatible detection function by quantizing and judging the internal reference voltage and the internal reference current.

In one embodiment, the signal detection method performs S2: the step of performing digital quantization conversion on the signal to be measured to acquire quantization information according to the reference voltage and the reference voltage comprises the following steps:

s10: converting a signal to be measured into a current to be measured;

s20: discharging a load capacitor of the comparator by using the current to be measured;

s30: when the voltage of the load capacitor is smaller than the reference voltage, charging the load capacitor by using the reference current until the voltage of the load capacitor is larger than the reference voltage;

s40: when the voltage of the load capacitor is greater than the reference voltage, the reference current is turned off until the voltage of the load capacitor is less than the reference voltage, and the process returns to S30.

In this embodiment, the signal detection method controls the current to be measured to discharge the load capacitor at the input terminal of the comparator. And comparing the voltage of the load capacitor with the reference voltage of the comparator to judge whether the current capacitor voltage state is higher or lower than the reference voltage, and controlling the reference current to charge the load capacitor when the current capacitor voltage state is lower than the reference voltage, thereby realizing digital quantization of the signal to be detected.

In one embodiment, the signal detection method performs S20: the step of discharging the load capacitance of the comparator with the current to be measured may comprise or be preceded by:

s21: discharging the load capacitor by using the substrate current;

s23: when the voltage of the load capacitor is greater than the reference voltage, the reference current is turned off until the voltage of the load capacitor is less than the reference voltage, and the process returns to S21.

In the present embodiment, the signal detection method controls the substrate current to discharge the load capacitor at the input terminal of the comparator. And comparing the voltage of the load capacitor with the reference voltage of the comparator to judge whether the current capacitor voltage state is higher or lower than the reference voltage, and controlling the reference current to charge the load capacitor when the current capacitor voltage state is lower than the reference voltage.

In one embodiment, the signal detection method performs S20: the step of discharging the load capacitance of the comparator with the current to be measured comprises:

s24: and simultaneously discharging the load capacitor by using the parallel substrate current and the current to be measured.

Optionally, the substrate current is a discharge current, and it is ensured that an output duty ratio obtained when the zero signal is measured has a substrate value. The signal detection method realizes the discharge of the load capacitor by controlling the on-off of the substrate current connected in parallel.

In one embodiment, the signal detection method performs S22: the step of charging the load capacitor with the reference current is preceded by the steps of:

s25: in response to obtaining the reference voltage, the reference voltage is converted to a reference current, a substrate current, and/or a reference voltage.

Alternatively, the signal detection method can obtain a fixed transfer function from the signal to be detected to the output signal through a fixed reference voltage.

Referring to fig. 8, in an embodiment, the signal detection method performs S3: the step of generating the detection result of the signal to be detected according to whether the quantization information meets the preset condition comprises the following steps:

s31: the method comprises the steps of charging a load capacitor by reference current, discharging the load capacitor of a comparator by current to be measured according to clock signal modulation to form waveform information for describing the duty ratio of quantization information, and counting the quantization information by a counter according to the clock signal and outputting a counting result.

Illustratively, sel _ vtest<4:0>Selecting voltage Vtest, sel _ Vtest to be measured through mux<4:0>Is a 5bit register. The bit number of the register is not limited, and the bit number of the actual sel _ vtest is extensible during design, for example, 8 bits can be selected2 ⁸ The voltage or current to be measured.

S32: when the counting result is within a preset threshold interval, judging that the signal to be detected meets the working requirement;

s32: and when the counting result exceeds a preset threshold interval, judging that the signal to be detected does not meet the working requirement.

Optionally, the size of the preset threshold interval is not limited in the present application. And selecting the size of a proper preset threshold interval by comprehensively considering the cost and the detection precision.

In an embodiment, the application does not limit the type of the signal to be detected, and the signal to be detected in the signal detection method is selected from at least one of a voltage signal, a current signal, a power signal, and a ground signal.

Illustratively, the signal detection method is applied to a voltage/current detection circuit.

Referring to fig. 9 and also referring to fig. 1-8, the voltage/current detection circuit includes: the device comprises a reference voltage Vbg and reference voltage Vref generating circuit, a voltage/current selection circuit, an analog-to-digital conversion circuit and a comparison circuit; the voltage/current selection circuit comprises a selection switch for selecting a certain path of currently quantized voltage or current; the analog-to-digital conversion circuit quantizes a selected certain path of voltage or current; the comparison circuit compares the digital signal output by the analog-to-digital conversion circuit with an expected value to obtain a judgment result.

Further, the analog-to-digital conversion circuit comprises a voltage-to-current conversion circuit, a current amplification circuit, a sigma-delta type ADC and a counter.

Further, after the voltage/current selection circuit selects a certain current quantized voltage Vtest to be measured, the voltage signal Vtest is processed into a converted current signal Iv2i through a voltage to a second conversion circuit, after a certain current Itest to be measured is selected, the current signal is processed into a quantized current signal Iin through a current amplification circuit, meanwhile, a reference voltage Vbg is processed into a reference current signal Iref and a base current signal Iofs through another set of voltage to a first conversion circuit, the converted current signal Iv2i or the quantized current signal Iin and the base current signal Iofs discharge a load capacitor at one input end of the ADC, the reference current signal Iref charges a load capacitor at one input end of the ADC under the control of the sigma-delta ADC feedback switch, the reference voltage Vref is coupled to the other input end of the ADC, and the sigma-delta ADC operates under the drive of the clock signal Clk to convert the current selected voltage or current into the digital signal Vout.

Further, the voltage-to-first conversion circuit of the reference voltage Vbg may have conversion capabilities of the reference voltage Vbg to the reference current signal Iref and the reference voltage Vbg to the substrate current signal Iofs, the substrate current signal Iofs conversion function may be turned off by a switch, and the conversion capabilities of the reference current signal Iref and the substrate current signal Iofs may have gain selection capabilities.

Further, the voltage-to-second conversion circuit of the voltage Vtest to be measured may have a resistance voltage division structure, and may have a voltage conversion capability supporting a power supply voltage one time higher than a power supply voltage one time lower than a ground voltage.

Further, the voltage-to-second conversion circuit of the voltage to be measured may have the same gain, i.e. identical R1, R2 to Rn, as the voltage of the reference voltage Vbg to the reference current signal Iref in the first conversion circuit. The voltage to first conversion circuit and the voltage to second conversion circuit maintain consistent gains in design, and may have a switch controllable additional gain in a current mirror configuration.

Further, the current amplification circuit may have gain selection capability, such as different current gains through current mirrors and switch selection.

Further, the analog-to-digital conversion circuit has a switch to select whether the current detected is the voltage or the current, and the selection can be performed by using the signal of the voltage/current selection circuit.

Furthermore, the reference current signal Iref can be controlled to be connected to the ground potential through the inverse signal of the feedback switch, except for the time that the reference current signal Iref charges the load capacitor at one input end of the ADC under the control of the sigma-delta ADC feedback switch;

further, the driving clock signal Clk of the sigma-delta ADC and the output digital signal Vout may have a delay matching circuit.

Further, the counter may be implemented by a digital circuit, and the counter may count the digital signal Vout output by the sigma-delta ADC using the driving clock signal Clk of the sigma-delta ADC, or may count the driving clock signal Clk and the output digital signal Vout separately using an additional clock.

Further, the comparison circuit may be implemented by a digital circuit.

Based on the circuit, the signal detection method which can be realized by the image sensor comprises the following steps: the image sensor is integrated with a voltage/current detection circuit, a power supply signal, a ground signal, an internal reference voltage signal and an internal reference current signal which are expected to be detected are connected to a port of the voltage/current detection circuit, and the detected voltage/current is gated through a voltage/current selection circuit for quantification and judgment.

Further, the voltage/current detection circuit has a scalable port count.

Furthermore, the detection of voltage/current in the working process of the image sensor has a time-sharing multiplexing mode; the voltage/current detection multiplexing circuit comprises an ADC, and circuit resources are saved.

Furthermore, all power supplies, grounds, internal reference voltages and internal reference currents which are expected to be detected in the working process of the image sensor can have the function of completing cyclic detection within one frame time and can also have the function of completing cyclic detection within multiple frames; by time-division multiplexing, multi-path voltage or current detection can be realized in one period.

Furthermore, the circulation detection function in the working process of the image sensor can be carried out in the image quantization time or can be carried out in the non-quantization time independently;

further, the threshold value of the image sensor for judging the quantized value of any one of the power supply, the ground, the internal reference voltage and the internal reference current can have a separate configuration function, such as setting through a register; by independently setting the judgment threshold, noise interference can be avoided.

Further, the image sensor may have a function of reporting to the outside of the image sensor if any of the power supply, the ground, the internal reference voltage, and the internal reference current is deemed to be out of an expected range after quantization and determination, such as by changing a pull-up or pull-down state of a specific pin.

The voltage/current detection circuit applied by the signal detection method is based on a delta-sigma ADC (analog to digital converter) framework, and can be compatible with level detection which is higher than one time of power supply voltage and lower than ground voltage by one time of power supply voltage. The voltage/current detection multiplexing comprises circuits including the ADC, and circuit resources are saved. Through time division multiplexing, multi-path voltage or current detection can be realized in one period. By independently setting the judgment threshold, noise interference can be avoided. The voltage to first conversion circuit and the voltage to second conversion circuit maintain a consistent gain in design.

Third embodiment

In another aspect, the present application provides an image sensor, in particular, an image sensor including the above signal detection circuit.

In another embodiment, an image sensor includes a processor and a storage medium coupled to each other, wherein: the storage medium is used for storing a computer program. The processor is used for executing the computer program to realize the signal detection method.

In the present embodiment, the image sensor realizes a voltage and current compatible detection function by quantizing and judging the internal reference voltage and the internal reference current.

In one embodiment, the image sensor implements the signal detection method in at least one frame time by means of time division multiplexing.

Optionally, the voltage/current detection in the working process of the image sensor has a time-division multiplexing form, the voltage/current detection multiplexes circuit components including the comparator, and the multiplexing of the voltage/current detection can realize multi-path voltage or current detection in one period through the time-division multiplexing, so that the circuit resources are saved.

In one embodiment, the image sensor synchronously implements a signal detection method within an image quantization time.

Optionally, all power supplies, grounds, internal reference voltages and internal reference currents which are expected to be detected in the working process of the image sensor may have a function of completing cycle detection within one frame time, and may also have a function of completing cycle detection within multiple frames, and a preset detection period for completing cycle detection within multiple frames may be changed. The circulation detection function in the working process of the image sensor can be carried out in the image quantization time or can be carried out in the non-quantization time independently.

In one embodiment, the image sensor sets the preset threshold interval through a register.

In this embodiment, the threshold value for the image sensor to determine the quantized value of any one of the power supply, the ground, the internal reference voltage, and the internal reference current may have a separate configuration function, such as being set by a register. The pattern sensor can avoid noise interference by independently setting the judgment threshold. Optionally, the judgment threshold set by the register is adjustable.

In one embodiment, when the detection result in the image sensor exceeds a preset threshold interval, the image sensor generates overrun report information.

In this embodiment, the image sensor may have a function of reporting to the outside of the image sensor if any one of the power supply, the ground, the internal reference voltage, and the internal reference current is deemed to be out of the expected range after quantization and determination. Illustratively, the graphical sensor may generate the alert information by changing the pull-up or pull-down state of a particular pin.

Illustratively, the image sensor voltage/current detection circuit has a scalable port count.

Illustratively, the image sensor incorporates a voltage/current detection circuit.

Further, after the voltage/current selection circuit selects a certain current quantized voltage Vtest to be measured, the voltage signal Vtest is processed into a converted current signal Iv2i through a voltage to a second conversion circuit, after a certain current Itest to be measured is selected, the current signal is processed into a quantized current signal Iin through a current amplification circuit, meanwhile, the reference voltage Vbg is processed into a reference current signal Iref and a base current signal Iofs through another set of voltage to a first conversion circuit, the converted current signal Iv2i or the quantized current signal Iin and the base current signal Iofs discharge to a load capacitor at one input end of the ADC, the reference current signal Iref charges the load capacitor at one input end of the ADC under the control of the sigma-delta ADC feedback switch, the reference voltage Vref is coupled to the other input end of the ADC, and the sigma-delta ADC operates under the drive of the clock signal Clk to convert the currently selected voltage or current into the digital signal Vout.

Further, the current amplification circuit may have gain selection capability, such as to achieve different current gains through current mirrors and switch selection.

Further, the comparison circuit may be implemented by a digital circuit.

Alternatively, based on the above circuit, the image sensor may have power, ground, internal reference voltage, and internal reference current detection capability, and the signal detection method of the image sensor may include: the image sensor is integrated with a voltage/current detection circuit, a power supply signal, a ground signal, an internal reference voltage signal and an internal reference current signal which are expected to be detected are connected to a port of the voltage/current detection circuit, and the detected voltage/current is gated through a voltage/current selection circuit for quantification and judgment.

Further, the voltage/current detection circuit has a scalable port count.

The voltage/current detection circuit of the image sensor is based on a delta-sigma ADC framework, and can be compatible with level detection of power supply voltage which is higher than one time of power supply voltage and lower than ground voltage by one time of power supply voltage. The voltage/current detection multiplexing circuit comprises an ADC, and circuit resources are saved. By time-division multiplexing, multi-path voltage or current detection can be realized in one period. By independently setting the judgment threshold, noise interference can be avoided. The voltage to first conversion circuit and the voltage to second conversion circuit maintain a consistent gain in design.

Fourth embodiment

In another aspect, the present application provides a storage medium, in particular, a storage medium having stored thereon a computer program, which when executed by a processor, implements the signal detection method as described above.

As described above, the signal detection circuit, method, image sensor and storage medium provided by the present application are based on a delta-sigma ADC architecture, and are capable of being compatible with level detection higher than one power supply voltage and lower than ground voltage by one power supply voltage. The voltage/current detection time division multiplexing circuit comprises an ADC (analog to digital converter), can realize multi-path voltage or current detection in one period, and saves circuit resources. By independently setting the judgment threshold, noise interference can be avoided. The first conversion circuit and the second conversion circuit maintain a uniform gain in design.

It should be noted that, in the present application, step numbers such as S10 and S20 are used for the purpose of more clearly and briefly describing corresponding contents, and do not constitute a substantial limitation on the sequence, and those skilled in the art may perform S20 first and then S10 in the specific implementation, but these should be within the protection scope of the present application.

In the embodiments of the storage medium provided in the present application, all technical features of any one of the above-mentioned method embodiments may be included, and the expanding and explaining contents of the specification are basically the same as those of the above-mentioned method embodiments, and are not described herein again.

Embodiments of the present application also provide a computer program product, which includes computer program code, when the computer program code runs on a computer, the computer is caused to execute the method in the above various possible embodiments.

Embodiments of the present application further provide a chip, which includes a memory and a processor, where the memory is used to store a computer program, and the processor is used to call and run the computer program from the memory, so that a device in which the chip is installed executes the method in the above various possible embodiments.

It is to be understood that the foregoing scenarios are only examples, and do not constitute a limitation on application scenarios of the technical solutions provided in the embodiments of the present application, and the technical solutions of the present application may also be applied to other scenarios. For example, as a person having ordinary skill in the art can know, with the evolution of the system architecture and the emergence of new service scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

The above-mentioned serial numbers of the embodiments of the present application are merely for description and do not represent the merits of the embodiments.

The steps in the method of the embodiment of the application can be sequentially adjusted, combined and deleted according to actual needs.

The units in the device in the embodiment of the application can be merged, divided and deleted according to actual needs.

In the present application, the same or similar term concepts, technical solutions and/or application scenario descriptions will be generally described only in detail at the first occurrence, and when the description is repeated later, the detailed description will not be repeated in general for brevity, and when understanding the technical solutions and the like of the present application, reference may be made to the related detailed description before the description for the same or similar term concepts, technical solutions and/or application scenario descriptions and the like which are not described in detail later.

In the present application, each embodiment is described with an emphasis on the description, and reference may be made to the description of other embodiments for parts that are not described or recited in any embodiment.

The technical features of the technical solution of the present application may be arbitrarily combined, and for brevity of description, all possible combinations of the technical features in the embodiments are not described, however, as long as there is no contradiction between the combinations of the technical features, the scope of the present application should be considered as being described in the present application.

The above description is only a preferred embodiment of the present application, and not intended to limit the scope of the present application, and all modifications of equivalent structures and equivalent processes, which are made by the contents of the specification and the drawings of the present application, or which are directly or indirectly applied to other related technical fields, are included in the scope of the present application.

Claims

1. A signal detection circuit is characterized by comprising a reference voltage generator, a reference voltage generation circuit, a selection circuit, a signal quantization circuit and a comparison circuit;

the reference voltage generator is used for generating a reference voltage;

the selection circuit is used for selecting a signal to be tested;

2. The signal detection circuit of claim 1, wherein the signal quantization circuit comprises a current conversion circuit, a sigma-delta ADC, and a counter;

the current conversion circuit comprises a reference current source for converting the reference voltage into reference current and a current source to be detected for converting the signal to be detected into current to be detected;

the sigma-delta ADC is used for performing analog-to-digital quantization conversion on the current to be measured according to the reference current and the reference voltage to obtain a quantization signal;

3. The signal detection circuit of claim 2, wherein a driving clock signal of the sigma-delta ADC and the quantized signal of the output have a delay matching circuit.

4. The signal detection circuit of claim 2, wherein the counter counts using a drive clock signal of the sigma-delta ADC.

5. The signal detection circuit according to claim 2, wherein the signal quantization circuit further includes a current amplification circuit, and when the signal to be measured selected by the selection circuit is a current signal, the current amplification circuit amplifies the current signal into the current to be measured.

6. The signal detection circuit of claim 5, wherein the current amplification circuit is selected by a current mirror and a switch to achieve different current gains.

7. The signal detection circuit of claim 2, wherein the current conversion circuit further comprises a substrate current source for converting the reference voltage to a substrate current;

8. The signal detection circuit of claim 2, wherein the signal quantization circuit further comprises a load capacitor and a first comparator, a first end of the load capacitor is connected to ground, and a second end of the load capacitor is connected to the current input terminal of the current source to be measured and the current output terminal of the reference current source; the first input end of the first comparator is connected with the second end of the load capacitor, and the reference voltage is input to the second input end of the first comparator.

9. The signal detection circuit of claim 8, wherein the signal quantization circuit further comprises a charge control switch, a first terminal of the charge control switch is connected to the output terminal of the reference current, a second terminal of the charge control switch is connected to the second terminal of the load capacitor, and a third terminal of the charge control switch is connected to the output terminal of the first comparator.

10. The signal detection circuit of any one of claims 2-9, wherein the current conversion circuit comprises a first conversion circuit comprising a second comparator, at least one first switching element, at least one second switching element, a third switching element, and a first resistor;

11. The signal detection circuit of claim 10 wherein said first switching circuit further comprises at least one first switch, at least one of said first switch elements being connected to said second comparator second input terminal via a respective first switch; and/or the first conversion circuit further comprises at least one second switch, and at least one second switch is correspondingly connected with the control end of the third switch through one second switch.

12. The signal detection circuit of claim 10, wherein the first conversion circuit further comprises a third switch connected between a control terminal of the third switch component and ground.

13. The signal detection circuit of any of claims 2-9, wherein the current conversion circuit comprises a second conversion circuit comprising a third comparator, at least one fourth switching element, a fifth switching element, a sixth switching element, and a second resistor;

14. The signal detection circuit of claim 13, wherein the second switching circuit further comprises at least one fourth switch, at least one of the fourth switches being connected to the second input of the third comparator via a fourth switch.

15. The signal detection circuit of claim 13, wherein the second conversion circuit further comprises a voltage range selection circuit comprising a fifth switch, a sixth switch, a seventh switch, a third resistor, a fourth resistor, a fifth resistor, and a sixth resistor;

16. The signal detection circuit of claim 13, wherein the second switching circuit achieves different gains through current mirror structures and switch selection.

17. An image sensor comprising the signal detection circuit according to any one of claims 1 to 16.

18. The image sensor of claim 17, wherein the image sensor operates the signal detection circuit for at least one frame time by time-division multiplexing.

19. The image sensor of claim 17, wherein the image sensor operates the signal detection circuit synchronously during an image quantization time.

20. The image sensor of claim 17, wherein the image sensor sets the preset threshold interval through a register.