CN219873512U

CN219873512U - Electronic device and package

Info

Publication number: CN219873512U
Application number: CN202320114145.9U
Authority: CN
Inventors: 陈永; D·加尼
Original assignee: STMicroelectronics SA
Current assignee: STMicroelectronics SA
Priority date: 2022-01-20
Filing date: 2023-01-18
Publication date: 2023-10-20
Anticipated expiration: 2033-01-18
Also published as: CN116469861A

Abstract

Embodiments of the present disclosure relate to electronic devices and packages. An electronic device, comprising: a die having a first surface and a second surface opposite the first surface; a first laminate layer on the first surface of the die; a plurality of openings through the first laminate layer; a redistribution layer on the first lamination layer extending through the plurality of openings to the first surface of the die; a plurality of pillars on the redistribution layer, each pillar comprising a first surface on the redistribution layer, a second surface of the pillar opposite the first surface of the pillar, a sidewall between the first surface of the pillar and the second surface of the pillar; a second laminate layer on the redistribution layer and the first laminate layer; a plurality of channels in the second laminate layer surrounding the plurality of posts, at least a portion of the sidewall and the second surface of each post being exposed to an external environment through the plurality of channels. With embodiments of the present disclosure, the reliability and expected life cycle of a semiconductor package are advantageously improved.

Description

Electronic device and package

Technical Field

The present disclosure relates to a semiconductor package, and more particularly, to a semiconductor package having exposed electrical contacts.

Background

A typical semiconductor package includes an integrated circuit packaged on a die in a molding compound. The package includes mounting posts electrically connected to the die, only one surface of the posts being exposed on an outer surface of the package. The posts on the package enable connection between the integrated circuit on the die and the printed circuit board. In many cases, the package is physically and electrically connected to pads on the circuit board by solder between the pads on the circuit board and the posts of the package. However, generally due to the scaling requirements of integrated circuits and packages, the mounting posts of packages become smaller as packages become smaller. The reduced size of the exposed mounting posts on the known packages results in only a small surface area available for soldering. As a result, the known packages have a weak connection with solder, which results in a number of disadvantages.

For example, cracks may form in the solder connection between the package and the circuit board and cause electrical disconnection between the mounted package and the circuit board. The electrical disconnection renders the package inoperative for its intended purpose. In addition to the rupture, the package may be separated from the board if the solder connection fails. As a result, the known packages have reliability and performance problems that may occur due to the drawbacks of the conventional structure and method for connecting the packages to the board. Accordingly, there is a need for a semiconductor package that overcomes the above-described drawbacks.

Disclosure of Invention

It is an object of the present disclosure to provide an electronic device and a package to at least partially solve the above-mentioned problems in the prior art.

An aspect of the present disclosure provides a device comprising: a die having a first surface and a second surface opposite the first surface; a first laminate layer on a first surface of the die; a plurality of openings through the first laminate layer; a redistribution layer on the first laminate layer, the redistribution layer extending through the plurality of openings to the first surface of the die; a plurality of pillars on the redistribution layer, each pillar of the plurality of pillars including a first surface on the redistribution layer, a second surface of the pillar opposite the first surface of the pillar, and a sidewall between the first surface of the pillar and the second surface of the pillar; a second laminate layer on the redistribution layer and the first laminate layer; a plurality of channels in the second laminate layer surrounding the plurality of posts, the second surface of each post of the plurality of posts and at least a portion of the sidewall exposed to an external environment through the plurality of channels.

In accordance with one or more embodiments, wherein the semiconductor package further comprises: a molding compound on the second surface of the die and the first laminate layer; plating on the second surface of each of the plurality of posts and the at least a portion of the sidewall.

The one or more embodiments, wherein the plurality of channels extend to the redistribution layer.

In accordance with one or more embodiments, wherein the plurality of channels have a depth that is less than a majority of a height of the sidewall of each of the plurality of posts.

In accordance with one or more embodiments, wherein the plurality of channels have a depth that is greater than a height of the sidewall of each of the plurality of posts.

In accordance with one or more embodiments, wherein the second laminate layer includes an outer surface, the second surface of each of the plurality of posts is aligned with the outer surface of the second laminate layer.

In accordance with one or more embodiments, the plurality of channels extends around an entire perimeter of the plurality of posts.

Yet another aspect of the present disclosure provides a package, comprising: a die having a first surface and a second surface opposite the first surface; a redistribution layer on the first surface of the die; a plurality of conductive extensions on the redistribution layer, each conductive extension of the plurality of conductive extensions including a first surface on the redistribution layer, a second surface of the conductive extension opposite the first surface of the conductive extension, and a sidewall between the first surface of the conductive extension and the second surface of the conductive extension; a lamination layer on the first surface of the die and on at least a portion of the redistribution layer; and a hole in the laminate layer at an interface between at least one of the plurality of conductive extensions and the laminate layer, second surface.

According to one or more embodiments, further comprising: and a plating layer on at least one of the plurality of conductive extensions.

According to one or more embodiments, wherein the plating is located on the second surface of the at least one of the plurality of conductive extensions and at least a portion of the sidewall.

The one or more embodiments, wherein the hole has a depth greater than a height of the sidewall of the at least one of the plurality of conductive extensions.

In accordance with one or more embodiments, the aperture extends around less than an entire perimeter of the at least one plurality of conductive extensions.

The one or more embodiments, wherein the laminate layer comprises a first laminate layer between the first surface of the die and the redistribution layer, and a second laminate layer on the first laminate layer and the at least a portion of the redistribution layer, the aperture in the second laminate layer.

Another aspect of the present disclosure provides a package, comprising: a die having a first surface and a second surface opposite the first surface; a plurality of conductive extensions on the first surface of the die, each conductive extension of the plurality of conductive extensions comprising a first surface, a second surface, and a sidewall between the first surface of the conductive extension and the second surface of the conductive extension; a lamination layer on the first surface of the die; and a channel in the laminate layer between the sidewall of the conductive stud and the inner sidewall of the laminate layer.

According to one or more embodiments, wherein the laminate layer comprises a plurality of openings, the package further comprises: a redistribution layer on the laminate layer and extending through the plurality of openings to the first surface of the die, the plurality of conductive extensions being on the redistribution layer.

The laminate layer includes a first laminate layer and a second laminate layer, the first laminate layer being between the first surface of the die and the redistribution layer, and the second laminate layer being on the first laminate layer.

According to one or more embodiments, the package further comprises: plating on a second surface of the at least one of the plurality of conductive extensions and at least a portion of the sidewall.

According to one or more embodiments, wherein the channel is one of a plurality of channels surrounding the at least one of the plurality of conductive extensions, the laminate layer extends between successive ones of the plurality of channels.

According to one or more embodiments, wherein the channel has a depth that is greater than a majority of a height of the sidewall of the at least one of the plurality of conductive extensions.

According to one or more embodiments, the package further comprises: plating over a majority of a height of the second surface of the at least one of the plurality of conductive extensions and the sidewall.

With embodiments of the present disclosure, the reliability and expected life cycle of a semiconductor package are advantageously improved.

Drawings

The present disclosure will be more fully understood by reference to the following drawings, which are for illustrative purposes only. These non-limiting and non-exhaustive embodiments are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified. The dimensions and relative positioning of elements in the drawings are not necessarily drawn to scale in some figures. For example, the shapes of the various elements are selected, enlarged, and positioned to enhance drawing clarity. In the other figures, the dimensions and relative positioning of the elements in the figures are precisely to scale. The particular shapes of the elements as drawn, are selected for ease of recognition in the drawings. The figures do not describe every aspect of the teachings disclosed herein and do not limit the scope of the claims.

FIG. 1 is a cross-sectional view of a known semiconductor package;

Fig. 2 is a bottom plan view of an embodiment of a semiconductor package with exposed mounting posts according to the present disclosure;

FIG. 3 is a cross-sectional view of the semiconductor package of FIG. 2 taken along line A-A in FIG. 2;

fig. 4 is a cross-sectional view of the semiconductor package of fig. 2 mounted to a printed circuit board;

5A-5L are cross-sectional views of steps in an embodiment of a manufacturing process of a semiconductor package according to the present disclosure;

fig. 6 is a cross-sectional view of an embodiment of a semiconductor package with partially exposed mounting posts according to the present disclosure;

fig. 7 is an isometric view of an embodiment of a semiconductor package with partially exposed mounting posts according to the present disclosure;

FIG. 8 is a cross-sectional view of an embodiment of a semiconductor package having a sidewall of a mounting post exposed to a redistribution layer of the package according to the present disclosure; and

fig. 9 is a cross-sectional view of an embodiment of a semiconductor package according to the present disclosure, wherein the sidewalls of the mounting posts are exposed to a depth less than a majority of the height of the sidewalls.

Detailed Description

Those of ordinary skill in the art will appreciate that the present disclosure is illustrative only and is not limiting in any way. Other embodiments of the disclosed systems and methods will be apparent to those skilled in the art from consideration of this disclosure.

Each of the features and teachings disclosed herein can be used alone or in combination with other features and teachings to form variations on such packages. Representative examples of utilizing many of these additional features and teachings, both separately and in combination, are described in more detail with reference to fig. 1-9. This detailed description is merely intended to teach a person of ordinary skill in the art further details for practicing aspects of the disclosure and is not intended to limit the scope of the claims. Thus, combinations of features disclosed in the detailed description may not be necessary to practice the disclosure in the broadest sense and are instead taught merely to particularly describe representative examples of the disclosure.

In the following description, for purposes of explanation only, specific nomenclature is set forth to provide a thorough understanding of the present systems and methods. It will be apparent, however, to one skilled in the art that these specific details are not required in order to practice the teachings of the present devices, systems, and methods.

Fig. 1 illustrates a known semiconductor package 20 to provide additional context for the advantages of the embodiments of the present disclosure. Package 20 includes a die 22 encapsulated with a molding compound 24. The die 22 is electrically connected to contacts 26 on a bottom surface 28 of the package 20. The contacts 26 are in turn coupled to pads 30 on a circuit board 32 by solder 34 to establish electrical connection between the die 22 and the board 32. As shown in fig. 1, the contacts 26 may be coplanar with the bottom surface 28 of the package 20, or may extend slightly beyond the bottom surface 28 of the package 20. Thus, the only surface area of the contacts 26 available for bonding to the solder 34 is the exposed bottom surface of the contacts 26 at the bottom of the package 20. Because the exposed surface of the contact 26 is small in area, it is difficult to establish a strong bond between the contact 26 and the solder 34. In other words, the relatively small exposed surface area of the contacts 26 results in a weak bond with the solder 34, which is prone to cracking. Cracks in the solder 34 may cause electrical disconnection between the package 20 and the circuit board 32, rendering the package 20 nonfunctional. Furthermore, if the solder connection fails, the package 20 may be completely separated from the board 32. Thus, the known packages have reliability and performance issues that may be caused by the soldered connection between the package 20 and the circuit board 32.

In contrast, the present disclosure generally relates to a semiconductor package having exposed electrical contacts that increase the surface area for bonding with solder when the package is mounted to a printed circuit board. As will be described in more detail below, the sidewalls of the contacts are exposed to significantly increase the surface area available for bonding with solder. The increase in available surface area results in a stronger bond between the package and the solder, which in turn reduces the likelihood of cracking or separation. Accordingly, the concepts of the present disclosure improve the reliability and expected life cycle of the semiconductor package.

Fig. 2 is a bottom plan view of an embodiment of a semiconductor package 100 according to the present disclosure. Fig. 3 is a cross-sectional view of the package 100 along line A-A in fig. 2. Beginning with fig. 3, the package 100 includes a die 102 having a first or inactive surface 104 and a second or active surface 106 opposite the first surface 104. The die 102 may be any semiconductor material, such as silicon in a non-limiting example, and includes an integrated circuit formed in or on the second surface 106. A first laminate layer 108 is on the second surface 106 of the die 102. As described in more detail below, a plurality of vias or openings 109 (fig. 5C) extend through the first laminate layer 108 to make electrical connection through the package 100 to the die 102. A redistribution layer 110 is on the first laminate layer 108 and extends to the first surface 104 of the die 102 through the vias 109 (fig. 5C). A plurality of electrical contacts 112 (which may also be referred to herein as a plurality of mounting posts or conductive extensions or contact pads 112 or a plurality of posts 112) are formed on the redistribution layer 110. In some embodiments, the second lamination layer 114 is disposed on the redistribution layer 110 and on at least a portion of the contacts 112. In some non-limiting examples, the redistribution layer 110 and the plurality of contacts 112 are copper, although different metals or metal alloys may be selected for the redistribution layer 110 and the contacts 112. Further, the laminate layers 108, 114 may be Build-up films (Build-up films) or any other insulating or dielectric material.

The die 102 and the first laminate layer 108 are encapsulated with a molding compound 116 to complete the package 100. Specifically, the molding compound 116 is on the first or inactive surface 104 of the die 102 and may be selected from any number of commercially available products. Thus, the package 100 has a first or top surface 118 and a second or bottom surface 120 opposite the first surface 118. In some embodiments, the molding compound 116 defines a boundary of a first surface 118 of the package 100, and the second laminate layer 114 defines a boundary of a second surface 120 of the package 100. The second surface 120 of the package 100 is shown in more detail in fig. 2.

The package 100 also includes a plurality of channels or grooves 122 extending into the second laminate layer 114 around the plurality of contacts 112. The second laminate layer includes an inner sidewall facing the contact 112. There is a gap or space between the inner side walls of the laminate layer and the side walls of the contacts 112.

Further, a plating or conductive layer 124 is provided or formed on each contact 112. The plating 124 may be a nickel-gold alloy, or any other selected metal or metal alloy. The plating 124 prevents oxidation or corrosion of the contacts 112 and, in some embodiments, the material used for the plating 124 may be selected to improve adhesion to solder as compared to the copper material of the contacts 112. Although the plating 124 is not necessarily required in the package 100, the plating 124 is included in the preferred embodiment to prevent oxidation and improve the reliability and life cycle of the package 100. Dashed line 126 in fig. 3 represents the interface between contact 112 and redistribution layer 110. In practice, there may be visible lines between these structures because the contacts 112 are formed on the redistribution layer 110 in a separate manufacturing step described below. However, for simplicity in the drawing, this line is represented by dashed line 126.

The contact 112 has a first or top surface 128 and a second or bottom surface 130 opposite the first surface 128. As shown in fig. 3, the first surface 128 of each contact 112 is on the redistribution layer 110. The second surface 130 is spaced apart from the first surface 128 across a sidewall 132 of the contact 112. In other words, the sidewall 132 of each contact 112 extends between the first surface 128 and the second surface 130 of each contact 112.

Plating 124 is on at least a portion of second surface 130 and sidewall 132 of each contact 112. Although the plating 124 is shown on a majority of the sidewalls 132 of each contact 112 in fig. 3, other configurations are possible and described in more detail herein. Thus, in some embodiments, the plating 124 and the second laminate layer 114 define a plurality of channels 122. Because the plating layer 124 is preferably a metal or metal alloy, the solder may form a strong bond with the plating layer 124. In addition, at least a portion of the sidewall 132 of each contact 112 is exposed through the corresponding channel 122 to increase the surface area for bonding with solder. As described above, the increased surface area results in a stronger bond relative to known packages. In some embodiments, the second surface 130 of the contact 112 is coplanar with the outer surface of the second laminate layer 114 or recessed relative to the outer surface of the second laminate layer 114. Accordingly, the contacts 112 may not protrude or extend beyond the second surface 120 of the package 100 from the second surface 120 of the package 100, but rather be internal to the package 100 unless otherwise exposed to the external environment through the channels 122. In some embodiments, only the plating 124 protrudes from the second surface 120 of the package 100.

Returning to the above description of fig. 2, the bottom surface 120 of the package 100 is shown in plan view in fig. 2. In some embodiments, the second laminate layer 114 defines a bottom surface 120 of the package 100, and is therefore visible in fig. 2. In addition, the package 100 includes a plating 124 (fig. 3) over the contacts 112 and a plurality of channels 122 (fig. 3) in the second laminate layer 114 and extending around the contacts 112. As shown in fig. 2, the channels 122 may extend around the entire perimeter of the plating 124. Thus, in some embodiments, the channel 122 may also extend around the entire perimeter of the contact 112. Further, the plating 124 is over the entire second surface 130 (fig. 3) of the contacts 112 and extends around the entire perimeter or outer surface of at least a portion of the sidewall 132 (fig. 3) of each contact 112 exposed through the channel 122.

Further, the contacts 112 (FIG. 3) and the plating 124 on the contacts 112 may be generally circular or cylindrical, as shown in FIG. 2, or they may have different selected shapes, as described herein. The package 100 may have an outermost edge or perimeter 134 that is square or rectangular in shape, but this is not required and the package 100 may have any selected shape. Although for simplicity fig. 2 shows nine contacts 112 (fig. 3) arranged in rows and columns equally spaced from each other, in practice the package 100 may include more or less than nine contacts 112 (fig. 3) in any selected particular arrangement.

Fig. 4 shows a cross-sectional view of package 100 coupled to a printed circuit board 136 (which may also be referred to herein as circuit board 136 or board 136). The board 136 includes a plurality of contacts 138 on a mounting surface 140 of the board 136. Package 100 is physically and electrically coupled to board 136 by solder 140. In particular, solder 140 bonds to the plating 124 on the contacts 112 and the contacts 138 on the board 136. Thus, there is an electrical path through the board 136 to the contacts 138 on the board 136, through the solder 140 to the plating 124, from the plating 124 to the contacts 112 of the package 100, through the redistribution layer 110 to the die 102. As shown in fig. 4, solder 140 extends into the channels 122 in the second laminate layer 114 of the package 100 and contacts the plating 124 on portions of each sidewall 132 of the contacts 112 exposed through the channels 122. Solder 140 may contact any portion of plating 124 on the portion of sidewall 132 of each contact 112 exposed by channel 122 due to variations or design factors in mounting package 100 to board 136. For example, in some embodiments, the solder 140 may contact the plating 124 over the entire exposed portion of the sidewall 132, over approximately half of the exposed portion of the sidewall 132, or over less than half of the exposed portion of the sidewall 132.

Further, fig. 4 shows that in some embodiments the channels 122 extend into the second laminate layer 114 to a depth that is greater than a majority of the height of the sidewalls 132 of the contacts 112. Thus, the plating 124 is over a majority of the total surface area of the contact 112 (i.e., over the second surface 130 of the contact 112 and greater than half the height of the sidewall 132 of the contact 112), and a minority of the surface area of the contact 112 is covered by the second laminate layer 114. As a result, the solder 140 can bond with a majority of the surface area of the contact 112 (or plating 124 over a majority of the surface area of the contact 112), which improves bond strength relative to known packages.

Fig. 5A-5L are cross-sectional views of steps in an embodiment of the manufacturing process of the semiconductor package 100 described above with reference to fig. 2-4. The process begins in fig. 5A with a wafer or substrate 103, which wafer or substrate 103 may be a selected semiconductor material, such as silicon in one non-limiting example. The wafer 103 includes a first or inactive surface 105 and a second or active surface 107 opposite the first surface 105. Then, in fig. 5B, a first laminate layer 108 is deposited or applied onto the second surface 107 of the wafer 103. A plurality of vias 109 are formed through the first laminate layer 108 to selectively expose portions of the second surface 107 of the wafer 103. The vias 109 extend through the entire first laminate layer 108 at selected locations and may be formed by drilling with a laser, etching, or cutting the first laminate layer 108 with any other selected technique.

In fig. 5D, a grinding operation is performed on the first surface 105 of the wafer 103 to reduce the thickness of the wafer 103. Then, tape 111 is applied to the first surface 105 of the wafer 103 to provide support for the wafer 103 during singulation. After the application of the adhesive tape 111, the first stage of the dicing process is performed. This creates an opening between adjacent die 102. Referring to fig. 5D, wafer 103 is singulated into individual die 102 by dicing, sawing or other singulation techniques down to tape 111. The tape 111 is removed after dicing in fig. 5D, and the die 102 is inverted and placed on the first carrier 113 as in fig. 5E. In particular, die 102 is located on first carrier 113 along with first laminate layer 108. A molding compound 116 is deposited over the die 102 to encapsulate the die 102. More specifically, the molding compound 116 encapsulates the first surface 104 of the die 102 and the first laminate layer 108. The molding compound 116 initially has a greater thickness over the first surface 104 of the die 102, but after the molding compound 116 cures, a grinding step is performed to reduce the thickness of the molding compound 116 to the thickness shown in fig. 5E. The first carrier 113 prevents the molding compound 116 from filling the via 119 and contacting the second or active surface 106 of the die 102.

In fig. 5F, the assembly at this stage is inverted and the molding compound 116 is placed on a second carrier 115, which may also be referred to as a transfer carrier 115. The assembly is flipped to the position shown in fig. 5F to expose the through hole 109 and enable the formation of the remaining components of the package 100, as described below. In fig. 5G, a pattern is applied and a redistribution layer 110 is plated on the die 102. As shown in fig. 5G, the redistribution layer 110 fills the plurality of vias 109 (fig. 5F) and is in direct contact with the second surface 106 of the die 102 through the vias 109 (fig. 5F). Then, in fig. 5H, a second pattern is applied and contacts 112 (which may also be referred to herein as mounting posts 112 or posts 112) are plated in selected locations on the redistribution layer 110. Then, as shown in fig. 5I, a second lamination layer 114 is deposited over the redistribution layer 110 and the contacts 112. In some embodiments, the second laminate layer 114 is deposited without patterning, or in other words, the second laminate layer 114 initially covers the contacts 112. In a subsequent grinding step, the thickness of the second laminate layer 114 is reduced to expose the outer surface of the contacts 112, as shown in fig. 5I. In particular, the second laminate layer 114 is lapped until the second surface 130 of the contact 112 is exposed. In one or more embodiments, the second laminate layer 114 may also be deposited with a pattern corresponding to the second surface 130 of the contact 112.

In fig. 5J, a channel 122 is formed around the contact 112. In some embodiments, the channels 122 are cut to a selected depth in the second laminate layer 114 using laser drilling. However, the channels 122 may also be formed by other alternative techniques, such as masking or patterning and plasma etching in one non-limiting example. While the channel 122 is generally illustrated as square or rectangular in shape with vertical sidewalls, it should be understood that in practice the channel 122 may have an uneven shape from laser drilling or an inclined shape with a rounded or rounded falling edge due to etching. Accordingly, the shape of the channel 122 in the drawings is for ease of identification only, and the present disclosure is not limited to the specifically illustrated shape.

In fig. 5K, plating 124 is applied to contacts 112 by any selected technique, such as electroless plating in one non-limiting example. The plating 124 covers the entire exposed surface of the contact 112 (i.e., the entire area of the contact that extends beyond the second laminate layer 114 and is exposed by the channel 122). Finally, in fig. 5L, the assembly is separated from the second carrier 115 (fig. 5K) and from other packages to complete the package 100. In other words, although the figures show only one package 100, the molding compound 116 and other features may be repeated to simultaneously form multiple packages 100 on the same carrier 113, 115. In fig. 5J, a grinding or sawing operation is performed to separate each individual package 100 from the array of packages 100. Each package 100 is then packaged for further shipment and may be mounted to a circuit board in a subsequent step prior to activation or use of the package 100, as described herein. Although not shown in fig. 5A-5K, it should be appreciated that the above-described process may include forming integrated circuits in or on the second surface 107 of the wafer 103 such that the second surface 106 of the die 102 likewise includes integrated circuits therein or thereon for performing the operational functions of the die 102 and the package 100 as a whole.

The above description relates to one or more embodiments of the manufacturing process of package 100. However, it should be appreciated that many aspects of the process or package 100 may be selected based on design factors. For example, in some embodiments, the contacts 112 are illustrated as being coplanar and aligned with the second laminate layer 114 such that the plating 124 extends beyond the second laminate layer 114 to form a raised surface on the package 100. In one or more embodiments, the plating or cutting depths described above may be selected such that the contacts 112 may be recessed with respect to the second laminate layer 114 or extend beyond the second laminate layer 114 such that the plating 124 is also recessed with respect to the second laminate layer 114, coplanar with the second laminate layer 114 and aligned with the second laminate layer 114, or extend beyond the second laminate layer 114. In further embodiments, one or more steps may be combined or omitted. The above variations are a few non-limiting examples of potential variations of the package 100 based on adjustments to the manufacturing process that are contemplated within the scope of the present disclosure.

Fig. 6 is a cross-sectional view of an embodiment of a semiconductor package 200 with partially exposed mounting posts. The package 200 includes a mounting post 202 having a first side 204 and a second side 206 opposite the first side 204. The outermost surface 208 of the post 202 interfaces with the first and second sides 204, 206, with the sides 204, 206 on opposite sides of the surface 208. The package 200 also includes a plurality of holes or apertures 210 in a laminate layer 212 of the package 200 to expose a portion of the stud 202.

In particular, the apertures 210 may be formed to a selected depth and width in the laminate layer 212 on only one side, such as on only the first side 204 or the second side 206 of each post 202. Thus, in some embodiments, the aperture 210 exposes only half of the stud 202. The other side or half of the post 202 is covered with a laminate layer 212. As a result, the package 200 includes the plating 214 on the outermost surface 208 and only one of the sides 204, 206 of the post 202. The package 200 in fig. 6 increases the available surface area for bonding with the solder 216 during mounting to the board 218 relative to known packages, but in some embodiments it turns out that the package 200 does not necessarily require the holes 210 to extend around the entire post 202.

Similarly, fig. 7 is an isometric view of an embodiment of a semiconductor package 300 having partially exposed mounting posts. In particular, package 300 includes a bottom surface 302, shown in fig. 7, at least partially defined by a laminate layer 304. The package 300 includes a plurality of posts 306 and a plurality of openings 308 exposing portions of the sidewalls 310 of the posts 306. Although fig. 7 shows four openings 308 equally spaced around the posts 306 separated by portions or bridges 312 of the laminate layer 304, the number and arrangement of openings 308 may be selected and the number and arrangement of openings 308 may be more or less than four openings with any spacing. Further, fig. 7 illustrates that in some embodiments the posts 306 may be square or rectangular rather than circular or cylindrical. Similar to fig. 6 and package 200, package 300 includes partially exposed posts 306 having an increased surface area for bonding with solder relative to known packages, without providing a channel around the entire post 306.

Fig. 8 is a cross-sectional view of an embodiment of a semiconductor package 400 having openings or channels extending to a redistribution layer. More specifically, the package 400 includes a redistribution layer 402 and a plurality of mounting posts 404 on the redistribution layer 402. The pillars 404 have a first surface 406 on the redistribution layer 402 and a second surface 408 opposite the first surface 406, with sidewalls 410 extending between the first and second surfaces 406, 408. The laminate layer 412 is on the redistribution layer 402, wherein the package 400 includes a plurality of openings 414 in the laminate layer 412 and extending around the pillars 404. In some embodiments, the openings 414 extend from the outer surface of the laminate layer 412 to the redistribution layer 402.

Plating 416 is disposed on mounting posts 404 and redistribution layer 402. In more detail, the plating 416 is on the second surface 408 and the entire sidewall 410 of the mounting stud 404, as well as on a portion of the redistribution layer 402 on either or both sides of the stud 404. The plating 416 extends to terminate at the laminate layer 412. Thus, in some embodiments, when the package 400 is mounted to the contacts 418 on the circuit board 420 with solder 422, the solder 422 extends along the entire sidewall 410 of the mounting posts 404 and contacts the redistribution layer 402 (or the contacts 404 and plating 416 on the redistribution layer 402).

Fig. 9 is a cross-sectional view of an embodiment of a semiconductor package 500 in which the sidewalls of the mounting posts are exposed to a depth less than a majority of the height of the sidewalls. Package 500 includes a redistribution layer 502 and a plurality of contacts 504 on the redistribution layer 502. The contacts 504 have a first surface 506 on the redistribution layer 502 and a second surface 508 opposite the first surface 506, with sidewalls 510 extending between the first and second surfaces 506, 508. The laminate layer 512 is on the redistribution layer 502, wherein the package 500 includes a plurality of gaps 514 in the laminate layer 512 extending around the contacts 504. In some embodiments, the gap 514 extends from the outer surface of the laminate layer 512 to a distance less than half the height of the side wall 510 of the contact 504.

Plating 516 is disposed over contacts 504 and terminates at redistribution layer 502. In more detail, the plating 516 is on the second surface 508 and a portion of the sidewalls 510 of the contacts 504 that is less than a majority of the height of the sidewalls 510 of the contacts 504, and on a portion of the redistribution layer 502 adjacent to the contacts 504. Thus, when the package 500 is mounted to the contacts 518 on the circuit board 520 with solder 522, the solder 522 extends along a majority of the side walls 510 that are smaller than the contacts 504 (or the plating 516 on the contacts 504).

As shown in the above examples in fig. 3, 8 and 9, the depth of the channel around the mounting post may be selected to correspond to any portion of the side wall. In other words, the channels may extend less than a majority of the height of the sidewall, half the height of the sidewall, a majority of the height of the sidewall, or the entirety of the sidewall or anywhere in between. The plating may also be located on the portion of the sidewall exposed by the channel. The contacts are inside the package, meaning that they do not protrude beyond the bottom of the package in order to reduce the package thickness while increasing the surface area for bonding therewith, as described herein. The package 200, 300, 400, 500 may be the same as the package 100 unless otherwise described above.

In view of the foregoing, the present disclosure is directed to a semiconductor package having exposed mounting posts to increase the bonding surface area in solder connections between the package and a printed circuit board. The increased bonding surface area creates a stronger physical and electrical connection between the package and the board, which overcomes the drawbacks of the known semiconductor packages.

One or more embodiments of a device according to the present disclosure may be summarized as including: a die having a first surface and a second surface opposite the first surface; a first laminate layer on a first surface of the die; a plurality of vias through the first laminate layer; a redistribution layer on the first laminate layer, the redistribution layer extending through the plurality of vias to the first surface of the die; a plurality of pillars on the redistribution layer, each pillar of the plurality of pillars comprising a first surface on the redistribution layer, a second surface opposite the first surface, and a sidewall between the first surface and the second surface; a second laminate layer on the redistribution layer and the first laminate layer; a plurality of channels in the second laminate layer surrounding the plurality of posts, the second surface of each post of the plurality of posts and at least a portion of the sidewall exposed to an external environment; and a molding compound on the second surface of the die and the first laminate layer.

In one embodiment, the device may further include a plating on the second surface and at least a portion of a sidewall of each of the plurality of pillars.

In one embodiment, the plurality of channels extend to the redistribution layer.

In one embodiment, the depth of the plurality of channels is less than a majority of the height of the sidewall of each of the plurality of posts.

In one embodiment, the depth of the plurality of channels is greater than a majority of the height of the sidewall of each of the plurality of posts.

In one embodiment, the plurality of channels are adjacent to a sidewall of each of the plurality of posts.

In one embodiment, the plurality of channels extend around the entire perimeter of the plurality of posts.

One or more embodiments of a package may be summarized as including: a die having a first surface and a second surface opposite the first surface; a redistribution layer in communication with the first surface of the die; a plurality of pillars on the redistribution layer, each pillar of the plurality of pillars comprising a first surface on the redistribution layer, a second surface opposite the first surface, and a sidewall between the first surface and the second surface; a lamination layer on the first surface of the die and on at least a portion of the redistribution layer; a hole in the laminate layer at an interface between at least one of the plurality of posts and the laminate layer, the second surface of the at least one of the plurality of posts and at least a portion of the sidewall exposed to an external environment through the hole; and a molding compound on the second surface of the die and the laminate layer.

In one embodiment, the package further comprises a plating on at least one of the plurality of posts.

In one embodiment, the plating is on the second surface and at least a portion of a sidewall of at least one of the plurality of studs.

In one embodiment, the depth of the hole is greater than a majority of the height of the sidewall of at least one of the plurality of posts.

In one embodiment, the aperture extends around less than the entire perimeter of the at least one plurality of posts.

In one embodiment, the laminate layer includes a first laminate layer between the first surface of the die and the redistribution layer, and a second laminate layer on at least a portion of the first laminate layer and the redistribution layer, the apertures being in the second laminate layer.

One or more embodiments of a package may be summarized as including: a die having a first surface and a second surface opposite the first surface; a plurality of stand-offs in communication with the first surface of the die, each of the plurality of stand-offs comprising a first surface, a second surface, and a sidewall between the first surface and the second surface; a laminate layer on the first surface of the die; a channel in the laminate layer through which the second surface of the at least one of the plurality of posts and at least a portion of the sidewall are exposed to an external environment; and a molding compound on the second surface of the die and the laminate layer.

In one embodiment, a package includes a laminate layer having a plurality of through holes, the package including a redistribution layer on the laminate layer, the redistribution layer extending to a first surface of a die through the plurality of through holes, a plurality of pillars on the redistribution layer.

In one embodiment, the laminate layer includes a first laminate layer between the first surface of the die and the redistribution layer and a second laminate layer on the first laminate layer.

In one embodiment, the package further comprises a plating on the second surface and at least a portion of the sidewall of at least one of the plurality of posts.

In one embodiment, the channel is one of a plurality of channels surrounding at least one of the plurality of posts, and the laminate layer extends between successive ones of the plurality of channels.

In one embodiment, the depth of the channel is greater than a majority of the height of the sidewall of at least one of the plurality of posts.

In one embodiment, the package further comprises a plating over a majority of the height of the second surface and the sidewall of at least one of the plurality of posts.

The semiconductor packages described herein generally include a semiconductor die having an active surface and a passive surface opposite the active surface. A first laminate layer or dielectric layer is on the active surface of the die, with a plurality of vias or openings formed through the first laminate layer to expose portions of the active surface of the die. A redistribution layer, typically copper or other similar metal, is located on the first laminate layer and extends through the vias to the active surface of the die. Electrical contacts or mounting posts are then formed on the redistribution layer. The mounting posts may also be copper or another metal to create an electrical path from the posts, through the redistribution layer, to the active surface of the die. Each stud includes a first surface on the redistribution layer, a second surface opposite the first surface, and a sidewall between the first and second surfaces.

A second laminate layer is deposited over the redistribution layer and the first laminate layer, wherein the second laminate layer initially surrounds the stud. The second laminate layer is ground down to expose the second surface of the stud. In addition, channels or holes are cut or etched in the second laminate layer around the pillars to expose selected amounts of the sidewalls of the pillars. In some examples, a plating is formed on the exposed portions of the pillars to prevent oxidation and corrosion. The molding compound encapsulates the non-active surface of the die and the first laminate layer to complete the package.

The package may then be physically and electrically coupled to electrical contacts on the printed surface board with solder through the exposed posts. In particular, solder connects to exposed mounting posts of the package and contacts on the board. Because the side walls of the mounting posts are exposed, there is more surface area on the posts for connection to solder. The increase in surface area results in a stronger bond between the post and the solder, which in turn results in a stronger bond between the package and the board, making cracking and separation less likely, thus overcoming the above-mentioned drawbacks of the known packages.

In the above description, certain specific details are set forth in order to provide a thorough understanding of various embodiments of the disclosure. However, it will be apparent to one skilled in the art that the present disclosure may be practiced without these specific details. In other instances, well-known structures associated with electronic components, packaging, and semiconductor manufacturing techniques have not been described in detail in order to avoid unnecessarily obscuring descriptions of the embodiments of the disclosure.

While various embodiments are shown and described with respect to silicon die, it will be readily understood that embodiments of the disclosure are not limited thereto. In various embodiments, the structures, devices, methods, etc. described herein may be implemented in or otherwise used with any suitable type or form of semiconductor die and may be fabricated using any suitable semiconductor die and packaging technology.

Certain words and phrases used in the specification are as follows. As used throughout this document (including the claims), the singular forms "a", "an" and "the" include plural referents unless the content clearly dictates otherwise. Any of the features and elements described herein may be singular, e.g., a die may refer to one die. The terms "include" and "comprise," as well as derivatives thereof, are intended to be inclusive and mean inclusion without limitation. The phrases "associated with" and derivatives thereof may mean including, being included within, interconnected with, being contained within, being connected to, or being coupled with, being communicable with, being co-operative with, being interleaved with, being in juxtaposition with, being bound to, or being bound to. Additional definitions for certain words and phrases are provided throughout this specification.

The use of ordinal numbers such as first, second, third, etc., does not necessarily imply a sequential sense of ordering, but rather may merely distinguish between multiple instances of an action or similar structure or material.

Throughout the specification, claims and drawings, the following terms take the meanings explicitly associated herein, unless the context clearly dictates otherwise. The term "herein" refers to the specification, claims and drawings associated with the present application. The phrases "in one embodiment," "in another embodiment," "in various embodiments," "in some embodiments," "in other embodiments," and other derivatives thereof, refer to one or more features, structures, functions, limitations, or characteristics of the present disclosure, and are not limited to the same or different embodiments unless the context clearly dictates otherwise. As used herein, the term "or" is an inclusive "or" operator and is equivalent to the phrase "a or B, or both" a or B or C, or any combination thereof, and the list with additional elements is similarly treated. The term "based on" is not exclusive and allows for being based on additional features, functions, aspects, or limitations that are not described, unless the context clearly indicates otherwise. Furthermore, throughout the specification, the meaning of "a," "an," and "the" include both singular and plural referents.

Where a range of values is provided, it is understood that each intervening value, to the tenth of the unit of the lower limit unless the context clearly dictates otherwise, between the upper and lower limit of that range, and any other stated or intervening value in that stated range, is encompassed within the disclosure. The upper and lower limits of these smaller ranges may independently be included in the smaller ranges, and are also encompassed within the disclosure, subject to any specifically excluded limit in the stated range. Where the stated range includes one or both of the limits, ranges excluding either or both of those included limits are also included in the disclosure.

In general, unless otherwise indicated, the materials used to make the present disclosure and/or components thereof may be selected from suitable materials, such as metals, metal alloys (high strength alloys, high hardness alloys), composite materials, ceramics, intermetallic compounds, plastics, 3D printable materials, polymers, semiconductor materials, plastic compounds, and the like.

The foregoing description, for purposes of explanation, used specific nomenclature and formulas to provide a thorough understanding of the disclosed embodiments. It will be apparent to one skilled in the art that the present disclosure may be practiced without the specific details. The embodiments were chosen and described in order to best explain the principles of the disclosed embodiments and their practical applications, thereby enabling others skilled in the art to utilize the disclosed embodiments and various embodiments with various modifications as are suited to the particular use contemplated. It is therefore intended to be exhaustive or to limit the disclosure to the precise form disclosed, and those skilled in the art will recognize that many modifications and variations are possible in light of the above teaching.

The terms "top," "bottom," "upper," "lower," "left," "right," and other similar derivatives are used merely for discussion purposes based on the orientation of the components in the figures of the present disclosure. These terms do not limit the possible orientations explicitly disclosed in the present disclosure, implicitly disclosed, or inherently disclosed, and any aspect of the embodiments of the present disclosure may be arranged in any orientation unless the context clearly indicates otherwise.

As used herein, the term "substantially" is to be construed as including the ordinary range of errors or manufacturing tolerances due to minor differences and variations in the manufacture of semiconductor packages. Relative terms such as "about," "substantially" and other derivatives thereof, when used in conjunction with a value, quantity, or dimension, generally refer to the value, quantity, or dimension as being plus or minus 5% of the value, quantity, or dimension unless the context clearly dictates otherwise. It should also be understood that any particular size of components or features provided herein is for illustrative purposes only with reference to the various embodiments described herein, and thus, it is expressly contemplated in this disclosure to include more or less sizes than stated, unless the context clearly dictates otherwise.

These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Thus, the breadth and scope of a disclosed embodiment should not be limited by any of the above-described embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims

1. An electronic device, comprising:

a die having a first surface and a second surface opposite the first surface;

a first laminate layer on a first surface of the die;

a plurality of openings through the first laminate layer;

a redistribution layer on the first laminate layer, the redistribution layer extending through the plurality of openings to the first surface of the die;

a plurality of pillars on the redistribution layer, each pillar of the plurality of pillars including a first surface on the redistribution layer, a second surface of the pillar opposite the first surface of the pillar, and a sidewall between the first surface of the pillar and the second surface of the pillar;

A second laminate layer on the redistribution layer and the first laminate layer;

a plurality of channels in the second laminate layer surrounding the plurality of posts, the second surface of each post of the plurality of posts and at least a portion of the sidewall exposed to an external environment through the plurality of channels.

2. The electronic device of claim 1, wherein the electronic device further comprises:

a molding compound on the second surface of the die and the first laminate layer;

plating on the second surface of each of the plurality of posts and the at least a portion of the sidewall.

3. The electronic device of claim 1, wherein the plurality of channels extend to the redistribution layer.

4. The electronic device of claim 1, wherein the plurality of channels have a depth that is less than a majority of a height of the sidewall of each of the plurality of pillars.

5. The electronic device of claim 1, wherein the plurality of channels have a depth greater than a height of the sidewall of each of the plurality of posts.

6. The electronic device of claim 1, wherein the second laminate layer comprises an outer surface, the second surface of each of the plurality of posts being aligned with the outer surface of the second laminate layer.

7. The electronic device of claim 1, wherein the plurality of channels extend around an entire perimeter of the plurality of posts.

8. A package, comprising:

a die having a first surface and a second surface opposite the first surface;

a redistribution layer on the first surface of the die;

a plurality of conductive extensions on the redistribution layer, each conductive extension of the plurality of conductive extensions including a first surface on the redistribution layer, a second surface of the conductive extension opposite the first surface of the conductive extension, and a sidewall between the first surface of the conductive extension and the second surface of the conductive extension;

a lamination layer on the first surface of the die and on at least a portion of the redistribution layer;

and a hole in the laminate layer at an interface between at least one of the plurality of conductive extensions and the laminate layer, second surface.

9. The package of claim 8, further comprising:

and a plating layer on at least one of the plurality of conductive extensions.

10. The package of claim 9, wherein the plating is on a second surface of the at least one of the plurality of conductive extensions and at least a portion of the sidewall.

11. The package of claim 9, wherein the hole has a depth greater than a height of the sidewall of the at least one of the plurality of conductive extensions.

12. The package of claim 9, wherein the aperture extends around less than an entire perimeter of the at least one plurality of conductive extensions.

13. The package of claim 9, wherein the laminate layer comprises a first laminate layer between the first surface of the die and the redistribution layer, and a second laminate layer on the first laminate layer and the at least a portion of the redistribution layer, the aperture in the second laminate layer.

14. A package, comprising:

a die having a first surface and a second surface opposite the first surface;

a plurality of conductive extensions on the first surface of the die, each conductive extension of the plurality of conductive extensions comprising a first surface, a second surface, and a sidewall between the first surface of the conductive extension and the second surface of the conductive extension;

A lamination layer on the first surface of the die; and

a channel in the laminate layer is located between the sidewall of the conductive extension and the inner sidewall of the laminate layer.

15. The package of claim 14, wherein the laminate layer comprises a plurality of openings, the package further comprising:

a redistribution layer on the laminate layer and extending through the plurality of openings to the first surface of the die, the plurality of conductive extensions being on the redistribution layer.

16. The package of claim 15, wherein the lamination layer comprises a first lamination layer and a second lamination layer, the first lamination layer being between the first surface of the die and the redistribution layer, and the second lamination layer being on the first lamination layer.

17. The package of claim 14, further comprising:

plating on a second surface of at least one of the conductive extensions and at least a portion of the sidewall.

18. The package of claim 14, wherein the channel is one of a plurality of channels surrounding at least one of the conductive extensions, the laminate layer extending between successive ones of the plurality of channels.

19. The package of claim 14, wherein the channel has a depth that is greater than a majority of a height of the sidewall of at least one of the plurality of conductive extensions.

20. The package of claim 19, further comprising:

plating over a majority of a height of the second surface of the at least one of the plurality of conductive extensions and the sidewall.