CN219893305U - Field effect power switch drive circuit - Google Patents

Abstract

Provided is a field effect power switch driving circuit including a driving control unit, a high level driving switch, a low level driving switch, and a clamp unit, wherein: the first and second output terminals of the drive control unit are respectively connected to the gate of the high-level drive switch and the gate of the low-level drive switch; the drain electrode of the high-level driving switch is connected to an internal power supply of the circuit, the source electrode of the high-level driving switch is connected to the drain electrode of the low-level driving switch and is used for being connected to the grid electrode of the field effect power switch; the source electrode of the low-level driving switch is grounded; and the clamping unit is used for controlling the voltage difference between the grid electrode of the high-level driving switch and the source electrode of the field effect power switch to be a fixed value.

Description

Field effect power switch drive circuit

Technical field

The utility model relates to the field of circuits, and in particular to a field effect power switch driving circuit.

Background technique

Field effect power switches, represented by gallium nitride field effect transistors and metal oxide semiconductor (MOS) field effect transistors, are widely used in switching power supplies, light emitting diode (LED) drives, motor drives, audio power amplifiers and other systems. Among them, field effect power switches The maximum saturation current that an effect power switch can withstand is closely related to the voltage difference between its gate and source (hereinafter referred to as "gate-source voltage").

Utility model content

The field effect power switch drive circuit according to the embodiment of the present invention includes a drive control unit, a high-level drive switch, a low-level drive switch, and a clamping unit, wherein: the first and second output terminals of the drive control unit are respectively Connected to the gate of the high-level drive switch and the gate of the low-level drive switch; the drain of the high-level drive switch is connected to the internal power supply of the circuit, and the source is connected to the drain of the low-level drive switch and is used to connect to the gate of the field effect power switch; the source of the low-level drive switch is grounded; and the clamping unit is used to control the voltage difference between the gate of the high-level drive switch and the source of the field-effect power switch at a fixed value.

A field effect power switch drive circuit according to another embodiment of the present invention includes a drive control unit, a high-level drive switch, a low-level drive switch, and a clamping unit, wherein: the first and second outputs of the drive control unit The terminals are connected to the gate of the high-level drive switch and the gate of the low-level drive switch respectively; the source of the high-level drive switch is connected to the internal power supply of the circuit, and the drain is connected to the drain of the low-level drive switch and used is connected to the gate of the field effect power switch; the source of the low-level drive switch is grounded; and the clamping unit is used to control the voltage difference between the gate and the source of the field effect power switch at a fixed value.

Description of the drawings

The present utility model can be better understood from the following description of specific embodiments of the present utility model in conjunction with the accompanying drawings, in which:

Figure 1 is a schematic diagram of a field effect power switch driving circuit according to an embodiment of the present invention.

FIG. 2 shows waveform diagrams of multiple signals related to the field effect power switch driving circuit shown in FIG. 1 .

FIG. 3 shows a schematic diagram of a field effect power switch driving circuit according to another embodiment of the present invention.

FIG. 4 shows waveform diagrams of multiple signals related to the field effect power switch driving circuit shown in FIG. 3 .

Detailed ways

Features and exemplary embodiments of various aspects of the present invention will be described in detail below. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, it will be apparent to one skilled in the art that the present invention may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present invention by illustrating examples of the present invention. This invention is in no way limited to any specific configurations set forth below, but covers any modifications, substitutions and improvements of elements and components without departing from the spirit of the invention. In the drawings and the following description, well-known structures and techniques are not shown to avoid unnecessarily obscuring the present invention. In addition, it should be noted that the term "A and B are connected" used here may mean "A and B are directly connected" or "A and B are indirectly connected via one or more other components."

Generally, within the allowed operating range, the greater the gate-source voltage of a field-effect power switch, the greater the maximum saturation current it can withstand. However, in practical applications, the source voltage of the field effect power switch often increases as the current flowing through it increases, which causes the gate-source voltage of the field effect power switch to decrease and the maximum saturation current it can withstand also decreases. correspondingly smaller. Due to the limitation of the gate-source breakdown voltage of field-effect power switches (especially the gate-source voltage of gallium nitride field-effect transistors is generally required to be less than 7V), in practical applications it is often necessary to select a field that can withstand a larger maximum saturation current. Effect power switches, but such field effect power switches are usually more expensive.

In view of the above problems, a field effect power switch driving circuit according to an embodiment of the present invention is proposed, which can control the gate voltage of the field effect power switch to follow the change of the source voltage, so that the gate-source voltage of the field effect power switch remains unchanged. As a result, the maximum saturation current that the field-effect power switch can withstand does not change with changes in its source voltage.

Figure 1 is a schematic diagram of a field effect power switch driving circuit according to an embodiment of the present invention. As shown in FIG. 1 , the field effect power switch driving circuit 100 includes a driving control unit U1, a high-level driving switch M1, a low-level driving switch M2, and a clamping unit U2, where: the first and third terminals of the driving control unit U1 The two output terminals are respectively connected to the gate of the high-level drive switch M1 and the gate of the low-level drive switch M2; the drain of the high-level drive switch M1 is connected to the internal power supply VDD of the circuit, and the source is connected to the low-level drive The drain of switch M2 is used to connect to the gate of field effect power switch M0; the source of low level driving switch M2 is grounded; the clamping unit U2 is used to connect the gate of high level driving switch M1 to the field effect power switch The voltage difference between the sources of M0 is controlled at a first fixed value.

As shown in Figure 1, in some embodiments, the first terminal of the clamping unit U2 is connected to the gate of the high-level drive switch M1, the second terminal is used to be connected to the source of the field effect power switch M0, and is used to connect via Sense resistor R0 is connected to ground.

As shown in Figure 1, in some embodiments, the high-level driving switch M1 and the low-level driving switch M2 can be implemented as N-type MOS field effect transistors, and the clamping unit U2 can be implemented as a Zener diode.

FIG. 2 shows waveform diagrams of multiple signals related to the field effect power switch driving circuit shown in FIG. 1 , wherein: PWM represents the external signal received by the field effect power switch driving circuit 100 for controlling high-level driving. Pulse width modulation (PWM) control signal for the turn-on and turn-off of switch M1 and low-level drive switch M2. Drv_H represents the gate drive signal used to control the turn-on and turn-off of high-level drive switch M1. Gate represents The gate drive signal used to control the on and off of the field effect power switch M0, CS represents the source voltage detection signal of the field effect power switch M0, and Vgs represents the gate-source voltage of the field effect power switch M0.

Combining Figures 1 and 2, it can be seen that the specific working process of the field effect power switch drive circuit 100 is as follows: the drive control unit U1 receives the PWM control signal from the outside and generates a gate for high-level driving switch M1 based on the PWM control signal. The drive signal Drv_H and the gate drive signal Drv_L for low-level drive switch M2; when the gate drive signal Drv_H is high level (that is, the high-level drive switch M1 is in the on state) and the gate drive signal Drv_L is When the gate drive signal Gate is low level (that is, the low-level drive switch M2 is in the off state), the gate drive signal Gate is at the high level (that is, the field effect power switch M0 is in the on state), and the gate of the field effect power switch M0 Voltage Vgate=Vdrv_H-Vth (Vdrv_H represents the gate voltage of the high-level drive switch M1, Vth represents the gate-source voltage when the high-level drive switch M1 is in the on state and is a fixed value); the clamping unit U2 will be high The voltage difference between the gate of the level drive switch M1 and the source of the field effect power switch M0 is controlled at the clamp voltage Vclamp; when the field effect power switch M0 is in the on state, due to the source of the field effect power switch M0 The drain and the inductor are connected in series, so the current flowing through the field effect power switch M0 gradually increases, and the source voltage of the field effect power switch M0 (that is, the voltage generated by the current flowing through the field effect power switch M0 on the detection resistor R0) also Gradually increases; under the action of the clamping unit U2, the gate voltage of the high-level drive switch M1 and the gate voltage of the field effect power switch M0 change with the source voltage of the field effect power switch M0, making the field effect power switch The gate-source voltage Vgs of M0 is maintained at (Vclamp-Vth).

FIG. 3 shows a schematic diagram of a field effect power switch driving circuit according to another embodiment of the present invention. As shown in FIG. 3 , the field effect power switch driving circuit 300 includes a driving control unit U1, a high-level driving switch M1, a low-level driving switch M2, and a clamping unit U2, where: the first and third terminals of the driving control unit U1 The two output terminals are respectively connected to the gate of the high-level drive switch M1 and the gate of the low-level drive switch M2; the drain of the high-level drive switch M1 is connected to the internal power supply PVDD of the circuit, and the source is connected to the low-level drive The drain of the switch M2 is used to connect to the gate of the field effect power switch M0; the source of the low-level drive switch M2 is grounded; the clamping unit U2 is used to connect the gate and the source of the field effect power switch M0. The voltage difference is controlled at a second fixed value.

As shown in Figure 3, in some embodiments, the first terminal of the clamping unit U2 is connected to the drain of the high-level driving switch M1 and the drain of the low-level driving switch M2, and the second terminal is used to connect to the field effect The source of power switch M0 and is used to connect to ground via sense resistor R0.

As shown in Figure 3, in some embodiments, the high-level drive switch M1 can be implemented as a P-type MOS field effect transistor, the low-level drive switch M2 can be implemented as an N-type MOS field effect transistor, and the clamping unit U2 can be implemented is a Zener diode.

FIG. 4 shows waveform diagrams of multiple signals related to the field effect power switch driving circuit shown in FIG. 3 , wherein: PWM represents the external signal received by the field effect power switch driving circuit 300 for controlling high-level driving. The PWM control signal for the turn-on and turn-off of switch M1 and low-level drive switch M2. Gate represents the gate drive signal used to control the turn-on and turn-off of field effect power switch M0. CS represents the gate drive signal for controlling the turn-on and turn-off of field effect power switch M0. Source voltage detection signal, Vgs represents the gate-source voltage of the field effect power switch M0.

Combining Figures 3 and 4, it can be seen that the specific working process of the field effect power switch drive circuit 300 is as follows: the drive control unit U1 receives the PWM control signal from the outside and generates a gate for high-level driving switch M1 based on the PWM control signal. The drive signal Drv_H and the gate drive signal Drv_L for the low-level drive switch M2; when the gate drive signal Drv_H is low level (that is, the high-level drive switch M1 is in the on state) and the gate drive signal Drv_L is When the gate drive signal Gate is low level (that is, the low-level drive switch M2 is in the off state), the gate drive signal Gate is at the high level (that is, the field effect power switch M0 is in the on state), and the gate of the field effect power switch M0 Voltage Vgate=Vcs+Vclamp (Vcs represents the source voltage of the field effect power switch M0, Vclamp represents the clamping voltage of the clamping unit U2); the clamping unit U2 controls the gate-source voltage of the field effect power switch M0 at the clamp Voltage Vclamp; when the field effect power switch M0 is in the on state, since the source and drain of the field effect power switch M0 are connected in series with the inductor element, the current flowing through the field effect power switch M0 gradually increases, and the source of the field effect power switch M0 The pole voltage (that is, the voltage generated on the detection resistor R0 by the current flowing through the field effect power switch M0) also gradually increases; under the action of the clamping unit U2, the gate voltage of the field effect power switch M0 changes with the source voltage. , so that the gate-source voltage of the field effect power switch M0 is maintained at Vclamp.

The utility model can be implemented in other specific forms without departing from its spirit and essential characteristics. The present embodiments are to be considered in all respects as illustrative rather than restrictive, and the scope of the present invention is defined by the appended claims rather than the foregoing description and is within the meaning and range of equivalents of the claims. All changes are included in the scope of the present invention.

Claims (10)

1. The field effect power switch driving circuit is characterized by comprising a driving control unit, a high-level driving switch, a low-level driving switch and a clamping unit, wherein:

the first and second output terminals of the drive control unit are connected to the gate of the high-level drive switch and the gate of the low-level drive switch, respectively;

the drain electrode of the high-level driving switch is connected to an internal power supply of the circuit, the source electrode of the high-level driving switch is connected to the drain electrode of the low-level driving switch and is used for being connected to the grid electrode of the field effect power switch;

the source electrode of the low-level driving switch is grounded; and is also provided with

The clamping unit is used for controlling the voltage difference between the grid electrode of the high-level driving switch and the source electrode of the field effect power switch to be a fixed value.

2. The field effect power switch driving circuit according to claim 1, wherein a first terminal of the clamping unit is connected to a gate of the high level driving switch, a second terminal is for connection to a source of the field effect power switch and for grounding via a sense resistor.

3. The field effect power switch drive circuit of claim 2 wherein the high level drive switch and the low level drive switch are implemented as N-type metal oxide semiconductor field effect transistors.

4. The field effect power switch drive circuit of claim 2, wherein the clamping unit is implemented as a zener diode.

5. The field effect power switch drive circuit of claim 2 wherein the field effect power switch is in an on state when the high level drive switch is in an on state and the low level drive switch is in an off state.

6. The field effect power switch driving circuit is characterized by comprising a driving control unit, a high-level driving switch, a low-level driving switch and a clamping unit, wherein:

the first and second output terminals of the drive control unit are connected to the gate of the high-level drive switch and the gate of the low-level drive switch, respectively;

the source electrode of the high-level driving switch is connected to an internal power supply of the circuit, the drain electrode of the high-level driving switch is connected to the drain electrode of the low-level driving switch and is used for being connected to the grid electrode of the field effect power switch;

the source electrode of the low-level driving switch is grounded; and is also provided with

The clamping unit is used for controlling the voltage difference between the grid electrode and the source electrode of the field effect power switch to be a fixed value.

7. The field effect power switch driving circuit of claim 6, wherein a first terminal of the clamping unit is connected to a drain of the high level driving switch, a second terminal is for connection to a source of the field effect power switch and for grounding via a sense resistor.

8. The field effect power switch drive circuit of claim 7, wherein the high level drive switch is implemented as a pmos field effect transistor and the low level drive switch is implemented as an nmos field effect transistor.

9. The field effect power switch drive circuit of claim 7, wherein the clamping unit is implemented as a zener diode.

10. The field effect power switch drive circuit of claim 7 wherein the field effect power switch is in an on state when the high level drive switch is in an on state and the low level drive switch is in an off state.