CN212785304U - Startup and shutdown circuit and POS machine - Google Patents
Startup and shutdown circuit and POS machine Download PDFInfo
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- CN212785304U CN212785304U CN202021001251.9U CN202021001251U CN212785304U CN 212785304 U CN212785304 U CN 212785304U CN 202021001251 U CN202021001251 U CN 202021001251U CN 212785304 U CN212785304 U CN 212785304U
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Abstract
本实用新型属于电源管理领域，公开了一种开关机电路及POS机，通过第一开关电路，输入端连接电源，输出端连接负载；按键组件接通低于预设时长时，控制第一开关电路的控制端置于第一电平状态以驱动所述第一开关电路导通；维持电路在接收到上电信号时，根据上电信号控制第一开关电路的控制端维持在第一电平状态；第二开关电路在按键组件接通高于预设时长时，输出电压信号使第一开关电路的控制端置于第二电平状态以驱动第一开关电路关断；由于通过简单的电路结构实现了短按开机和长按关机功能，故不仅可以降低成本，还可以降低系统的电路复杂程度。
The utility model belongs to the field of power management, and discloses a switch circuit and a POS machine. Through a first switch circuit, an input end is connected to a power source, and an output end is connected to a load; when the key component is turned on for less than a preset time, the first switch is controlled The control terminal of the circuit is placed in the first level state to drive the first switch circuit to conduct; when the maintenance circuit receives the power-on signal, the control terminal of the first switch circuit is controlled to maintain the first level according to the power-on signal state; the second switch circuit outputs a voltage signal to make the control terminal of the first switch circuit set to the second level state when the button assembly is turned on for longer than a preset time period to drive the first switch circuit to turn off; due to the simple circuit The structure realizes the functions of short-pressing to turn on and long-pressing to turn off, so it can not only reduce the cost, but also reduce the circuit complexity of the system.
Description
Technical Field
The utility model belongs to the power management field especially relates to a switching on and shutting down circuit and POS machine.
Background
In a traditional on-off circuit, if short-press startup and long-press shutdown functions need to be realized, a power management chip is needed, the power management chip is used as a power management integrated unit matched with a specific main chip of a consumer electronic product and can provide all power supplies with different voltages required by the main chip, however, the number of peripheral circuits required by the power management chip is large, so that the on-off circuit is complex, the cost is high, and the on-off circuit is generally suitable for a complex system. For some electronic products with simpler systems, the problems of complex implementation scheme and high cost are faced.
SUMMERY OF THE UTILITY MODEL
The utility model provides a switching on and shutting down circuit and POS machine aims at solving thereby the needs that traditional switching on and shutting down circuit exists use the power management chip to lead to the complicated and costly problem of ground circuit.
The utility model discloses a realize like this, a switching on and shutting down circuit, include:
the input end of the first switch circuit is connected with a power supply, and the output end of the first switch circuit is connected with a load;
the key assembly is connected with the control end of the first switch circuit and is configured to control the control end of the first switch circuit to be in a first level state to drive the first switch circuit to be conducted when the key assembly is switched on and is lower than a preset time length;
the maintaining circuit is connected with the control end of the first switch circuit and is configured to control the control end of the first switch circuit to be maintained in a first level state according to a power-on signal when the power-on signal is received;
and the input end of the second switch circuit is connected with the power supply, the output end of the second switch circuit is connected with the control end of the first switch circuit, and the key assembly is also configured to control the second switch circuit to output a voltage signal to enable the control end of the first switch circuit to be in a second level state to drive the first switch circuit to be switched off when the key assembly is switched on for a time longer than a preset time.
In one embodiment, the second switching circuit includes:
the input end of the first switch component is connected with the power supply, and when the key component is also configured to be switched on for a time length higher than a preset time length, the first switch component outputs a control voltage;
and the input end of the second switch component is connected with the first switch component, the output end of the second switch component is connected with the control end of the first switch circuit, and the control end of the first switch circuit is placed in a second level state to drive the first switch circuit to be switched off based on the control voltage output voltage signal.
In one embodiment, the first switch assembly comprises a first field effect transistor, a first capacitor, a first resistor and a second resistor;
the source electrode of the first field effect transistor, the first end of the first capacitor and the first end of the first resistor jointly form the input voltage input end of the first switch component, the grid electrode of the first field effect transistor is connected with the first end of the second resistor, the second end of the first capacitor and the second end of the first resistor, the second end of the second resistor is the key signal input end of the first switch component, and the drain electrode of the first field effect transistor is the control voltage output end of the first switch component.
In one embodiment, the second switch assembly comprises a second field effect transistor, a third field effect transistor, a first diode, a second capacitor, a third resistor, a fourth resistor and a fifth resistor;
the grid electrode of the second field effect transistor is connected with the anode of the first diode, the first end of the fifth resistor and the first end of the second capacitor, the first end of the third resistor is connected with the cathode of the first diode, the second end of the fifth resistor and the first end of the third resistor, the second end of the third resistor is a control voltage input end of the second switch component, the drain electrode of the second field effect transistor is connected with the grid electrode of the third field effect transistor, the source electrode of the third field effect transistor is an input voltage input end of the second switch component, the drain electrode of the third field effect transistor is a voltage signal output end of the second switch component, and the source electrode of the second field effect transistor, the second end of the second capacitor and the second end of the fourth resistor are connected to a power ground in common.
In one embodiment, the second switch assembly comprises a voltage regulator tube and a sixth resistor;
the first end of the sixth resistor and the source electrode of the third field effect transistor jointly form an input voltage input end of the second switch component, the second end of the sixth resistor is connected with the negative electrode of the voltage regulator tube, the drain electrode of the second field effect transistor and the grid electrode of the third field effect transistor, and the negative electrode and the positive electrode of the voltage regulator tube are connected with a power supply ground.
In one embodiment, the first switch circuit comprises a fourth field effect transistor and a seventh resistor;
the source electrode of the fourth field effect transistor and the first end of the seventh resistor jointly form an input voltage input end of the first switch circuit, the drain electrode of the fourth field effect transistor is an input voltage output end of the first switch circuit, and the grid electrode of the fourth field effect transistor and the second end of the seventh resistor jointly form a voltage signal input end of the first switch circuit.
In one embodiment, the sustain circuit includes a first transistor, a second diode, an eighth resistor, and a ninth resistor;
the negative electrode of the second diode is a key signal input end of the maintaining circuit, the positive electrode of the second diode is connected with the collector electrode of the first triode and the first end of the eighth resistor, the second end of the eighth resistor is a switch control voltage output end of the maintaining circuit, the base electrode of the first triode is connected with the first end of the ninth resistor, the second end of the ninth resistor is an electrifying signal input end of the maintaining circuit, and the emitting electrode of the first triode is connected with a power ground.
In one embodiment, the key assembly includes a key.
The embodiment of the utility model provides a still provide a POS machine, the POS machine includes as foretell switch circuit.
The embodiment of the utility model realizes the short-press startup and long-press shutdown functions through a simple circuit structure, thereby not only obviously reducing the cost, but also obviously reducing the circuit complexity of the system; furthermore, the embodiment of the utility model provides a can also be by oneself according to specific demand set time threshold value, it is more nimble for chip class scheme, can couple some OverVoltage Protection (OVP) functions moreover.
Drawings
In order to more clearly illustrate the technical utility model in the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a block diagram of a switching circuit according to an embodiment of the present invention;
fig. 2 is a block diagram of a second switching circuit of the switching circuit according to an embodiment of the present invention;
fig. 3 is a circuit diagram of an example of a switching circuit according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.
Fig. 1 shows a module structure of a switching circuit provided by an embodiment of the present invention, and for convenience of description, only the parts related to the embodiment of the present invention are shown, and detailed descriptions are as follows:
the switch circuit includes a first switch circuit 11, a key assembly 12, a sustain circuit 13, and a second switch circuit 14.
The input end of the first switch circuit 11 is connected with a power supply, and the output end is connected with a load;
the key assembly 12 is connected with the control end of the first switch circuit 11, and the key assembly 12 is configured to control the control end of the first switch circuit 11 to be in a first level state to drive the first switch circuit 11 to be conducted when the key assembly is switched on for a time shorter than a preset time;
a maintaining circuit 13, connected to the control terminal of the first switch circuit 11, and configured to control the control terminal of the first switch circuit 11 to maintain a first level state according to the power-on signal when receiving the power-on signal;
the input end of the second switch circuit 14 is connected to the power supply, the output end of the second switch circuit is connected to the control end of the first switch circuit 11, and the key assembly 12 is further configured to control the second switch circuit 14 to output a voltage signal to enable the control end of the first switch circuit 11 to be in a second level state to drive the first switch circuit 11 to turn off when the key assembly is turned on for a time longer than a preset time.
As shown in fig. 2, the second switch circuit 14 includes a first switch component 141 and a second switch component 142.
A first switch component 141, the input end of which is connected with the power supply, and when the key component 12 is also configured to be switched on for a time longer than a preset time, the control voltage is output;
and the input end of the second switch component 142 is connected to the first switch component 11, the output end of the second switch component is connected to the control end of the first switch circuit 11, and the control end of the first switch circuit 11 is set to a second level state based on the control voltage output voltage signal to drive the first switch circuit 11 to be turned off.
Fig. 3 shows an exemplary circuit structure of a switching circuit provided in an embodiment of the present invention, and for convenience of description, only the portions related to the embodiment of the present invention are shown, and detailed descriptions are as follows:
the first switch element 141 includes a first fet Q1, a first capacitor C1, a first resistor R1, and a second resistor R2.
The source of the first fet Q1, the first end of the first capacitor C1, and the first end of the first resistor R1 together form an input voltage input terminal of the first switch element 141, the gate of the first fet Q1 is connected to the first end of the second resistor R2, the second end of the first capacitor C1, and the second end of the first resistor R1, the second end of the second resistor R2 is a key signal input terminal of the first switch element 141, and the drain of the first fet Q1 is a control voltage output terminal of the first switch element 141.
The second switch component 142 includes a second fet Q2, a third fet Q3, a first diode D1, a second capacitor C2, a third resistor R3, a fourth resistor R4, and a fifth resistor R5.
A gate of the second fet Q2 is connected to an anode of the first diode D1, a first end of the fifth resistor R5, and a first end of the second capacitor C2, a first end of the third resistor R3 is connected to a cathode of the first diode D1, a second end of the fifth resistor R5, and a first end of the third resistor R4, a second end of the third resistor R3 is a control voltage input terminal of the second switching element 142, a drain of the second fet Q2 is connected to a gate of the third fet Q3, a source of the third fet Q3 is an input voltage input terminal of the second switching element 142, a drain of the third fet Q3 is a voltage signal output terminal of the second switching element 142, a source of the second fet Q2, a second end of the second capacitor C2, and a second end of the fourth resistor R4 are commonly connected to a power ground.
The second switch assembly 142 includes a regulator tube Z1 and a sixth resistor R6.
The first end of the sixth resistor R6 and the source of the third field-effect transistor Q3 jointly form an input voltage input end of the second switch component 142, the second end of the sixth resistor R6 is connected with the negative electrode of the regulator tube Z1, the drain of the second field-effect transistor Q2 and the gate of the third field-effect transistor Q3, and the negative and positive electrodes of the regulator tube Z1 are connected with the power ground.
The first switch circuit 11 includes a fourth field effect transistor Q4 and a seventh resistor R7.
The source of the fourth fet Q4 and the first end of the seventh resistor R7 together form an input voltage input terminal of the first switch circuit 11, the drain of the fourth fet Q4 is an input voltage output terminal of the first switch circuit 11, and the gate of the fourth fet Q4 and the second end of the seventh resistor R7 together form a voltage signal input terminal of the first switch circuit 11.
The sustain circuit 13 includes a first transistor Q5, a second diode D2, an eighth resistor R8, and a ninth resistor R9.
The cathode of the second diode D2 is a key signal input terminal of the holding circuit 13, the anode of the second diode D2 is connected to the collector of the first transistor Q5 and the first end of the eighth resistor R8, the second end of the eighth resistor R8 is a voltage signal output terminal of the holding circuit 13, the base of the first transistor Q5 is connected to the first end of the ninth resistor R9, the second end of the ninth resistor R9 is a power-on signal input terminal of the holding circuit 13, and the emitter of the first transistor Q5 is connected to the power ground.
The key assembly 11 includes a key S1.
The description of fig. 3 is further described below in conjunction with the working principle:
when the system is powered off, the key S1 is pressed for a short time (less than a preset time), the first end of the key S1 outputs a low-level key signal less than the preset time, the low-level key signal generates a voltage signal in a first level state (low level) through the second diode D2 and the eighth resistor R8, the gate of the fourth fet M4 is pulled down to low level, the fourth fet M4 is turned on, the fourth fet M4 outputs an input voltage VIN to the power supply terminal VCC of the microprocessor U1, and the microprocessor U1 is powered on to operate according to the input voltage VIN and outputs a power-on signal from the data input/output terminal P1.0 of the microprocessor U1; the first triode D5 is turned on according to the power-on signal, so as to control the gate of the fourth fet M4 to maintain the first level state, and at this time, the key S1 can be released, thereby implementing the short-press power-on function.
When the system is powered on, the key S1 is pressed for a long time (greater than or equal to a preset time), the voltage of the gate of the first fet Q1 is the voltage divided by the first resistor R1 and the second resistor R2, the first fet Q1 is turned on and outputs a control voltage, wherein the first capacitor C1 is a slow start capacitor of the first fet Q1, and the voltage ramp time of the gate of the first fet Q1 can be controlled by setting parameters of the first resistor R1, the second resistor R2 and the first capacitor C1, so as to control the start delay of the first fet Q1, which can be used as the first time delay T1 for long-time press power-off.
After the first fet Q1 is turned on, if the button S1 is pressed all the time, the control voltage charges the second capacitor C2 through the third resistor R3 and the fifth resistor R5, and finally charges the second capacitor C2 to the divided voltage value of the fourth resistor R4 and the third resistor R3, and the second fet Q2 can be set to delay the on-time T2 by setting the parameters of the third resistor R3, the fourth resistor R4, the fifth resistor R5, and the second capacitor C2.
After the second fet Q2 is turned on, the gate of the third fet Q3 is pulled to the power ground by the second fet Q2, at this time, the third fet Q3 is turned on and outputs a voltage signal in the second level state (high level), and the fourth fet Q4 is turned off, so that the output of the input voltage VIN is cut off, thereby realizing the long press shutdown function.
When the input voltage VIN is greater than the stabilized voltage of the regulator tube Z1, the regulator tube Z1 is reversely broken down, and the regulator tube Z1 is in a voltage stabilization protection state. At this time, the third fet Q3 is turned on, and the fourth fet Q4 is turned off, thereby implementing an overvoltage protection function.
The first diode D1 is a fast discharge diode of the second capacitor C2, when the key S1 is released, the first field effect transistor Q1 is cut off, the second capacitor C2 discharges through the first diode D1 and the fourth resistor R4, and the capacitor of the pole plate of the second capacitor C2 can be discharged to 0 within the shortest time, so that the situation that the set long-time press shutdown time is not disordered when the key S1 is continuously pressed or released is guaranteed. Without the first diode D1, the second capacitor C2 is discharged via the fifth resistor R5 and the fourth resistor R4, the discharge time being almost equal to the charge time due to the coincidence of the charge and discharge paths. If the key S1 is pressed again during the discharging time, the time for the second capacitor C2 to charge to the on voltage of the second fet Q2 is shortened, and the long-press shutdown time is inaccurate.
It should be noted that the condition of the long press power off is that the pressed time length of the key S1 is longer than the sum of T1 and T2, i.e., the preset time length is the sum of T1 and T2.
The embodiment of the utility model provides a Point of Sale terminal (POS machine) is still provided, the POS machine includes foretell switch circuit.
The embodiment of the utility model has the input end connected with the power supply and the output end connected with the load through the first switch circuit; when the key assembly is switched on and is lower than the preset time length, controlling the control end of the first switch circuit to be in a first level state so as to drive the first switch circuit to be conducted; when the maintaining circuit receives the power-on signal, the control end of the first switch circuit is controlled to be maintained in a first level state according to the power-on signal; when the key assembly is switched on for a time longer than the preset time, the second switch circuit outputs a voltage signal to enable the control end of the first switch circuit to be in a second level state so as to drive the first switch circuit to be switched off; the short-press startup and long-press shutdown functions are realized through a simple circuit structure, so that the cost can be remarkably reduced, and the circuit complexity of a system can be remarkably reduced; furthermore, the embodiment of the utility model provides a can also be by oneself according to specific demand set time threshold value, it is more nimble for chip class scheme, can couple some OverVoltage Protection (OVP) functions moreover.
The above description is only for the preferred embodiment of the present invention, and is not intended to limit the present invention, and any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention should be included within the protection scope of the present invention.
Claims (9)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202021001251.9U CN212785304U (en) | 2020-06-03 | 2020-06-03 | Startup and shutdown circuit and POS machine |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202021001251.9U CN212785304U (en) | 2020-06-03 | 2020-06-03 | Startup and shutdown circuit and POS machine |
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| Publication Number | Publication Date |
|---|---|
| CN212785304U true CN212785304U (en) | 2021-03-23 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202021001251.9U Active CN212785304U (en) | 2020-06-03 | 2020-06-03 | Startup and shutdown circuit and POS machine |
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| CN (1) | CN212785304U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113489478A (en) * | 2021-07-12 | 2021-10-08 | 重庆建安仪器有限责任公司 | Button on/off control circuit for low-voltage power supply |
| CN114237092A (en) * | 2021-11-18 | 2022-03-25 | 北京卫星制造厂有限公司 | Level signal type on-off control circuit |
-
2020
- 2020-06-03 CN CN202021001251.9U patent/CN212785304U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113489478A (en) * | 2021-07-12 | 2021-10-08 | 重庆建安仪器有限责任公司 | Button on/off control circuit for low-voltage power supply |
| CN113489478B (en) * | 2021-07-12 | 2022-11-22 | 重庆建安仪器有限责任公司 | Button on/off control circuit for low-voltage power supply |
| CN114237092A (en) * | 2021-11-18 | 2022-03-25 | 北京卫星制造厂有限公司 | Level signal type on-off control circuit |
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