CN213071148U

CN213071148U - Semiconductor device with a plurality of semiconductor chips

Info

Publication number: CN213071148U
Application number: CN201890001587.XU
Authority: CN
Inventors: 高桥哲平; 井上徹人; 菅井昭彦; 望月孝; 中村俊一
Original assignee: Shindengen Electric Manufacturing Co Ltd
Current assignee: Shindengen Electric Manufacturing Co Ltd
Priority date: 2018-04-11
Filing date: 2018-04-11
Publication date: 2021-04-27
Anticipated expiration: 2028-04-11
Also published as: WO2019198167A1

Abstract

The semiconductor device includes: a semiconductor substrate composed of silicon carbide; a drift layer of a first conductivity type formed on one main surface of the semiconductor substrate; and a well region of a second conductivity type formed on the drift layer layer; a source region of the first conductivity type, which is formed on the well region; an insulating film, which is formed on the drift layer; a contact metal film, which is formed on the insulating film , and the two regions, the source region and the well region, are in contact with each other through an opening provided in the insulating film; and a source electrode film is formed so as to contact the contact metal film. Wherein, the contact metal film includes titanium nitride.

Description

Semiconductor device with a plurality of semiconductor chips

Technical Field

The utility model relates to a semiconductor device.

Background

Silicon carbide (SiC) has an electric field strength of about 10 times that of silicon (Si), and thus is used as a material for a high-voltage semiconductor device (see, for example, patent document 1).

Prior art documents

Patent document

Patent document 1: japanese unexamined patent publication Hei 09-283738

In order to manufacture a semiconductor device, for example, in a source portion of a MOSFET, an ohmic electrode needs to be formed on a substrate. Electrodes in semiconductor devices are generally formed by forming a metal film called a contact metal on a semiconductor substrate, and forming an electrode film (e.g., an alloy containing aluminum and silicon (Al — Si), aluminum (Al)) thereon.

In order to form an ohmic electrode with high reliability, a material of a contact metal in contact with a semiconductor substrate is a critical point. Titanium (Ti), which is a representative electrode material, forms a schottky junction with n-type silicon carbide.

While nickel (Ni), which is also a representative electrode material, has a low contact resistance value. However, in actual manufacturing processes, nickel silicide is formed at the silicon carbide/nickel interface upon annealing. This causes free carbon to be generated in the electrode, and the adhesion between the silicon carbide and the electrode is reduced.

Conventionally, titanium nitride (TiN) has been known to be very useful as a material for a contact metal film for n-type silicon carbide (see patent document 1). That is, it is known that both high adhesion between n-type silicon carbide and an electrode and low contact resistance can be obtained by using a contact metal film formed of titanium nitride. On the other hand, however, it has been known that when a heat treatment at 1050 ℃ which is disclosed uniquely in the examples of patent document 1 is used, nitrogen atoms (N) as an donating element are diffused from titanium nitride as a contact metal into silicon carbide. Therefore, if it is intended to improve the adhesion of the p-type titanium silicon carbide nitride contact metal film by annealing, nitrogen atoms may diffuse by heating, and the contact resistance value may also be increased. Thus, it is difficult to form a good contact metal film using titanium nitride for p-type silicon carbide.

In view of the above, an object of the present invention is to provide a semiconductor device having an ohmic electrode with high reliability and a method for manufacturing the same.

Disclosure of Invention

The utility model discloses a semiconductor device that mode relates to, a serial communication port, include:

a semiconductor substrate made of silicon carbide;

a drift layer of a first conductivity type provided on one main surface of the semiconductor substrate;

a well region of a second conductivity type disposed on the drift layer;

a source region of the first conductivity type disposed on the well region;

an insulating film provided on the drift layer;

a contact metal film provided on the insulating film and contacting both the source region and the well region via an opening portion provided in the insulating film; and

a source electrode film formed as: is in contact with the contact metal film,

wherein the contact metal film comprises titanium nitride.

The present invention according to one aspect provides a method for manufacturing a semiconductor device, including:

a drift layer forming step of forming a drift layer of a first conductivity type on one main surface of a semiconductor substrate made of silicon carbide;

a well region forming step of forming a well region of a second conductivity type opposite to the first conductivity type and exposed on a surface of the drift layer on the drift layer;

a source region forming step of forming a source region of the first conductivity type exposed on a surface of the drift layer on the well region of the drift layer;

an insulating film forming step of forming an insulating film having an opening on a surface of the drift layer, the opening being formed so as to: at least a part of the source region is exposed when viewed in a plane from the side of the one main surface;

a contact metal film forming step of forming a contact metal film so as to be in contact with the source region in the opening; and

a source electrode film forming step of forming a source electrode film so as to be in contact with the contact metal film,

wherein the contact metal film comprises titanium nitride.

Effects of the invention

According to the semiconductor device and the method for manufacturing the semiconductor device of the present invention, the ohmic contact having high adhesion to the semiconductor substrate can be formed with a single electrode material. Thus, a semiconductor device having an ohmic electrode with high reliability can be provided without going through a complicated process.

Drawings

Fig. 1 is a sectional view showing a configuration of a semiconductor device according to a first embodiment.

Fig. 2 is a flowchart showing a method for manufacturing a semiconductor device according to the first embodiment.

Fig. 3A is a sectional view showing a method for manufacturing a semiconductor device according to the first embodiment.

Fig. 3B is a sectional view showing the method of manufacturing the semiconductor device according to the first embodiment.

Fig. 3C is a sectional view showing the method for manufacturing the semiconductor device according to the first embodiment.

Fig. 4A is a sectional view showing a method for manufacturing a semiconductor device according to the first embodiment.

Fig. 4B is a sectional view showing the method of manufacturing the semiconductor device according to the first embodiment.

Fig. 4C is a sectional view showing the method of manufacturing the semiconductor device according to the first embodiment.

Fig. 5A is a sectional view showing a method for manufacturing a semiconductor device according to the first embodiment.

Fig. 5B is a sectional view showing the method of manufacturing the semiconductor device according to the first embodiment.

Detailed Description

[ first embodiment ] to provide a liquid crystal display device

Hereinafter, a first embodiment of the present invention will be described with reference to fig. 1 to 5.

(Structure of semiconductor device)

Hereinafter, the configuration of the semiconductor device according to the present embodiment will be described with reference to fig. 1. The semiconductor device according to this embodiment is a planar MOSFET. In the semiconductor device according to this embodiment, although a plurality of semiconductor elements are arranged adjacent to each other, only one of the semiconductor elements is shown in fig. 1.

The present embodiment is specifically described for better understanding of the gist of the present invention, and the present invention is not limited thereto unless otherwise specified. In addition, in order to facilitate understanding of the features of the present invention, the drawings used in the following description may show the main portions in an enlarged manner, and the dimensional ratios of the respective components are not necessarily the same as those in reality.

As shown in fig. 1, a semiconductor device 1 includes: a semiconductor substrate 101; a drift layer 102; a well region 103; a source region 104; an insulating film 105; a contact metal film 107 and a source electrode film 108. The semiconductor device 1 further includes a high concentration second conductive type region 109. The semiconductor device 1 further includes a drain electrode 110 and a gate electrode 111.

Semiconductor substrate101 is made of silicon carbide (SiC) and is doped with an n-type dopant (first conductivity type). The semiconductor substrate 101 is n⁺A silicon carbide single crystal substrate of type. The semiconductor substrate 101 is, for example, an n-type 4H — SiC substrate on the (0001) plane.

The drift layer 102 is made of silicon carbide, and is formed on the one principal surface F1 of the semiconductor substrate 101. An n-type dopant is introduced into the drift layer 102 at a lower concentration than the semiconductor substrate 101.

The drain electrode 110 is formed on the other main surface F2 of the semiconductor substrate 101. The drift layer 102 and the drain electrode 110 are ohmically connected via the semiconductor substrate 101. The drain electrode 110 may be formed using, for example, titanium nitride.

The well region 103 is formed on a part of the surface on the opposite side to the semiconductor substrate 101 on the drift layer 102. A p-type (second conductivity type) dopant is introduced into the well region 103.

A high concentration second conductivity type region 109 is formed on a part of the surface of the well region 103. In the high concentration second conductivity type region 109, a p-type dopant is introduced at a higher concentration than the other well regions 103 (well regions 103 not including the high concentration second conductivity type region 109). The concentration of p-type dopant is greater than or equal to 2 x 10¹⁹/cm³Preferably, it is not less than 2X 10²⁰/cm³. This can suppress the operation of the parasitic bipolar transistor in the semiconductor device 1. Further, ohmic contact with the electrode can be accurately performed.

A source region 104 is formed on a portion of the surface of the well region 103. On the source region 104, n-type dopants are introduced at a higher concentration than the drift layer 102. When viewed in plan from the side F1 of the one main surface of the semiconductor substrate 101 (hereinafter referred to as "in plan view"), the source region 104 is surrounded by the well region 103.

In this embodiment mode, the source region 104 is formed in a ring shape when viewed in plan. As shown in fig. 1, in the present embodiment, the source region 104 is formed of a first source region 104a into which n-type dopant of high concentration is introduced and which is ring-shaped in plan view, and a second source region 104b into which n-type dopant of low concentration is introduced outside the first source region 104a, but the structure of the source region 104 is not limited thereto.

The insulating film 105 is made of an insulator and is formed on the surface of the drift layer 102. The insulating film 105 has an opening 106. The opening 106 is formed such that: at least a portion of the source region 104 and at least a portion of the high concentration second conductive type region 109 are exposed when viewed in plan. In the present embodiment, the opening 106 is formed as follows: a portion of the first source region 104a is exposed.

The gate electrode 111 is formed across, as viewed in plan: the region of the well region 103 where the source region 104 is not formed, the region of the drift layer 102 where the well region 103 is not formed, and the source region 104 are opposed to each other with the region therebetween. Second, the gate electrode 111 may also be formed so as to straddle: another well region (not shown) that faces the well region 103 across the drift layer 102, and a source region (not shown) that faces the well region across the other well region.

In a state where no voltage is applied to the gate electrode 111 (or in a state where a negative voltage is applied), even if a forward bias voltage is applied between the source region 104 and the drain electrode 110, a current does not flow between the source region 104 and the drain electrode 110. In a state where a forward bias voltage is applied between the source region 104 and the drain electrode 110, if a positive voltage is applied to the gate electrode 111, an inversion channel whose conductivity type is inverted with respect to the well region 103 is formed on the surface of the region of the well region 103 which is opposed to the gate electrode 111. Thus, a current flows between the source region 104 and the drain electrode 110. That is, the current between the source region 104 and the drain electrode 110 can be controlled by applying a voltage toward the gate electrode 111.

The contact metal film 107 is formed as: the opening 106 is in contact with the source region 104 and the well region 103. The contact metal film 107 is formed of titanium nitride. In particular, in the present embodiment, the contact metal film 107 is formed such that: contacts a portion of the first source region 104a and a portion of the high concentration second conductive type region 109.

The source electrode film 108 is formed as: is in contact with the contact metal film 107. The source electrode film 108 is formed of, for example, an alloy containing aluminum and silicon, or an alloy containing aluminum and copper, or aluminum. The source regions 104 of the plurality of semiconductor elements are connected to each other by a source electrode film 108.

In this embodiment mode, the contact metal film 107 is formed of titanium nitride. Therefore, unlike the case where titanium is used for the contact metal film, since a schottky junction is not formed with n-type silicon carbide, an ohmic contact can be formed. Further, unlike the case where nickel is used for the contact metal film, since free carbon is not generated at the time of annealing, adhesion between silicon carbide and the electrode is not lowered.

In addition, a contact metal film 107 made of titanium nitride is provided in contact with both the high-concentration second conductivity type region 109 and the source region 104 which are adjacent to each other in plan view. Therefore, by selecting a heating condition that can suppress diffusion of nitrogen atoms of the contact metal film 107 into the high concentration second conductivity type region 109, diffusion of nitrogen atoms from the contact metal film 107 into the high concentration second conductivity type region 109 is suppressed by heating, and therefore, the contact resistance value in the high concentration second conductivity type region 109 can be reduced. Thus, even for p-type silicon carbide, a favorable contact metal film can be formed using titanium nitride.

According to this embodiment, an ohmic contact having high adhesion to a semiconductor substrate can be formed using a single electrode material (titanium nitride). Therefore, it is not necessary to separately produce: a contact metal layer in contact with the source region 104 containing n-type dopants, and a contact metal layer in contact with the high concentration second conductive type region 109 containing p-type dopants. This can reduce the margin for the photolithography process. Thus, the cell pitch of the semiconductor element can be reduced and the manufacturing cost can be reduced, and therefore, a semiconductor device having an ohmic electrode with high reliability can be provided without a complicated process.

(method of manufacturing semiconductor device)

Hereinafter, a method for manufacturing a semiconductor device according to the present embodiment will be described with reference to fig. 2 to 5.

As shown in fig. 2, the method for manufacturing a semiconductor device according to the present embodiment includes: a drift layer forming step S1; a well region forming step S2; a source region forming step S3; an insulating film forming step S4; a contact metal film forming step S5 and a source electrode film forming step S6.

Hereinafter, each step in the method for manufacturing a semiconductor device according to the present embodiment will be described with reference to fig. 3 to 5. In the semiconductor device according to this embodiment, although a plurality of semiconductor elements are arranged adjacent to each other, only one of the semiconductor elements is shown in fig. 3 to 5.

(S1: Process for Forming drift layer)

First, the drift layer forming process S1 shown in fig. 3A is performed. In the drift layer forming step S1, n produced by, for example, sublimation is first formed⁺The type silicon carbide single crystal is processed into a wafer (disk) shape as a substrate. At the n⁺N is formed on the upper surface of the type silicon carbide single crystal substrate by Chemical Vapor Deposition (CVD)^-And (3) a type silicon carbide epitaxial layer. Thus, n is formed on the one principal surface F1 of the n-type semiconductor substrate 101 made of silicon carbide^-And an n-type drift layer 102 formed of an epitaxial layer of type silicon carbide.

(S2: well region Forming Process)

Next, the well region forming process S2 shown in fig. 3B is performed. In the well region forming step S2, the surface of the drift layer 102 is first cleaned. Subsequently, silicon dioxide (sio) is formed on the surface of the drift layer 102₂) An oxide film (not shown) formed. Then, a resist pattern (not shown) is formed only at a portion where the p-type dopant is not introduced using a known photolithography technique. Next, the oxide film in a portion not protected by the resist pattern is etched by Reactive Ion Etching (RIE), thereby forming a mask (not shown) having an opening at a portion corresponding to the well region 103. After that, the resist pattern is removed. In this state, a p-type dopant (e.g., aluminum) is introduced into the drift layer 102 by ion implantation. After the p-type dopant is introduced, the mask is removed. Thereby, a p-type well region 103 exposed in a part of the drift layer 102 is formed. In addition, high concentrationA second conductivity type region 109 is also formed on a portion of the surface of the well region 103 in the same step. The high concentration second conductive type region 109 may be formed between the source region forming step S3 and the insulating film forming step S4, for example.

(S3: Source region Forming Process)

Next, the source region forming process S3 shown in fig. 3C is performed. In the source region forming step S3, first, a mask (not shown) having an opening is formed in a portion corresponding to the first source region 104a, similarly to the well region forming step S2. In this state, an N-type dopant, such as phosphorus (P) or nitrogen (N), is introduced using ion implantation on a part of the well region 103 in the drift layer 102. After the n-type dopant is introduced, the mask is removed. Thereby forming the first source region 104a exposed at a portion of the surface of the well region 103. In addition, the second source region 104b is also formed on a part of the surface of the well region 103 in the same step.

In the well region forming step S2 and the source region forming step S3, after the dopant is introduced by ion implantation, annealing is performed at 1650 to 1800 ℃, for example, in order to activate the implanted dopant.

(S4: insulating film formation Process)

Next, the insulating film forming step S4 shown in fig. 4A to C is performed. In the insulating film forming step S4, first, as shown in fig. 4A, the oxide film 105a is formed on the surface of the drift layer 102. Subsequently, a polysilicon film is formed on the oxide film 105a by chemical vapor deposition. After the polysilicon film is formed, an n-type dopant (e.g., phosphorus) is introduced into the polysilicon film. After the introduction of the dopant, a resist pattern (not shown) for protecting a portion corresponding to the gate electrode 111 is formed using a known photolithography technique. Subsequently, portions not protected by the resist pattern are removed by dry etching. After that, the resist pattern is removed. Thereby, as illustrated in fig. 4B, the gate electrode 111 is formed. Next, silicon dioxide is formed by chemical vapor deposition so as to cover the gate electrode 111, and an oxide film 105b is formed. After that, a resist pattern (not shown) having an opening is formed at a portion corresponding to the opening portion 106 using a known photolithography technique. In the

oxide films

105a and 105b, portions not protected by the resist pattern are removed by dry etching. After that, the resist pattern is removed. As a result, as shown in fig. 4C, an insulating film 105 including

oxide films

105a and 105b and having an opening 106 is formed, and the opening 106 is formed such that: at least a portion of the source region 104 is exposed when viewed from a plane.

(S5: Process for Forming contact Metal film)

Next, the contact metal film forming process S5 shown in fig. 5A is performed. In the contact metal film forming step S5, nitrogen (N) is first added₂) In a mixed atmosphere with argon (Ar) or in nitrogen (N)₂) Titanium nitride is formed on the surface of the insulating film 105 by sputtering in an atmosphere at a substrate temperature of, for example, 150 to 350 ℃. In the contact metal film forming step S5, for example, titanium nitride may be formed on the other main surface F2 of the semiconductor substrate 101.

Subsequently, annealing is performed. The annealing temperature is preferably 800 to 1000 ℃, and more preferably 950 ℃. Once the temperature is 1050 deg.c or higher, nitrogen atoms diffuse from titanium nitride forming the contact metal film 107 to p-type silicon carbide, which results in an increase in contact resistance of the p-type silicon carbide portion. In addition, the annealing time of the p-type silicon carbide is 20-40 minutes. The annealing is performed in, for example, a mixed atmosphere of nitrogen and argon. Thereby forming a contact metal film 107 in contact with the source region 104. At the same time, the drain electrode 110 that is ohmically connected to the drift layer 102 is formed on the other main surface F2 of the semiconductor substrate 101 via the semiconductor substrate 101.

In this embodiment, the drain electrode 110 is formed in the contact metal film forming step S5, but another step may be provided to form the drain electrode 110.

When nickel is used for the contact metal, nickel silicide is formed at the interface during annealing to generate free carbon, which lowers the adhesion between silicon carbide and the contact metal film. In view of this problem, in the present embodiment, since free carbon is not generated during annealing, the adhesion of the contact metal film 107 can be maintained. In this embodiment, if the annealing temperature is 1000 ℃ or less, a good ohmic contact can be obtained for p-type silicon carbide.

(S6: Source electrode film Forming Process)

Finally, the source electrode film forming process S6 shown in fig. 5B is performed. In the source electrode film forming step S6, an alloy containing aluminum and silicon, an alloy containing aluminum and copper, or aluminum is formed by sputtering: is in contact with the contact metal film 107. Thereby, the source electrode film 108 connected to the source regions 104 of the plurality of semiconductor elements is formed. In the source electrode film 108, a portion unnecessary for connection to the source region 104 is removed by appropriate etching. Thereby forming the semiconductor device 1.

According to the method for manufacturing a semiconductor device of this embodiment mode, the contact metal film 107 is formed of titanium nitride. Therefore, unlike the case where titanium is used for the contact metal film, since a schottky junction is not formed with n-type silicon carbide, an ohmic contact can be formed. Further, unlike the case where nickel is used for the contact metal film, since free carbon is not generated at the time of annealing, adhesion between silicon carbide and the electrode is not lowered.

According to the method for manufacturing a semiconductor device of the present embodiment, an ohmic contact having high adhesion to a semiconductor substrate can be formed using a single electrode material (titanium nitride). Therefore, it is not necessary to separately produce: a contact metal layer in contact with the source region 104 containing n-type dopants, and a contact metal layer in contact with the high concentration second conductive type region 109 containing p-type dopants. This can reduce the margin for the photolithography process. Thus, the cell pitch of the semiconductor element can be reduced and the manufacturing cost can be reduced, and therefore, a semiconductor device having an ohmic electrode with high reliability can be provided without a complicated process.

In addition, according to the method of manufacturing a semiconductor device according to the present embodiment, in the drift layer forming step S1, a silicon carbide epitaxial layer is formed on the upper surface of the silicon carbide single crystal substrate by a chemical vapor deposition method. Therefore, unlike a method for manufacturing a semiconductor device in which a titanium nitride film is directly formed on a silicon carbide single crystal substrate (see, for example, patent document 1), damage occurring on a processing surface (that is, a surface of the silicon carbide single crystal substrate) when processing a silicon carbide single crystal into a wafer shape does not affect a contact metal film. In this way, since nitrogen atoms can be suppressed from diffusing from the contact metal film made of titanium nitride into silicon carbide, the contact resistance value can be reduced.

[ second embodiment ]

Hereinafter, a second embodiment of the present invention will be described. The description will be omitted for portions common to the first embodiment.

(Structure of semiconductor device)

The semiconductor device of the present embodiment is an Insulated Gate Bipolar Transistor (IGBT). The semiconductor device of this embodiment is a semiconductor device except that the semiconductor substrate 101 is p⁺The structure other than the type (second conductivity type) is the same as that of the first embodiment. The semiconductor device of this embodiment has the same effects as those of the first embodiment.

(method of manufacturing semiconductor device)

The method for manufacturing a semiconductor device according to this embodiment includes: a drift layer forming step S1 similar to the first embodiment; a well region forming step S2; a source region forming step S3; an insulating film forming step S4; a contact metal film forming step S5 and a source electrode film forming step S6.

However, in this embodiment, the drift layer is formedThe semiconductor substrate 101 prepared in the sequence S1 is p⁺The type (second conductivity type) is different from that of the first embodiment.

The method for manufacturing a semiconductor device according to this embodiment has the same effects as those of the first embodiment.

Although the embodiments of the present invention have been described above, the present invention can be implemented in other embodiments. For example, the source electrode film 108 is formed using an alloy containing aluminum and silicon, an alloy containing aluminum and copper, or aluminum, but a conductive material such as another metal may be used. Further, although the source region 104 is formed in a ring shape in plan view and the region surrounded by the source region 104 includes the high concentration second conductivity type region 109, the shape of the source region 104 is not limited thereto, and the high concentration second conductivity type region 109 may not be provided. In the above embodiment, the first conductivity type is n-type and the second conductivity type is p-type, but the first conductivity type may be p-type and the second conductivity type may be n-type.

Further, in the above-described embodiment, although the source region 104 is surrounded by the well region 103 in plan view and is formed in a ring shape while being adjacent to the high concentration region 109 and is a "square cell structure" surrounding the high concentration region 109 in plan view, it is not limited to this configuration. The semiconductor device of the present invention may have a "stripe cell structure" having a cross section as shown in fig. 1, for example. In this case, the well region 103 is a region extending in a direction substantially perpendicular to the cross section of the semiconductor device when viewed in plan. The high concentration region 109 is included in the well region 103 as viewed in plan, and is a region extending in the same direction as the well region 103. The source region 104 is included in the well region 103 in plan view, and is a pair of regions extending adjacent to both sides of the high concentration region 109.

Various design changes can be made within the scope of the items described in the claims.

Description of the symbols

1 … semiconductor device

101 … semiconductor substrate

102 … drift layer

103 … well region

104 … source region

105 … insulating film

106 … opening part

107 … contact metal film

108 … Source electrode film

109 … high concentration second conduction type region

One main face of F1 …

F2 … another main face

S1 … drift layer Forming Process

S2 … well region forming process

S3 … Source region Forming Process

S4 … insulating film Forming Process

S5 … contact metal film formation step

S6 … Source electrode film Forming Process

Claims

1. A semiconductor device, comprising:

a semiconductor substrate consisting of silicon carbide;

a drift layer of the first conductivity type, which is arranged on one main surface of the semiconductor substrate;

A well region of the second conductivity type is disposed on the drift layer;

a source region of the first conductivity type disposed on the well region;

an insulating film disposed on the drift layer;

a contact metal film provided on the insulating film and contacting both the source region and the well region through an opening provided in the insulating film; and

a source electrode film formed to contact the contact metal film,

Wherein, the contact metal film includes titanium nitride.

2. The semiconductor device according to claim 1, wherein:

Here, the source electrode film is formed of an alloy containing aluminum and silicon, an alloy containing aluminum and copper, or aluminum.

3. The semiconductor device according to claim 1 or 2, wherein:

The source region is formed in a ring shape when viewed in plan from one side of the one main surface of the semiconductor substrate.

4. The semiconductor device of claim 3, wherein:

The well region includes a high-concentration second-conductivity-type region surrounded by the source region when viewed in plan from the side of the one main surface of the semiconductor substrate.

5. The semiconductor device according to claim 1 or 2, wherein:

Wherein, when viewed in plan from one side of the one main surface of the semiconductor substrate, the source regions are a pair of regions that are spaced apart from each other and extend in a direction parallel to the one main surface repeating composition.

6. The semiconductor device of claim 5, wherein:

The well region includes a high-concentration second-conductivity-type region sandwiched by the source region when viewed in plan from the one main surface side of the semiconductor substrate.