CN220776394U - Semiconductor device - Google Patents

Abstract

The present disclosure relates to a semiconductor device. According to the semiconductor device of the present disclosure, it includes: a carrier substrate; a buried dielectric region covering the carrier substrate; a semiconductor film separated from the carrier substrate by the buried dielectric region; and an NMOS transistor and a PMOS transistor, which are arranged at the surface of the semiconductor film and coupled together to form a static random access memory SRAM cell, and the NMOS transistor and the PMOS transistor each include a gate dielectric layer having a thickness greater than 3 nanometers and an active region in the semiconductor film. The embodiments of the present disclosure advantageously allow the reverse bias to be applied independently to the NMOS and PMOS transistors.

Description

Semiconductor device

Technical Field

Implementations and embodiments relate to semiconductor devices of the silicon-on-insulator type, for example implementing static RAM circuits.

Background technique

Semiconductor devices of the silicon-on-insulator type, which are usually manufactured inside integrated circuits, usually include a semiconductor film separated from a carrier substrate by a buried dielectric region. For example, in a technology called FDSOI (Fully Depleted Silicon On Insulator), the semiconductor film advantageously has a thickness fine enough to completely deplete the minority charges.

Conventionally, a static RAM (usually SRAM for static random access memory) includes a memory cell provided with two PMOS transistors and two NMOS transistors (commonly known to those skilled in the art as "p-type/n-type metal oxide semiconductor") connected between a power supply terminal and a ground terminal to form two top to tail inverters, and typically two access transistors, usually NMOS transistors, coupled between a bit line and a data node (i.e., the input-output node of the inverter) and controlled by a signal transmitted on a word line.

Writing and reading of data segments in an SRAM cell are performed via access transistors and bit lines by applying a voltage level on a data node when writing or measuring a voltage level on a data node when reading. Retention of data segments in a memory cell is achieved by the stable state of the signal generated on the data node of an assembly of top-to-tail inverters.

In the "write-read" mode, the supply voltage is generated at a nominal level, ie the normal operating level of the transistors, for example between 0.8 and 1.2 volts for semiconductor devices of the silicon-on-insulator type, in order to have a well-defined and distinguishable steady state in the memory cell.

In the "retention" mode of an SRAM cell, it is advantageous to reduce the energy consumption of the device as much as possible. The supply voltage can be minimized, but still remain greater than the threshold voltage of the cell's transistors so as not to lose the stable state of the SRAM cell and the data fragments retained thereby. Therefore, it is desirable to propose an SRAM memory cell technology with the lowest possible current leakage. The FDSOI technology with the highest performance in terms of current leakage (often called ULL for "ultra-low leakage") has a result of about 1 picoampere (or 1000 femtoamperes) in retention mode.

Utility Model Content

An object of the present disclosure is to provide a semiconductor device to at least partially solve the above-mentioned problems existing in the prior art.

One aspect of the present disclosure provides a semiconductor device, comprising: a carrier substrate; a buried dielectric region covering the carrier substrate; a semiconductor film separated from the carrier substrate by the buried dielectric region; and an NMOS transistor and a PMOS transistor, arranged at a surface of the semiconductor film and coupled together to form a static random access memory SRAM cell, the NMOS transistor and the PMOS transistor each comprising a gate dielectric layer having a thickness greater than 3 nanometers and an active region in the semiconductor film.

According to one or more embodiments, the gate dielectric layer of the NMOS transistor and the PMOS transistor has a thickness between the active region and the gate conductive region of between 3.5 nanometers and 6 nanometers.

According to one or more embodiments, the semiconductor device further includes a plurality of additional PMOS transistors, wherein the active regions of the plurality of the PMOS transistors extend along a first direction.

According to one or more embodiments, the further PMOS transistor is coupled to a further NMOS transistor to form a further SRAM cell, wherein the active area of the further PMOS transistor and the active area of the NMOS transistor extend along the first direction to incorporate other SRAM cells.

According to one or more embodiments, the active regions of the plurality of PMOS transistors extend along the first direction so as not to relax compressive stress in the first direction.

According to one or more embodiments, wherein the NMOS transistor and the PMOS transistor are respectively located in doped wells of the carrier substrate, the device further includes a bias circuit coupled to the doped wells of the carrier substrate.

According to one or more embodiments, wherein the bias circuit is configured to generate voltages suitable for reverse back biasing of the PMOS and NMOS transistors in the respective doped wells of the carrier substrate.

According to one or more embodiments, the NMOS transistor is located in a p-type doped well in the carrier substrate, and the PMOS transistor is located in an n-type doped well in the carrier substrate.

According to one or more embodiments, the bias circuit is configured to generate a reverse back bias voltage between 0 volts and -2 volts in the p-type doped well.

According to one or more embodiments, the bias circuit is configured to generate a reverse back bias voltage between 0 volts and +2 volts in the n-type doped well.

According to one or more embodiments, the bias circuit is configured to generate a voltage suitable for reverse biasing of the PMOS and NMOS transistors in a mode for retaining a data segment of the memory cell, rather than in a read/write mode of the memory cell.

According to one or more embodiments, the bias circuit is configured to generate a power supply voltage for the memory cell having a nominal level in a read/write mode and having a voltage of 50% to 85% of the nominal level in a mode for retaining data fragments.

Utilizing embodiments of the present disclosure advantageously allows for independent application of reverse bias on NMOS and PMOS transistors.

BRIEF DESCRIPTION OF THE DRAWINGS

Other advantages and features of the invention will become apparent upon examination of the detailed description of specific embodiments and examples (which are in no way limiting) and of the accompanying drawings, in which:

FIG1 schematically shows a semiconductor device DSM of the silicon-on-insulator type;

FIG. 2 shows a circuit diagram of an SRAM storage cell;

FIG. 3 shows an example of a layout in a top view of a circuit of a memory cell as described above with respect to FIGS. 1 and 2 ;

FIG4 shows the results of the intensity of the current leakage of the memory cell; and

FIG. 5 shows a simplified example of a method for manufacturing a semiconductor device.

Detailed ways

The embodiments are first described in the text, and examples are then explained with respect to the figures.

According to one aspect, in this regard, a semiconductor device of the silicon-on-insulator type is proposed, comprising a semiconductor film separated from a carrier substrate by a buried dielectric region. The device comprises a static RAM circuit having at least one unit memory, the unit memory comprising an NMOS transistor and a PMOS transistor, each transistor comprising a gate dielectric layer having a thickness greater than 3 nanometers and an active region in the respective semiconductor film. The active region of the PMOS transistor is made of a silicon-germanium alloy.

Relative to typical SRAM memory architectures using FDSOI technology, the thickness of the gate dielectric layer of the transistor is large, which is greater than 3 nanometers. In practice, the thickness of the gate dielectric layer is typically 1 nanometer to 1.5 nanometers. Therefore, the memory cell defined according to this aspect has extremely small gate current leakage. However, the memory cell according to this aspect may have a volume greater than that in a conventional architecture (thickness from 1nm to 1.5nm), and in addition, the threshold voltages of the NMOS and PMOS transistors are greater than those in a conventional architecture (thickness from 1nm to 1.5nm). In particular, the active region of the PMOS transistor made of a silicon-germanium alloy having a compressive stress in the channel (source-drain) direction of the transistor allows the threshold voltage of the PMOS transistor to be reduced, and thus has appropriate performance, especially in terms of stability in read and write modes, without increasing the power supply voltage. The increase in the threshold voltage of the NMOS transistor advantageously allows the current leakage of the conductive region of the NMOS transistor to the ground to be reduced.

The term "active area" refers in a usual and well-known manner to those skilled in the art to a designated area of a semiconductor film that is not covered by a lateral isolation region, such as a shallow isolation trench (typically shallow trench isolation), so that an interface between the gate region and the channel region of the transistor and an interface between the source and drain regions are formed in the active region.

According to one embodiment, the gate dielectric layer of the NMOS transistor and the PMOS transistor has a thickness between 3.5 nanometers and 6 nanometers between the active region and the gate conductive region.

For example, the gate dielectric layer of the NMOS transistor and the PMOS transistor comprises a portion made of silicon oxide, for example made of “SiON” silicon oxynitride (or SiO _x N _y , typically Si ₂ O ₂ N), having a thickness between 1 nanometer and 3.5 nanometers, and optionally comprises a portion made of a “high dielectric constant” (typically “high-k”) dielectric, for example hafnium oxide, having a thickness of substantially 2.5 nanometers, located above the portion made of silicon oxide, in particular in a technology known as “high-k/metal gate”, that is, a technology that comprises a “high dielectric constant” dielectric and a portion made of metal in the gate conductive region.

A total thickness of the gate dielectric layer between 3.5 nm and 6 nm may, for example, correspond to a gate dielectric for a "medium voltage" transistor intended to operate at voltages up to 1.8 volts, as opposed to conventional architectures (from 1 nm to 1.5 nm) which correspond to gate dielectrics for "low voltage" transistors intended to operate at voltages below 1.2 volts.

Circuits other than static RAM circuits belonging to the semiconductor device may incorporate "medium voltage" transistors, that is, transistors having a gate dielectric layer thickness between 3.5 nm and 6 nm and for operating at voltages between 1.2 volts and 1.8 volts, and optionally "low voltage" transistors, that is, transistors having a gate dielectric layer thickness between 1 nm and 1.5 nm and for operating at voltages between 0.5 volts and 1.2 volts.

According to one implementation, the active region extends along a first direction in the memory circuit so as to be combined with other unit memories and so as not to relax the compressive stress in the first direction of the silicon germanium alloy.

This corresponds to a “continuous active area” architecture for PMOS transistors, which allows exploiting compressive stresses in the channel length of the PMOS transistors, but which gives rise to the presence of an additional transistor by construction, called “gate tied”, which is advantageously connected to be always deactivated.

Furthermore, the first direction corresponds to the length of the channel of the transistor, ie the direction between the source and the drain of the transistor.

According to one implementation, the NMOS transistor and the PMOS transistor are respectively located in doped wells of a carrier substrate, and the device includes a bias circuit configured to generate voltages suitable for reverse biasing the PMOS and NMOS transistors in corresponding semiconductor wells of the carrier substrate.

The reverse bias generates a field effect in the active region, which is caused by the bias of the carrier substrate under the buried dielectric region. The reverse reverse bias allows to "slow down" the operation of the transistor by increasing its threshold voltage and reducing the current leakage in the channel of the transistor.

According to one embodiment, the NMOS transistor is located in a p-type doped well in a carrier substrate, the PMOS transistor is located in an n-type doped well in the carrier substrate, and the bias circuit is configured to generate a reverse back bias voltage between 0 volts and -2 volts in the p-type doped well and to generate a reverse back bias voltage between 0 volts and +2 volts in the n-type doped well.

According to one implementation, the bias circuit is configured to generate the voltage suitable for reverse biasing of the PMOS and NMOS transistors in a mode for retaining data fragments of the unit memory, but not in a read-write mode of the unit memory, and the bias circuit is configured to generate a power supply voltage for the unit memory having a nominal level in the read-write mode, and the power supply voltage has 50% to 85% of the nominal level in the mode for retaining data fragments.

According to another aspect, a method for manufacturing a semiconductor device of the silicon-on-insulator type is proposed, the semiconductor device comprising a semiconductor film separated from a carrier substrate by the buried dielectric region. At least one unit memory of a static RAM circuit comprising an NMOS transistor and a PMOS transistor is manufactured. The method comprises forming an active region in the respective semiconductor films and forming a gate dielectric layer having a thickness greater than 3 nanometers. The active region of the PMOS transistor is made of a silicon-germanium alloy.

According to one embodiment, the thickness of the gate dielectric layer of the NMOS transistor and the PMOS transistor between the active region and the gate conductive region is between 3.5 nanometers and 6 nanometers.

According to one embodiment, an active region is made by extending in a first direction in a memory circuit so as to be combined with other unit memories and not to relax the compressive stress in the first direction of the silicon germanium alloy.

According to one embodiment, the manufacture of NMOS transistors and PMOS transistors includes forming separately doped semiconductor wells in a carrier substrate, the PMOS and NMOS transistors are located in the wells with corresponding types of doping, and the method also includes manufacturing a bias circuit that can generate a voltage suitable for reverse biasing of the PMOS and NMOS transistors in the corresponding semiconductor wells of the carrier substrate.

According to one embodiment, the well in which the NMOS transistor is positioned has a p-type doping, the well in which the PMOS transistor is positioned has an n-type doping, and the bias circuit is fabricated to generate a reverse back bias voltage between 0 volts and -2 volts in the p-type doped well and to generate a reverse back bias voltage between 0 volts and +2 volts in the n-type doped well.

According to one embodiment, the bias circuit is manufactured to generate the voltage suitable for reverse biasing of the PMOS and NMOS transistors in a mode for retaining data fragments of the unit memory, rather than in a read-write mode of the unit memory, and the bias circuit is manufactured to generate a power supply voltage for the unit memory having a nominal level in the read-write mode, and the power supply voltage has 50% to 85% of the nominal level in the mode for retaining data fragments.

Reference is now made to the drawings.

FIG. 1 schematically shows a semiconductor device DSM of the silicon-on-insulator type, which includes an NMOS type transistor NM and a PMOS type transistor PM, which will be denoted by the terms “NMOS transistor” and “PMOS transistor” hereinafter.

In the silicon-on-insulator technology, NMOS transistors and PMOS transistors are made of a substrate structure comprising semiconductor films ACTn, ACTp which are separated from a carrier substrate SUB by a buried dielectric region BOX.

NMOS and PMOS transistors are particularly suitable for integrating the cell memory CLL of ultra-low leakage "SRAM" static RAM circuits.

In this respect, the NMOS transistor and the PMOS transistor each particularly include a gate dielectric layer or "region" EG having a thickness tEG greater than 3 nanometers, and also particularly, the PMOS transistor includes an active region ACTp in a corresponding semiconductor film made of a silicon-germanium alloy. In fact, the entire semiconductor film ACTp for the PMOS transistor is made of a silicon-germanium alloy.

For example, the gate dielectric layer EG of the NMOS transistor and the PMOS transistor has a thickness tEG between 3.5 nm and 6 nm, or even 7 nm, taken along the vertical direction Z between the active regions ACTn, ACTp and the gate conductive region RG (see below).

Advantageously, the gate dielectric layer EG has an equivalent electrical thickness of substantially 4 nanometers or less. The equivalent electrical thickness corresponds to the thickness t of a dielectric (e.g. SiO2 silicon dioxide) having a reference dielectric constant ε, thereby generating the same capacitance value C at an equal surface S according to the formula C=ε(S/t).

Therefore, a reduction in electrical thickness allows increasing the capacitance value of the dielectric layer, which is advantageous in terms of performance, without reducing the physical thickness of the dielectric layer, which is advantageous in terms of gate current leakage.

For example, in this regard, the gate dielectric layer EG may include a portion made of "SiON" silicon oxynitride (or _SiOxNy , typically _Si2O2N ) with a thickness between 1 nm and _4.5 nm, and a portion made of a "high _dielectric constant" (typically "high-k") dielectric (e.g. hafnium oxide) with a thickness of substantially 2.5 nm above the portion made of silicon oxide. A physical thickness of these materials of, for example, approximately 6 nm (3.5+2.5) corresponds to an equivalent electrical thickness of approximately 4 nm.

Furthermore, NMOS and PMOS transistors typically include a gate conductive region RG on a gate dielectric layer EG and including, for example, a layer made of metal and a volume of polysilicon, as well as a source S region and a drain D region implanted into the respective active regions ACTn, ACTp.

The active regions ACTn, ACTp are located in the semiconductor film of the silicon-on-insulator type substrate and are defined by a lateral isolation structure STI (usually a shallow isolation trench). The active region ACTn of the NMOS transistor is made of intrinsic silicon, for example.

Finally, the NMOS transistor is positioned facing the p-type doped well PW implanted in the carrier substrate SUB, and the PMOS transistor is positioned facing the n-type doped well NW implanted in the carrier substrate SUB, that is, in a configuration corresponding to a "conventional" structure of the well (as opposed to an "inverted" structure of the well in which the NMOS transistor is positioned facing the n-type well of the carrier substrate SUB and the PMOS transistor is positioned facing the p-type well of the carrier substrate SUB).

The "conventional" structure of the wells advantageously allows to realize the reverse reverse biasing of NMOS and PMOS transistors, since the junction PN between the wells is blocked under such biasing conditions (negative bias in a p-type doped well and positive bias in an n-type doped well). In this respect, the semiconductor wells PW, NW comprise respective contacts P+, N+, usually in an opening of a buried dielectric region BOX formed between two shallow isolation trenches STI and, for example, returning from a circuit comprising transistors NM, PM.

The reverse bias conditions BBn, BBp correspond to the field effects in the active areas ACTn, ACTp generated by the bias of the carrier substrate SUB (wells PW, NW) through the buried dielectric region BOX. The reverse reverse bias comprises a negative bias for NMOS transistors and a positive bias for PMOS transistors, which allows to "slow down" the operation of the transistors and reduce the current leakage to the carrier substrate SUB.

The semiconductor device DSM comprises a bias circuit ALM, for example inside a power supply circuit of the device, configured to generate voltages BBn, BBp suitable for reverse biasing of PMOS and NMOS transistors in respective semiconductor wells PW, NW of a carrier substrate SUB.

For example, the reverse bias voltage BBn applied to the NMOS transistor and applied in the p-type doped well PW is between 0 volts and -2 volts, and the reverse bias voltage BBp applied to the PMOS transistor and applied in the n-type doped well NW is between 0 volts and +2 volts.

Advantageously, the bias circuit ALM is configured to generate said voltages BBn, BBp for reverse back biasing of PMOS and NMOS transistors in a mode for holding data segments of said cell memory CLL, while generating no reverse biasing in a read/write mode of said cell memory CLL.

Furthermore, the bias circuit ALM may be configured to generate a power supply voltage VDD for the unit memory CLL, the power supply voltage VDD having a nominal level in a read/write mode and having 50% to 85% of the nominal level in a mode of retaining data segments.

Reference is made to Figure 2 in this regard.

FIG. 2 is a circuit diagram showing a memory cell CLL of an SRAM static RAM including an NMOS transistor and a PMOS transistor as shown in FIG. 1 .

The memory cell includes two "pull-up" PMOS transistors PU1, PU2 and two "pull-down" NMOS transistors PD1, PD2 connected between a power supply terminal VDD and a ground terminal GND so as to form two top-to-tail inverters. The output node N1 (or "first data segment node N1") of the first inverter PU1, PD1 is coupled to the input of the second inverter PU2, PD2, and the output node N2 (or "second data segment node N2") of the second inverter PU2, PD2 is coupled to the input of the first inverter PU1, PD1.

Furthermore, the cell CLL conventionally comprises two access NMOS transistors PG1, PG2, allowing selection of the cell for reading and writing. The first access transistor PG1 is coupled between the bit line BL1 and the first data node N1 and is controlled by a signal transmitted on the word line WL. The second access transistor PG2 is coupled between the further bit line BL2 and the second data node N2 and is controlled by a signal transmitted on the word line WL.

Writing and reading of data segments in the cell CLL are performed via access transistors PG1, PG2 by measuring a voltage level of at least one of the data segment nodes N1, N2 via the corresponding bit lines BL1, BL2 during reading, and by applying a voltage level to at least one of the data segment nodes N1, N2 via the corresponding bit lines BL1, BL2 during writing.

Retention of the data fragment in the memory cell is obtained by the stable state of the signal generated on the data nodes N1, N2 of the assembly of two top-to-tail inverters PU1-PD1, PU2-PD2.

In the read and write mode, the supply voltage VDD is generated by the bias circuit ALM at a nominal level, ie a normal operating level of the transistors PU1, PD1, PU2, PD2, for example between 0.8 Volt and 1.2 Volt, preferably 0.8 Volt.

In the retention mode of the SRAM cell, the supply voltage VDD is generated by the bias circuit ALM at an economical level, for example 50% to 85% of the nominal level, that is to say between 0.4 Volt and 1.0 Volt, preferably substantially 0.6 Volt.

FIG. 3 shows an example of a layout in a top view of the circuit of the memory cell CLL as described above with respect to FIGS. 1 and 2 .

The same elements have the same reference numerals as in FIGS. 1 and 2 and will not be described again in detail here.

It is particularly noteworthy that the active regions ACTn (Si), ACTp (SiGe) extend on either side of the outline of the memory cell CLL along the first direction L in the memory circuit, thereby incorporating adjacent unit memories (extending to the left and right of the cell CLL in the direction of Figure 3).

This corresponds to a "continuous active region" structure of the active region made of silicon-germanium alloy ACTp (SiGe) of the PMOS transistor.

This allows not to relax the compressive stress in the first direction L of the silicon-germanium alloy ACTP (SiGe), and thus utilizes the improvement of the performance of the PMOS transistor, especially the reduction of the threshold voltage of the PMOS transistor and the low variability of the threshold voltage of the PMOS transistor.

However, this results in the generation of a "parasitic" transistor GT1, GT2 in each active area ACTp of the functional pull-up PMOS transistor PU1, PU2 for the cell CLL. The two parasitic PMOS transistors GT1, GT2 are deactivated by connecting their gates and their sources to the power supply voltage terminal VDD and are generally referred to in this context as "gate-connected transistors". In FIG. 2 , the parasitic PMOS transistors GT1, GT2 are shown in dotted lines because they exist but they are in a deactivated state.

The gate-connected transistors GT1, GT2 may introduce additional leakage current into the leakage current of the memory cell CLL in the off mode or the holding mode (generally the "off-state mode"), but the consumption of the memory cell in the read/write mode is negligible. That is, even in the off mode or the holding mode, the leakage of the "gate-connected" transistors is low due to the thickness of their gate dielectric layer being greater than 3 nanometers and the large gate length (in the first direction L), for example greater than 100 nm.

The first direction L corresponds to the length of the transistor, ie the source-drain direction of the transistor. The width W of the transistor is defined by the extension of the active area in a second direction W perpendicular to the first direction L and the vertical direction Z.

For example, the NMOS and PMOS transistors of the cell CLL may have a channel length in a first direction L between 100 nm and 200 nm, and a channel width in a second direction W between 100 nm and 200 nm. The length (L) and width (W) of the transistors of the cell CLL are relatively large, but relative to the thickness of the gate dielectric layer EG, allowing to ensure, respectively, a good electrostatic control of the carriers in the channel (and therefore less leakage between the source and drain regions), and a conduction current sufficient for the operation of the SRAM memory cell.

That is, the current leakage in the memory cell CLL as described with respect to FIGS. 1 to 3 is extremely low, eg, substantially times less than the current leakage of an “ultra-low leakage” memory cell.

Reference is made to Figure 4 in this regard.

4 shows results of the intensity of the current leakage ISB in picoamperes (10-12 A) of the memory cell CLL as described above with respect to FIGS. 1 to 3 in retention mode, depending on the level of the supply voltage VDD, in volts, and for various reverse back biases BBn/BBp.

It should be noted that in the retention mode at a power supply voltage VDD of 0.6 volts, at a reverse bias voltage of BBn=2 volts and BBp=+2 volts (BBn/BBp: 2/2), the intensity of the current leakage ISB in the memory cell CLL is substantially 24 femtoamperes (24×10-15 A).

For comparison, a cell of a conventional ultra-low leakage SRAM memory using FDSOI technology has a leakage of about 1 to 1.5 picoamps in retention mode. In other words, the memory cell CLL described above with respect to Figures 1 to 3 has a current leakage that is a factor of 50 less than conventional technology.

It is also noted that other power supply voltage VDD and/or reverse bias BBn/BBp conditions give satisfactory results. For example: in the case of a power supply voltage VDD of 0.8 volts and a reverse bias of BBn/BBp: 2/2, the intensity of the current leakage ISB in the memory cell CLL is less than 100 femtoamperes; in the case of a power supply voltage VDD of 0.6 volts and a reverse bias of BBn/BBp: 1/1, the intensity of the current leakage ISB in the memory cell CLL is less than 1 picoampere.

FIG. 5 shows a simplified example of a method for manufacturing a semiconductor device DSM as described above with respect to FIGS. 1 to 4 , in particular the manufacturing of NMOS and PMOS transistors of a memory cell CLL.

In step 101, a silicon-on-insulator type substrate including a semiconductor film made of intrinsic silicon (ACT) is prepared, the semiconductor film being separated from a carrier substrate SUB by a buried dielectric region BOX.

In step 103, the material (initial intrinsic silicon) in the active area ACTp of the future PMOS transistor is modified, for example, via a technique commonly known as "condensation". This condensation technique first consists in selectively growing silicon germanium by epitaxy on a semiconductor film made of intrinsic silicon in the area receiving the PMOS transistor. Then, the germanium is diffused deep (downward) in the semiconductor film. The diffusion is carried out by oxidizing the epitaxial area, then the oxide thus generated is removed and an active area ACTp made of a silicon-germanium alloy is locally formed. The active area ACTn of the future NMOS transistor remains in intrinsic silicon.

In step 103 , shallow isolation trenches STI are also formed in order to define the active areas ACTn, ACTp of the future NMOS and PMOS transistors and the contacts in the future wells of the carrier substrate SUB.

In step 105 , wells NW, PW are formed in the carrier substrate SUB by implanting dopants of corresponding types.

In step 107 , the gate dielectric layer EG of the future NMOS and PMOS transistors is formed, for example by depositing a dielectric layer EG or a superposition of dielectric layers with a total thickness greater than 3 nm, for example between 3.5 nm and 4.5 nm, over the entire front side of the substrate.

In step 109 , gate conductive regions RG of the NMOS and PMOS transistors are formed, for example, by depositing a conductive structure RG on the entire dielectric layer EG, which conductive structure RG may include a metal layer and a polysilicon volume on top.

The various structures of the gates EG, RG of the NMOS and PMOS transistors are then defined by etching, typically by photolithography, to remove the gate conductive region RG and the gate dielectric layer EG in the portion located outside the mask pattern. In FIG3 , the area filled with the most closely ascending oblique hatching (“RG” in FIG1 ) represents the etching result of the gate structures EG, RG, and substantially corresponds to the pattern of the mask.

After defining the structures of the gates EG, RG of the NMOS and PMOS transistors, the source and drain regions S/D are implanted into the active regions ACTn, ACTp on the gate structures EG, RG in a self-aligned manner, that is, into the portions of the active regions ACTn, ACTp that are not masked by the gate structures EG, RG.

On the one hand, the NMOS and PMOS transistors of the memory cell are electrically connected via vertical metal vias and metal tracks, such as shown in FIG. 3 , where the squares filled with crosses in the two diagonals correspond to the locations of the vias, and where the areas filled with the least dense rising oblique hatched lines (VDD, N1, N2, WL, BL1, BL2) correspond to the metal tracks.

Thus, in step 111, the memory cell CLL is functional and may be powered, for example, with a supply voltage VDD between 0.8 volts and 1.2 volts (0.8 V ≤ VDD ≤ 1.2 V) in a read/write operation mode without reverse bias (BBn=BBp=0 V), and with a supply voltage VDD of substantially 0.6 volts (VDD=0.6 V) in a retention operation mode, and with a reverse back bias BBn, BBp of substantially 2 volts in the p-type well PW, and with a reverse back bias BBn, BBp of substantially +2 volts in the n-type well NW (BBn=2 V; BBP=+2 V).

Furthermore, the method for manufacturing a memory cell advantageously uses manufacturing steps that can also already be planned in conventional manufacturing methods and is therefore performed in a fully co-integrated manner and without additional costs. In practice, the circuits of the semiconductor device DSM other than the static RAM circuits may include "medium voltage" transistors, that is to say transistors having a gate dielectric layer with a thickness between 3.5 nm and 4.5 nm and for operation at voltages between 1.2 volts and 1.8 volts, for which the manufacturing steps correspond substantially to the manufacturing steps 101-111 of NMOS and PMOS transistors. Furthermore, other circuits of the semiconductor device DSM may include "low voltage" transistors, that is to say transistors having a gate dielectric layer with a thickness between 1 nm and 1.5 nm and for operation at voltages between 0.5 volts and 1.2 volts.

One aspect of the present disclosure provides a method for operating a static random access memory, wherein the static random access memory is formed by an NMOS transistor and a PMOS transistor arranged on a surface of a semiconductor film, wherein the semiconductor film is separated from a carrier substrate by a buried dielectric region, wherein the NMOS transistor and the PMOS transistor each include a gate dielectric layer having a thickness greater than 3 nanometers and an active region in the semiconductor film, and wherein the active region of the PMOS transistor includes a silicon-germanium alloy, the method comprising: operating the memory in a read-write mode, wherein the NMOS transistor and the PMOS transistor are reverse biased to a nominal voltage in the read-write mode; and operating the memory in a retention mode, wherein the NMOS transistor and the PMOS transistor are reverse biased to a voltage of 50% to 85% of the nominal voltage in the retention mode.

According to one or more embodiments, the method further includes applying a reverse back bias voltage between 0 volts and -2 volts to the p-type doped well of the NMOS transistor.

According to one or more embodiments, the method further includes applying a reverse back bias voltage between 0 volts and +2 volts to the n-type doped well of the PMOS transistor.

According to one or more embodiments, the semiconductor film is separated from a carrier substrate by a buried dielectric region, and the method includes: forming an NMOS transistor and a PMOS transistor on a surface of the semiconductor film; and coupling the NMOS transistor and the PMOS transistor together to form a plurality of static random access memory SRAM cells; wherein the NMOS transistor and the PMOS transistor each include a gate dielectric layer having a thickness greater than 3 nanometers; wherein the NMOS transistor includes an active region of silicon in the semiconductor film; and wherein the PMOS transistor includes an active region of a silicon-germanium alloy in the semiconductor film.

According to one or more embodiments, forming the NMOS transistor and the PMOS transistor includes: modifying the silicon film in the area of the active area of the PMOS transistor to form the silicon-germanium alloy; forming a shallow isolation trench to define the active area; forming an n-type doped well of the PMOS transistor in the carrier substrate; forming a p-type doped well of the NMOS transistor in the carrier substrate; forming the gate dielectric layer; forming a gate conductive layer on the gate dielectric layer; patterning the gate conductive layer to form a gate conductive region; forming a source region and a drain region for the NMOS transistor and the PMOS transistor; and interconnecting the NMOS transistor and the PMOS transistor to form the SRAM cell.

According to one or more embodiments, wherein modifying the silicon film includes performing a condensation technique.

According to one or more embodiments, the gate dielectric layer is formed to a thickness between 3.5 nm and 6 nm.

According to one or more embodiments, the active region is formed to extend along a first direction so as to incorporate a plurality of the SRAM cells.

According to one or more embodiments, the active region is formed to extend along the first direction so as not to relax compressive stress of the silicon-germanium alloy in the first direction.

According to one or more embodiments, the method further includes fabricating a bias circuit electrically coupled to the n-type doped well of the PMOS transistor and the p-type doped well of the NMOS transistor.

Embodiments propose SRAM memory technology with even lower energy consumption, for example in data retention mode.

In one embodiment, a semiconductor device includes a carrier substrate, a buried dielectric region covering the carrier substrate, and a semiconductor film separated from the carrier substrate by the buried dielectric region. An NMOS transistor and a PMOS transistor are disposed on a surface of the semiconductor film and coupled together to form a static random access memory (SRAM) cell. The NMOS transistor and the PMOS transistor each include a gate dielectric layer having a thickness greater than 3 nanometers and an active region in the semiconductor film. The active region of the PMOS transistor is formed of a silicon germanium alloy.

Another embodiment provides a method for operating a static random access memory, which is formed by an NMOS transistor and a PMOS transistor disposed on the surface of a semiconductor film, and the semiconductor film is separated from a carrier substrate by a buried dielectric region. The NMOS transistor and the PMOS transistor each include a gate dielectric layer having a thickness greater than 3 nanometers and an active region in the semiconductor film. The active region of the PMOS transistor includes a silicon-germanium alloy. The method includes operating the memory in a read-write mode and operating the memory in a retention mode. The NMOS transistor and the PMOS transistor are reverse biased to a nominal voltage in the read-write mode, and the NMOS transistor and the PMOS transistor are reverse biased to a voltage of 50% to 85% of the nominal voltage in the retention mode.

Another embodiment provides a method for forming a semiconductor device in a semiconductor film, wherein the semiconductor film is separated from a carrier substrate by a buried dielectric region. The method includes forming an NMOS transistor and a PMOS transistor on a surface of the semiconductor film, and coupling the NMOS transistor and the PMOS transistor together to form a plurality of static random access memory (SRAM) cells. The NMOS transistor and the PMOS transistor each include a gate dielectric layer having a thickness greater than 3 nanometers. The NMOS transistor includes a silicon active region in the semiconductor film, and the PMOS transistor includes a silicon germanium alloy active region in the semiconductor film.

In summary, the realization of a static RAM cell of a semiconductor device DSM of FDSOI type has been described, comprising an NMOS transistor and a PMOS transistor in a configuration with a regular well, allowing a reverse bias to be applied independently to the NMOS and PMOS transistors. A thickness of the gate dielectric layer EG greater than 3 nanometers allows the elimination of gate current leakage. The active area ACTp of the PMOS transistor made of a silicon-germanium alloy under compressive stress in the channel direction L allows the threshold voltage of the PMOS transistor to be reduced, and thus sufficient stability in reading and writing is ensured. The continuous active area ACTp structure of the PMOS transistor allows the relaxation of the compressive stress of the silicon-germanium alloy to be avoided, which therefore avoids variability and increase in the threshold voltage of the PMOS transistor. In addition, the method for manufacturing a memory cell can use conventional manufacturing steps, and is therefore implemented in a fully co-integrated manner without additional dedicated costs.

Claims (12)

1. A semiconductor device, comprising: a carrier substrate; a buried dielectric region covering the carrier substrate; a semiconductor film separated from the carrier substrate by the buried dielectric region; and An NMOS transistor and a PMOS transistor are arranged at the surface of the semiconductor film and coupled together to form a static random access memory SRAM cell, each of the NMOS transistor and the PMOS transistor comprising a gate dielectric layer having a thickness greater than 3 nanometers and an active region in the semiconductor film. 2 . The semiconductor device according to claim 1 , wherein the gate dielectric layer of the NMOS transistor and the PMOS transistor has a thickness between the active region and the gate conductive region of between 3.5 nanometers and 6 nanometers. 3 . The semiconductor device according to claim 1 , further comprising a plurality of additional PMOS transistors, wherein the active regions of the plurality of PMOS transistors extend along a first direction. 4. The semiconductor device according to claim 3, characterized in that the further PMOS transistor is coupled to a further NMOS transistor to form a further SRAM cell, wherein the active area of the further PMOS transistor and the active area of the NMOS transistor extend along the first direction so as to be incorporated into other SRAM cells. 5 . The semiconductor device according to claim 3 , wherein the active regions of the plurality of PMOS transistors extend along the first direction so as not to relax the compressive stress in the first direction. 6 . The semiconductor device according to claim 1 , wherein the NMOS transistor and the PMOS transistor are respectively located in doped wells of the carrier substrate, and the device further comprises a bias circuit coupled to the doped wells of the carrier substrate. 7 . The semiconductor device according to claim 6 , wherein the bias circuit is configured to generate voltages suitable for reverse biasing of the PMOS and NMOS transistors in the corresponding doped wells of the carrier substrate. 8 . 8 . The semiconductor device according to claim 6 , wherein the NMOS transistor is located in a p-type doped well in the carrier substrate, and the PMOS transistor is located in an n-type doped well in the carrier substrate. 9 . The semiconductor device of claim 8 , wherein the bias circuit is configured to generate a reverse bias voltage between 0 volts and −2 volts in the p-type doped well. 10 . The semiconductor device of claim 8 , wherein the bias circuit is configured to generate a reverse back bias voltage between 0 volts and +2 volts in the n-type doped well. 11. The semiconductor device according to claim 6, wherein the bias circuit is configured to generate a voltage suitable for reverse biasing of the PMOS and NMOS transistors in a mode for retaining a data segment of the memory cell rather than in a read/write mode of the memory cell. 12. The semiconductor device according to claim 6, characterized in that the bias circuit is configured to generate a power supply voltage for the memory cell, the power supply voltage having a nominal level in a read/write mode and having a voltage of 50% to 85% of the nominal level in a mode for retaining data fragments.